JPH04277850A - Descriptor control system - Google Patents

Abstract

PURPOSE:To reduce overhead to the error frame of a host system, to improve efficiency for using an outside storage area 9 and to considerably improve system efficiency so as to report only the valid received frame to the host system. CONSTITUTION:A DMA controller 1 is connected through a bus 8 to an outside storage area 9. This outside storage area 9 is equipped with a descriptor 10 or a reception buffer area 11 and further, the descriptor 10 is equipped with a command area 12 having an overwrite select bit 13, address area 14, transfer size area 15 and status area 16. On the other hand, the DMA controller 1 reads information containing the overwrite select bit 13 in the command area 12 into a control register 3 and DMA-transfers only the valid frame in received frames to the reception buffer area 11 by selecting the address of the descriptor 10 by a descriptor address selecting circuit 7 together with the set data of a descriptor address register 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a descriptor control system, and more particularly to a descriptor control system that uses descriptors to control a direct memory access controller (hereinafter referred to as a DMA controller).

0002

2. Description of the Related Art Conventionally, when a DMA controller continuously accesses a buffer area on an external storage area, in order to prevent system efficiency from decreasing due to the host system controlling the DMA controller in real time, DMA using descriptor control has been used. A controller control method has been proposed. For example, when continuously receiving HDLC frames in a communication system, the received frames are successively transferred to a plurality of buffer areas on an external storage area by direct memory access (hereinafter referred to as DMA) under descriptor control. That is, the host system sets information of a plurality of descriptors in advance in a continuous area on the external storage area based on a predetermined descriptor format.

FIG. 3 is a configuration diagram of a DMA controller and an external storage area for explaining an example of such a conventional system. As shown in FIG. 3, the DMA controller 1 is connected to an external storage area 9 via a bus 8, and the external storage area 9 stores a plurality of descriptors 10 and a reception buffer area 11.
Contains. The format of each descriptor 10 includes a command area 12 that stores control information for the DMA controller 1, an address area 14 that indicates the start address of the buffer area 11 that stores transfer data, and a transfer size area 15 that stores the number of transfer data. It also includes a status area 16 for storing execution results of DMA transfer. Data in the command area 12 in the descriptor 10 of the external storage area 9 is transferred to the control register 3 of the DMA controller 1, and similarly, data in the address area 14 and transfer size area 15 are transferred to the DMA address register 4 and DMA size register, respectively. Transferred to 5.

FIG. 4 is a diagram showing the correspondence between the descriptor of the external storage area shown in FIG. 3 and the reception buffer area. As shown in FIG. 4, the DMA controller 1 uses descriptor 1
All frames corresponding to 0 (10A to 10H) are reported to the host system, and the receive buffer area 1
1 (11A to 11H). In other words, not only valid frames but also error frames are written.

First, the host system sets the start address of descriptor 10 to be executed first as a descriptor.
Set address register 2 and DMA controller 1
Start. This DMA controller 1 changes the set value of the descriptor address register 2 to the DMA address.
Load register 4 and load the predefined size n of descriptor 10 into DMA size register 5. Thereafter, the set value of the descriptor address register 2 is rewritten by the adder 6 to a value incremented by the size n. This allows DM
The A controller 1 starts DMA transfer for the number of data set in the DMA size register 5 from the address set in the DMA address register 4. By this first DMA transfer, the command area 12, address area 14, and
The transfer size area 15 is read into the DMA controller 1. Again, the DMA controller 1 sets the read information of the command area 12 in the control register 3, and similarly sets the information of the address area 14 and transfer size area 15 in the DMA address register 4 and DMA size register 5, respectively. Start DMA transfer again. By this second DMA transfer, each data of the received frame is stored in the reception buffer area 11 on the external storage area 9 specified by the descriptor 10.

[0006] When the transfer of the received data is completed by the second DMA transfer, the D is transferred as the third DMA transfer.
The MA controller 1 DMA-transfers the number of data actually transferred in the second DMA transfer to the transfer size area 15, and information regarding the execution result of the DMA transfer and the received frame to the status area 16. One reception buffer area 11 is created by the series of operations of three DMA transfers described above.
data transfer is completed.

Next, if the control information stored in the control register 3 further specifies DMA transfer chaining using the descriptor 10, the DMA controller 1 stores the address following the descriptor 10, that is, the descriptor address register 2. The value stored in the DMA address register 4 is set to the value stored in the DMA address register 4, and the descriptor information stored in the address following the descriptor 10 is read out. Furthermore, based on this information, the DMA is used to transfer data to the designated reception buffer area 11.
Start the transfer. In this way, chaining of DMA transfers is continuously executed until the end of chaining is instructed by the control information of the DMA controller 1 specified by the command information 12 of the descriptor 10.

[0008]

[Problems to be Solved by the Invention] In the conventional descriptor control method described above, when a plurality of descriptors are chained, consecutively received frames are sequentially received in an external storage area based on the information of each descriptor. DMA transfer is being performed to the buffer area.

However, in a normal communication system, a received frame may be received as an error frame due to the influence of the transmission path and the processing capabilities of the transmitting and receiving sides. However, on the receiving side, it is not possible to determine whether or not a frame is an error frame until the reception of one received frame is completed, so as soon as the reception of the received frame starts, the received frame is transferred to the reception buffer area on the external storage area by DMA transfer. is being transferred to. Therefore, error frames, that is, invalid frames, exist in the plurality of reception buffer areas on the external storage area in addition to normal reception frames. For this reason, there are disadvantages in that the usage efficiency of the receive buffer area on the external storage area deteriorates, the overhead of the host system related to error frame processing increases, and the effective efficiency of the entire system decreases.

An object of the present invention is to provide a descriptor control method that can reduce the overhead of such a host system, make effective use of external storage areas, and improve system efficiency.

[0011]

[Means for Solving the Problems] The descriptor control system of the present invention includes an external storage area having a plurality of descriptors and a reception buffer area that are successively set in advance, and a descriptor control system that is connected to the external storage area by a bus and that stores the descriptors. a first storage means for storing a start address; a second storage means for storing control information stored in the descriptor; an addition means for calculating a start address of a descriptor next to the descriptor; a direct memory access controller having descriptor address selection means for determining the execution result of the access transfer and selecting a start address of the two descriptors, By retaining overwrite selection bit information in the descriptor of the external storage area that specifies that DMA transfer by the descriptor can be repeatedly executed, the direct memory access transfer can be performed multiple times by the descriptor. configured.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a DMA controller and an external storage area for explaining one embodiment of the present invention. As shown in FIG. 1, this embodiment uses a DMA controller 1
and an external storage area 9 are connected by a bus 8, and the external storage area 9 has a command area 12 and an address area 14.
, a descriptor 10 including a transfer size area 15 and a status area 16, and a reception buffer area 11. In particular, this command area 12 includes an overwrite selection bit 13. This overwrite selection bit 13 determines whether overwriting of the receive buffer area 11 in which error frames are stored is possible. That is, if overwrite selection bit 13 is inactive, the received frame will be descriptor 1.
The received frame is transferred to the receive buffer area 11 with the address specified in the address area 14 of 0 as the first address, and the next received frame is DMA transferred based on the information of other descriptors stored in the address following the descriptor 10. In addition, if the overwrite selection bit 13 is active, only if the received frame is an error frame, the next received frame will also be placed in the receive buffer area 11 whose starting address is the address specified in the address area 14 of the descriptor 10. will be forwarded to. On the other hand, DMA
In comparison with the conventional example shown in FIG. The difference is that a descriptor address selection circuit 7 for selection is added, and the rest is the same.

When the DMA controller 1 controlled by the descriptor 10 of the external storage area 9 described above continuously stores only valid reception frames in the reception buffer area 11 and discards all error frames, the host system First, all overwrite selection bits 13 of each descriptor 10 are set to active. Thereafter, the DMA controller 1 is started, and the plurality of descriptors 10 on the continuous external storage area 9 start transferring to each receive buffer area 11 on the external storage area 9 specified by each descriptor 10. Each descriptor 10
If an error frame is received during successive DMA transfers by chaining, the chaining is interrupted and the next received valid frame is transferred to the receive buffer area 11 specified by the descriptor 10. The frame is retransmitted and chaining of descriptors 10 is continued again. The operation in such a case will be explained below.

The host system sets the start address of the descriptor 10 to be executed first in the descriptor address register 2, and starts the DMA controller 1. This DMA controller 1 transfers the setting value of the descriptor address register 2 to the DMA address register 4, and also transfers the setting value of the descriptor address register 2 to the DMA address register 4
The size n of each is loaded into the DMA size register 5. The DMA controller 1 starts DMA transfer by the number of data set in the DMA size register 5 from the address set in the DMA address register 4. By this first DMA transfer, the command area 12, address area 14, and transfer size area 15 of the designated descriptor 10 on the external storage area 9 are read into the DMA controller 1. The DMA controller 1 sets the read information of the command area 12 to the control register 3, the information of the address area 14 to the DMA address register 4, and the information of the transfer size area 15 to the DMA size register 5. Start DMA transfer. By this second DMA transfer, the received data is transferred to the receive buffer area 11 on the external storage area 9 designated by the descriptor 10.

[0016] When the transfer of the received frame is completed by the second DMA transfer, it is checked whether or not this received frame is an error frame. If it is not an error frame, as the third DMA transfer, the DMA controller 1 records the number of data actually transferred in the second DMA transfer in the transfer size area 15, and also records information regarding the execution result of the DMA transfer and the received frame in the status. Area 1
6, respectively. One reception buffer area 11 is created by the series of operations of three DMA transfers described above.
data transfer is completed. After this, the address following this descriptor 10, that is, the adder 6 of the DMA controller 1 is used to register the descriptor address register 2.
A value obtained by adding the size n of the descriptor 10 to the set value is designated by the descriptor address selection circuit 7 and transferred to the DMA address register 4 and the descriptor address register 2. Therefore, the next received frame is transferred by DMA using the new descriptor 10 information.

On the other hand, if the received frame is an error frame, the DMA controller 1 ends the series of operations regarding the descriptor 10 without performing the third DMA transfer. Thereafter, the set value of the descriptor address register 2 is selected by the descriptor address selection circuit 7 as the start address of the next descriptor 10 and transferred to the DMA address register 4. At this time, the contents of descriptor address register 2 are not updated. Therefore, the DMA controller 1 again uses descriptor 10 as the next descriptor.
It is read by transfer and performs DMA transfer for the next received frame. In this way, the DMA controller 1 repeatedly transfers DMA data to the same receive buffer area 11 based on the information in the descriptor 10 until it receives an error-free frame.
Since the transfer is performed, only valid received frames are stored in the receive buffer area 11 on the external storage area 9.

FIG. 2 is a correspondence diagram of the descriptor of the external storage area shown in FIG. 1 and the reception buffer area. As shown in FIG. 2, in the descriptor control method of this embodiment,
Since the reception of error frames is not reported to the host system, and only valid received frames 11A to 11D are reported, it is possible to reduce the overhead related to error frame processing in the host system. Since only valid frames 11A to 11D are stored in the reception buffer area 11 on the external storage area 9, the unused areas 11E to 11H are increased and the usage efficiency of the external storage area 9 is improved, thereby greatly improving system efficiency. Is possible.

Furthermore, in the present embodiment described above, the status area 1 is transferred from the descriptor 10 of the external storage area 9 shown in FIG.
It is also possible to configure by deleting 6. In this case, the host system sets the start address of the descriptor 10 to be executed first in the descriptor address register 2, and starts the DMA controller 1, as in the above-described embodiment. The DMA controller 1 stores the setting value of the descriptor address register 2 in the DMA address register 4, and also stores the predefined size n of the descriptor 10 in the DMA size register 5.
Load each into As a result, the DMA controller 1 starts DMA transfer of the number n of data set in the DMA size register 5 from the address set in the DMA address register 4. By this first DMA transfer, data in the command area 12, address area 14, and transfer size area 15 of the designated descriptor 10 on the external storage area 9 is read into the DMA controller 1. The DMA controller 1 transfers the read information of the command area 12 to the control register 3 and also transfers it to the address area 1.
4 is set in the DMA address register 4, and information in the transfer size area 15 is set in the DMA size register 4, and DMA transfer is started again. By this second DMA transfer, the received frame is transferred to the receive buffer area 11 on the external storage area 9 specified by the descriptor 10. When the transfer of the received frame is completed by this second DMA transfer, it is determined whether the received frame is an error frame. If it is not an error frame, as the third DMA transfer, the DMA controller 1 transfers information regarding the number of data actually transferred in the second DMA transfer and the execution results to a prespecified external storage area 9 other than the descriptor 10. Forward. This method is used for the second DMA of each descriptor 10.
This is effective when the amount of information regarding transfer execution is variable. Thereafter, the address following this descriptor 10, that is, the value obtained by adding the size n of the descriptor 10 to the setting value of the descriptor address register 2 by the adder 6, is specified by the descriptor address selection circuit 7, and the DMA address Transferred to register 4 and descriptor address register 2. Therefore, the next received frame is transferred by DMA using the new descriptor 10 information. On the other hand, if the received frame is an error frame, the DMA controller 1 ends the series of operations related to the descriptor 10 without performing the third DMA transfer. After this, the next descriptor 10
The set value of the descriptor address register 2 is selected by the descriptor address selection circuit 7 as the start address of the DMA address register 4, and is transferred to the DMA address register 4. At this time, the contents of descriptor address register 2 are not updated. Therefore, DMA controller 1 again selects descriptor 1 as the next descriptor.
0 is read by DMA transfer, and DMA transfer is performed for the next received frame. In this way, DMA controller 1
repeats the same receive buffer area 1 based on the information in descriptor 10 until it receives an error-free frame.
Since DMA transfer is performed in 1, only valid received frames can be stored in the receive buffer area 11 on the external storage area 9.

[0020]

As explained above, the descriptor control method of the present invention allows the descriptor to be re-executed to be specified in advance by the overwrite selection bit in the descriptor, thereby controlling multiple Even if an error frame is received during DMA transfer to multiple receive buffer areas on an external storage area based on descriptor chaining, the next valid frame to be received will be retransferred only to that receive buffer area. , the interrupted descriptor chaining can be continued again. Therefore, only valid received frames are reported without reporting to the host system that an error frame has been received, which has the effect of reducing the overhead associated with error frame processing in the host system. Moreover, since only valid frames are stored in the reception buffer area on the external storage area, there is an effect that the usage efficiency of the external storage area can be improved and the system efficiency can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a DMA controller and an external storage area for explaining one embodiment of the present invention.

FIG. 2 is a correspondence diagram of a descriptor of an external storage area and a reception buffer area shown in FIG. 1;

FIG. 3 is a configuration diagram of a DMA controller and an external storage area for explaining a conventional example.

FIG. 4 is a correspondence diagram of a descriptor of an external storage area and a reception buffer area shown in FIG. 3;

[Explanation of symbols]

1 DMA controller 2 Descriptor address register 3
Control register 4 DMA address register 5 DMA size register 6 Adder 7 Descriptor address selection circuit 8
Bus 9 External storage area 10 Descriptor 11 Receive buffer area 12 Command area 13 Overwrite selection bit 14 Address area 15 Transfer size area 16 Status area

Claims (1)

[Claims] 1. An external storage area having a plurality of descriptors and a reception buffer area that are consecutively set in advance; a first storage means connected to the external storage area by a bus and storing a start address of the descriptor; a second storage means for storing control information stored in a descriptor; an addition means for calculating a start address of a descriptor next to the descriptor; and a second storage means for determining the execution result of the direct memory access transfer by the descriptor; a direct memory access controller having descriptor address selection means for selecting a start address of a descriptor, and the DMA transfer using the descriptor can be repeatedly executed based on the execution result of the direct memory access transfer. A descriptor control method characterized in that the direct memory access transfer is performed a plurality of times using the descriptor by holding specified overwrite selection bit information in the descriptor of the external storage area.