JP2002183080A - Data transfer controlling device and data transferring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA controller (data transfer controlling device) capable of accelerating a DMA transferring speed in spite of reducing a load on a CPU. SOLUTION: In registers SREG1, SREG2, EREG1 and EREG2, two sets of the starting address and the finishing address of a main memory are prepared. Selectors SEL1 and SEL2 switch between the starting address A and the finishing address A of the storage area A of the main memory and the starting address B and the finishing address B of the storage area B of the main memory. An address counter AC1 generates a destination address increased sequentially with the starting address of one set as a start point and outputs it to an arbiter 45. The arbiter 45 controls a memory control circuit to carry out DMA transfer to the destination address of the main memory. The load on the CPU 17 is reduced and the DMA transfer rate is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DMA controller in an image processing integrated circuit such as a digital camera.

[0002]

2. Description of the Related Art FIG. 11 is a schematic block diagram of a general digital still camera. As shown, in the digital still camera 100, a CCD (Charge-Couple) is used.
After an image signal captured by an image sensor 105 such as a pled device) sensor or a CMOS sensor is A / D converted into a digital signal, the image processing unit 106 performs various pixel interpolation processing, color space conversion processing, contour enhancement processing, and the like. Image processing is performed. The image data subjected to such image processing is thinned out and displayed in a viewfinder on the liquid crystal monitor 109 or the like, or JPEG (Joint Photographic Experts).
Group) and stored in a memory card 110 such as a nonvolatile memory or output to an external device such as a personal computer via an interface 111. In FIG.
Reference numeral 1 denotes an optical lens, 102 denotes a color correction filter, 103 denotes an optical LPF (low-pass filter), 104 denotes a color filter array, and 107 denotes a driving unit that drives and controls the image sensor 105 and the like.

When the image sensor 105 is driven by the interlace method, the first field and the second field are transferred to and stored in the main memory 108, and then the image processing section 10 is driven.
6 reads out the first and second fields and performs image processing such as the above-described pixel interpolation processing, or temporarily transfers and stores the first field in the main memory 108, and then the image processing unit 106 The first data stored in the main memory 108 in synchronization with the reading of the second field
Or reading a field. At this time, the main memory 1
Data transfer between the image processing unit 08 and the image processing unit 106 by DMA.
(Direct memory access), which reduces the load on the CPU (not shown), transfers data at high speed, and increases the image processing speed.

[0004]

However, in the conventional DMA system, each time a DMA transfer of image data having a predetermined capacity is performed once, the CPU starts the start address of a storage area on the main memory 108 for storing the image data. And the end address had to be specified. Therefore, when the image data is DMA-transferred a plurality of times, the CPU performs software processing to make (n + 1) by the software process before the destination address of the DMA reaches the end address at the time of the n-th (n ≧ 1) DMA transfer.
It is necessary to specify the start address of the next storage area in preparation for the second DMA transfer. In such a case, when small-capacity image data is frequently DMA-transferred, or when image data is divided into small areas and DMA-transferred, the CPU must frequently rewrite the start address and the end address. The load on the CPU increases, and the data is
There arises a problem that it is difficult to perform MA transfer.

In view of the above problems, the present invention seeks to solve the problem while reducing the load on the CPU while reducing the load on the CPU.
Another object of the present invention is to provide a DMA controller (data transfer control device) that can increase the MA transfer speed.

[0006]

In order to solve the above-mentioned problems, the invention according to claim 1 controls data transfer via a bus between a main memory for storing an image signal output from an image sensor and an internal module. A data transfer control device for storing a plurality of sets of start addresses and end addresses of each of a plurality of storage areas in the main memory, and a set of start addresses and end addresses among the plurality of sets. A selection circuit to select, an address counter that generates and outputs a destination address that sequentially changes until a start address output from the selection circuit is reached and reaches an end address that is paired with the start address, and controls the main memory. And acquiring the bus and executing data transfer between the storage area of the main memory corresponding to the destination address and the internal module. And a memory control circuit which,
Address switching means for controlling the selection circuit to select a next set of start address and end address from the plurality of sets when the destination address generated by the address counter matches the end address. And the following.

According to a second aspect of the present invention, in the data transfer control device according to the first aspect, the address switching means switches the set of the start address and the end address cyclically. is there.

According to a third aspect of the present invention, there is provided the data transfer control device according to the first or second aspect, wherein the counting circuit calculates a count value counted in synchronization with the change of the destination address in the address counter. A second selection circuit that selects a zero value until the count value output from the counting circuit reaches a predetermined value, and selects an offset value when the count value reaches the predetermined value; An addition / subtraction circuit that outputs to the address counter an addition / subtraction value obtained by adding / subtracting the offset value or the zero value output from the selection circuit and the destination address output from the address counter. When the count value reaches the predetermined value, the count value is reset, and the address counter sequentially changes the destination address starting from the addition / subtraction value. And it generates output a scan.

According to a fourth aspect of the present invention, there is provided the data transfer control device according to the third aspect, wherein the second counter circuit calculates a count value counted in synchronization with a change in the destination address in the address counter. Selecting a zero value until the count value output from the second count circuit reaches a predetermined value, and selecting a second offset value when the count value reaches the predetermined value. 4. A circuit for adding and subtracting the second offset value or the zero value output from the third selection circuit and the addition / subtraction value output from the addition / subtraction circuit according to claim 3, and outputting the result to the address counter. A second adding / subtracting circuit, wherein the second counting circuit resets the counted value when the counted value reaches the predetermined value, and the address counter determines whether or not the second adding / subtracting circuit is used. And it generates a destination address sequentially changes the outputted subtraction value as a starting point.

A fifth aspect of the present invention is a data transfer control device for controlling data transfer via a bus between a main memory for storing an image signal output from an image sensor and an internal module, An address counter that generates and outputs a destination address that sequentially changes starting from a predetermined address in the storage area of the main memory, a counting circuit that calculates a count value counted in synchronization with the change in the destination address in the address counter, A selection circuit that selects a zero value until the count value output from the counting circuit reaches a predetermined value, and selects an offset value when the count value reaches the predetermined value, and a selection circuit output from the selection circuit. An addition / subtraction value obtained by adding / subtracting the offset value or the zero value and the destination address output from the address counter is used as the address counter. A memory control circuit that controls the main memory, acquires the bus, and executes data transfer between a storage area of the main memory corresponding to the destination address and the internal module. The counter circuit resets the count value when the count value reaches the predetermined value, and the address counter generates a destination address that changes sequentially from the addition / subtraction value as a starting point.

According to a sixth aspect of the present invention, there is provided the data transfer control device according to the fifth aspect, wherein a count value counted until reaching a predetermined value in synchronization with a change in the destination address in the address counter is calculated. And a zero value until the count value output from the second count circuit reaches a predetermined value, and a second offset value is selected when the count value reaches the predetermined value. A third selection circuit that performs addition and subtraction between the second offset value or the zero value output from the third selection circuit and the addition / subtraction value output from the addition / subtraction circuit according to claim 5. A second addition / subtraction circuit for outputting to the address counter, the second counting circuit resets the count value when the count value reaches the predetermined value, and the address counter resets the count value. And it generates a destination address sequentially changes as a starting point outputted subtraction value from the subtraction circuit.

Next, a seventh aspect of the present invention is a data transfer method for transferring data via a bus between a main memory for storing an image signal output from an image sensor and an internal module. A) storing a plurality of sets of start addresses and end addresses of each of the plurality of storage areas in the main memory; and (b) a set of start addresses and ends from the plurality of sets stored in the step (a). Selecting an address; (c) generating a destination address starting from the start address selected in the step (b) and changing sequentially until reaching an end address that is paired with the start address; and (d). Controlling the main memory and acquiring the bus to execute data transfer between a storage area of the main memory corresponding to the destination address and the internal module; and (e) When the destination address generated in the step (c) matches the end address, in the step (b), a next set of start address and end address is selected from the plurality of sets, and the step (b) is performed. and c) and (d).

The invention according to claim 8 is the data transfer method according to claim 7, wherein in the step (e),
The next set is selected from the plurality of sets cyclically.

According to a ninth aspect of the present invention, there is provided the data transfer method according to the seventh or eighth aspect, wherein (f) a count value counted in synchronization with a change in the destination address generated in the step (c). And (g) selecting a zero value until the count value calculated in the step (f) reaches a predetermined value, and selecting an offset value when the count value reaches the predetermined value. And (h) adding and subtracting the zero value or the offset value selected in the step (g) and the destination address generated in the step (c). And calculating a destination address that changes sequentially from the addition / subtraction value calculated in the step (h) as a starting point in the step (c).

The invention according to claim 10 is the invention according to claim 9
The data transfer method according to claim 1, wherein (i) said step (c)
Calculating a second count value counted in synchronization with the change in the destination address generated in step (j); and (j) selecting a zero value until the second count value in step (i) reaches a predetermined value. Selecting a second offset value when the count value reaches the predetermined value and resetting the second count value in the step (i); and (k) selecting the second count value in the step (j). Calculating an addition / subtraction value obtained by adding the zero value or the second offset value calculated in step (h) to the addition / subtraction value calculated in step (h). In the step (c), the step (k) is performed. A destination address that sequentially changes starting from the addition / subtraction value calculated in step (1) is generated.

An eleventh aspect of the present invention is a data transfer method for transferring data via a bus between a main memory for storing an image signal output from an image sensor and an internal module. -1) a step of generating a destination address that sequentially changes starting from a predetermined address of the storage area of the main memory; and (f-1) synchronizing with a change of the destination address generated in the step (c-1). (G-1) selecting a zero value until the count value calculated in the step (f-1) reaches a predetermined value;
Selecting the offset value when the count value reaches the predetermined value and resetting the count value in the step (f-1); and (h-1) selecting the offset value in the step (g-1). Calculating a value obtained by adding or subtracting the zero value or the offset value and the destination address generated in the step (c-1); and (d-1) controlling the main memory and acquiring the bus to obtain the bus. Performing a data transfer between a storage area of the main memory corresponding to a destination address and the internal module; and in the step (c-1),
The present invention is characterized in that a destination address that changes sequentially from the addition / subtraction value calculated in the step (h-1) is generated.

The invention according to claim 12 is based on claim 1.
(I-1) a step of calculating a second count value counted in synchronization with a change in the destination address generated in the step (c-1); 1) selecting a zero value until the second count value of the step (i-1) reaches a predetermined value, selecting a second offset value when the count value reaches the predetermined value, and Step (i-1)
And (k-1) the zero value or the second offset value selected in the step (j-1) and the addition / subtraction value calculated in the step (h-1). Calculating an addition / subtraction value obtained by adding and subtracting
In the step (c-1), destination addresses that sequentially change starting from the addition / subtraction value calculated in the step (k-1) are generated.

[0018]

FIG. 1 is a schematic diagram showing the overall configuration of a digital still camera 1 used in an embodiment of the present invention. This digital still camera 1 has A
An optical mechanism 11 having an F (auto focus) function and an automatic exposure adjustment function is provided.
Is imaged. At this time, if necessary, a light whose amount is adjusted in synchronization with the photographing timing is supplied to a strobe (flash device) 3.
The light may be emitted from 0 to the subject. Original image data of the captured subject is taken into the analog signal processing circuit 13 and A / D converted into a digital image signal. The digital image signal is subjected to pixel interpolation processing, color space conversion processing, and RPU (Real Time Processing Unit) 14.
Real-time processing (real-time processing) of predetermined image processing such as gamma correction processing, contour correction processing, and filtering
It is applied in. The image signal that has undergone such image processing is displayed on the LCD 23 functioning as a finder, or transferred to the main bus 10 after being subjected to compression processing by the CPU 17 according to the JPEG method or the like, and is transferred to the memory card 27 Or output to an external device such as a personal computer through an external interface (I / F) 28.

In FIG. 1, reference numeral 15 denotes a CCD drive circuit that drives the CCD sensor 12, 16 denotes a timing generator that regulates the operation timing of the RPU 14 and the CCD drive circuit 15, etc., 18 denotes a PLL oscillation circuit,
Reference numeral 9 denotes an auxiliary processing unit (coprocessor) of the CPU 17, reference numeral 20 denotes a display module, reference numeral 21 denotes a digital encoder, and reference numeral 22 denotes an LCD for driving an LCD 23.
4 shows a drive circuit. Clock generator 29
Generates a drive clock signal for all modules such as the RPU 14, the timing generator 16, the CPU 17, and the digital encoder 21 by dividing the frequency of the clock signal supplied from the PLL oscillation circuit 18.

The main memory 26 is mutually connected to the analog signal processing circuit 13, RPU 14, DMA controller (data transfer control device) 24 and JPEG processing unit 25 via the main bus 10. Data transfer between the analog signal processing circuit 13 and the RPU 14 and the main memory 26 can be directly executed without the intervention of the CPU 17 under the control of the DMA controller 24.

Embodiment 1 FIG. 2 shows a DMA controller (data transfer control device) according to Embodiment 1 of the present invention.
FIG. 24 is a block diagram showing a configuration of the H.24. The DMA controller 24 includes DMA channels CH0 and CH1, an arbiter (arbitration circuit) 45, and a memory control circuit MC1.
The arbiter 45 and the memory control circuit MC1 are connected to the main bus 10. In FIG. 2, the internal modules ML0 and ML1
Or the display module 20. The number of internal modules is not limited to two, but may be three or more.

FIG. 3 shows a DMA channel CHn (n = 0,
FIG. 4 is a schematic diagram showing the circuit configuration of 1), and FIG.
FIG. 6 is a diagram for explaining a transfer process by a DMA controller 24 according to the first embodiment.

As shown in FIG. 3, the DMA channel CH
n is a register SREG1, SREG2, EREG1, EREG2 for storing the start addresses A, B and the end addresses A, B of the storage areas A, B of the main memory 26 shown in FIG.
From the CPU 17 to the registers SREG1,
The start addresses A and B are transferred to SREG2, respectively.
End addresses A and B are transferred and stored in registers EREG1 and EREG2, respectively. Selector SEL
1 is a register SREG1 controlled by the CPU 17.
And the selector SEL2 selects one of the start address A stored in the register ER2 and the start address B stored in the register SREG2.
End address A stored in EG1 and register EREG2
, And selects one of the end address B and outputs it to the comparator CMP1.

The address counter AC1 has a selector S
A destination address that is sequentially incremented (incremented) from the start address A or B loaded from EL1 is generated and output to both the comparator CMP1 and the arbiter 45. In the present invention, “incremental” means changing the amount in the positive or negative direction.

The comparator CMP1 compares the output signal from the selector SEL2 with the output signal from the address counter AC1, and if the two signals match, "H (High)".
A level signal is output. If both signals do not match, "L (Lo
w) Outputs a "level" signal. Also, in FIG.
44 is an AND element, 41 is a NOR element, 42 and 43 are O
The R element is shown.

An operation example of the DMA controller 24 having such a configuration will be described below in detail.

First, the internal module MLn (n = 0,
From 1), a DMA transfer request is issued to the arbiter 45.
The arbiter 45 transmits the internal module MLn (n = 0,
DMA channel CHn (n = 0,
An operation signal ACK is sent to 1). At this time, Arbiter 4
5 from a plurality of internal modules MLn (n = 0, 1) to D
When receiving the MA transfer request at the same time or when the CPU 17 accesses the main memory 26, the arbiter 45 determines the priority of each DMA transfer request and generates the operation signal ACK according to the priority. . This operation signal ACK is the AND signal of the DMA channel CHn shown in FIG.
Input to element 44. The AND element 44 performs a logical product operation of the operation signal ACK and the signal input from the OR element 42, and outputs an “H” level enable signal when both signals are at “H” level. If at least one of the signals is at the "L" level, the signal output is "L" level. Now, the AND element 44 outputs an “H” level enable signal to the address counter AC1.

As shown in FIG. 3, the CPU 17 controls the registers SREG1, SREG2 and EREG1, EREG2.
The start address A, B and the end address A, B are transferred to and stored in REG2, respectively.
By controlling EL2, the start address A stored in the register SREG1 and the end address A stored in the register EREG1 are selected. Next, the CPU 17 issues a control signal to the address counter AC1 to load the start address A from the selector SEL1. This control signal is supplied to the address counter AC1 via the OR element 43.
And the start address A is loaded.

When the address counter AC1 receives the enable signal from the AND element 44, the start address A
The destination addresses sequentially incremented starting from
And the comparator CMP1. The arbiter 45 outputs a control signal for permitting use of the main bus 10 to the memory control circuit MC1 and the destination address, and then the memory control circuit MC1 acquires the main bus 10 and transfers the destination address to the main memory 26. Then, the data is DMA-transferred from the internal module MLn (n = 0, 1) to the storage element corresponding to the destination address, and stored in the storage area A of the main memory 26 shown in FIG. Alternatively, the memory control circuit MC1 may cause the data stored in the storage element of the storage area A corresponding to the destination address to be DMA-transferred to the internal module MLn.

On the other hand, the comparator CMP1 is connected to the selector SEL1.
Address A and address counter AC1 selected in
And outputs a "H" level signal when both addresses match, and outputs an "L" level signal when both addresses do not match. Therefore,
Before the destination address incremented by the address counter AC1 reaches the end address A, the comparator CMP1 issues an "L" level signal. Therefore, regardless of whether the signal level stored in the register CREG1 is "L" or "H", the OR operation is performed. Element 43
Outputs an "L" level signal, and the OR element 42 outputs an "H" level signal. Therefore, the AND element 44 continues to output an “H” level enable signal obtained by performing an AND operation of the “H” level signal input from the OR element 42 and the “H” level operation signal ACK, and outputs the destination address in the address counter AC1. Increment is continued.

Next, the destination address is the end address A
Is reached, an "H" level signal is issued from the comparator CMP1. At this time, the subsequent processing branches depending on whether the signal value stored in the register CREG1 is “L” or “H”.

When the signal value stored in the register CREG1 is "L", when the comparator CMP1 issues an "H" level signal, the signal level input from the OR element 42 to the AND element 44 changes from "H" to "L". ". Therefore AN
The level of the output signal of the D element 44 becomes "L", the address counter AC1 stops the address increment operation by the "L" level signal, and the DM for the storage area A is stopped.
The A transfer process ends. The CPU 17 is provided with a selector SE.
L1 and SEL2 to control the selectors SEL1 and SEL2.
The CPU 17 issues a control signal to the address counter AC1 to load the start address B of the next storage area B from the selector SEL1 to the address counter AC1. This control signal is input to the address counter AC1 via the OR element 43 to load the start address B. As a result, the comparator CMP1 outputs an "L" level signal, the AND element 44 outputs an "H" level enable signal, and the address counter AC1 outputs the start address until the start address B matches the end address B. Generate destination addresses sequentially incremented starting from B,
The destination address is output to the comparator CMP1 and the arbiter 45. Next, as described above, the DMA transfer is performed on the destination address in the storage area B. When the destination address matches the end address B, the comparator CMP1 outputs an "H" level signal, so that the AND element 44 outputs an "L" level signal, and the address counter AC1 stops the address increment operation. I do. Thus, the DMA transfer processing for the storage area B is completed.

On the other hand, when the signal value stored in the register CREG1 is "H", the destination address is the end address A
, An "H" level signal is output from the comparator CMP1. In synchronization with this "H" level signal, the CPU 17 controls the selectors SEL1 and SEL2 to
1 and SEL2 are controlled to select a start address B and an end address B, respectively. OR element 43
Outputs an "H" level signal, which is input to the address counter AC1 via the OR element 43. Upon receiving the "H" level signal, the address counter AC1 loads the start address B from the selector SEL1, generates a destination address sequentially incremented from the start address B, and sends it to the comparator CMP1 and the arbiter 45. Output. At this time, the AND element 44 outputs A
An "H" level enable signal obtained by performing a logical AND operation of the "H" level signal input to the ND element 44 and the "H" level operation signal ACK is continuously output. In this manner, the DMA transfer is executed to the destination address in the storage area B in the same manner as the DMA transfer processing to the storage area A described above.

Subsequently, when the destination address and the end address B match, the comparator CMP1 outputs an "H" level signal, and the CPU 1 synchronizes with the "H" level signal.
7 controls the selectors SEL1 and SEL2,
Control is performed on EL1 and SEL2 to select a start address A and an end address A, respectively. Further, the address counter AC1 receiving the “H” level signal output from the OR element 43 loads the start address A of the next storage area A from the selector SEL1, and executes the DMA transfer to the storage area A as described above. Is done. When the storage area A and the storage area B are used cyclically (cyclically) in the DMA transfer, the address counter AC1 is used when the incremented destination address matches the end address.
Receives an "H" level control signal, and the control signal automatically loads the next start address.
The PU 17 does not need to specify the start address and the end address one by one, and the load on the CPU 17 can be reduced.

As described above, the DMA according to the first embodiment
Since the controller 24 has two sets of the start address and the end address, the controller 24 can execute the DMA transfer at a high speed, and switches the storage area A and the storage area B between the storage area A and the storage area B when the DMA transfer to the main memory 26 is executed. Can be run without any load. Therefore, the load on the CPU 17 is reduced even if the small-volume data is frequently DMA-transferred. In this embodiment, the number of pairs of the start address and the end address is two, but the present invention is not limited to this, and may be three or more.

Since the start addresses A and B and the end addresses A and B are selectively switched using the selectors SEL1 and SEL2, the overall image processing speed can be improved by using the CPU 17 efficiently. It becomes possible. For example, while data is being DMA-transferred to the storage area B, the data stored in the storage area A can be read and software-processed.

Embodiment 2 Next, FIG. 5 is a diagram showing a circuit configuration of a DMA channel CHn of a DMA controller (data transfer control device) 24 according to Embodiment 2 of the present invention, and FIGS. 6 and 7 show transfer processing by the DMA controller. FIG. In FIG. 5, symbols and blocks denoted by the same reference numerals as those shown in FIG. 3 have substantially the same functions, and detailed descriptions thereof will be omitted.

DMA channel CHn of the second embodiment
Is a local counter LC1 that performs a counting process in synchronization with the address increment operation of the address counter AC1 in addition to the configuration of the DMA channel of the first embodiment.
It has. Further, the comparator CMP2 calculates the value of the output signal of the local counter LC1 and the value of the register LEREG1.
Is compared with the final value A stored in the memory. If the two signals match, an "H" level comparison signal is output. If the two signals do not match, an "L" level comparison signal is output. The selector SEL2 selects and outputs the value "0" when the level of the comparison signal is "L", and selects the offset value stored in the register OREG1 when the level of the comparison signal is "H". And output it. The adder AD1 includes a selector SE
The output signal of L2 and the destination address incremented by the address counter AC1 are added. In this embodiment, the adder AD1 is used on the assumption that the destination address is incremented in the positive direction. However, when the destination address is incremented in the negative direction, the adder AD1 performs the subtraction. It is replaced with a vessel.

The operation of the DMA controller 24 having such a DMA channel CHn will be described in detail below.

As in the first embodiment, when a DMA transfer request is issued from the internal module MLn to the arbiter 45, the arbiter 45 sends an operation signal ACK to the DMA channel CHn assigned to the internal module MLn. This operation signal ACK is input to the AND element 44 of the DMA channel CHn shown in FIG. The AND element 44 performs a logical product operation of the operation signal ACK and the output signal of the OR element 42, and when both signals are at the “H” level, outputs the “H” level enable signal to the address counter AC1 and the address counter AC1. Output to the counter LC1 to execute the increment operation and the count operation. Note that both the address counter AC1 and the local counter LC1 are supplied with a clock signal (not shown) that causes the destination address to be incremented and counted at the same timing.

As in the case of the first embodiment, C
PU17 includes registers SREG1, SREG2 and ER
The start addresses A and B and the end addresses A and B are transferred and stored in EG1 and EREG2, respectively. Also, C
The PU 17 issues a control signal to the address counter AC1 to load the start address A selected by the selector SEL1, and the address counter AC1 receiving the control signal loads the start address A, and starts from the start address A. A sequentially incremented destination address is generated and output to the comparator CMP1 and the arbiter 45. Further, the local counter LC1 generates a count value counted from a predetermined initial value A (usually a zero value) in synchronization with the increment operation of the address counter AC1.

The arbiter 45 receiving the destination address
Outputs a control signal for permitting use of the main bus 10 to the memory control circuit MC1 and the destination address. The memory control circuit MC1 is connected to the main bus 1
0, and outputs the destination address to the main memory 26. The data stored in the storage element corresponding to the destination address is DMA-transferred to the internal module MLn, or the data is transferred from the internal module MLn to the storage element. Is DMA-transferred.

When the count value of the local counter LC1 coincides with the final value A stored in the register LEREG1, the comparator CMP2 outputs an "H" level signal, and the selector SEL2 which has received the signal outputs the register OR.
The offset value A stored in EG1 is selected and the adder AD is selected.
Output to 1. At this time, the value of the local counter LC1 is reset to the initial value A. The adder AD1 generates an addition value obtained by adding the offset value A to the destination address, and outputs the addition value to the address counter AC1. The address counter AC1 receives the "H" level signal from the comparator CMP2, loads the added value, and generates and outputs a destination address sequentially incremented from the added value as a starting point.

Next, the DM for the storage area A is
After the A transfer is completed, the DMA transfer to the storage area B is continued in the same procedure.

As described above, by adjusting the final value A and the offset value A, the image data stored in the main memory 26 or the like can be thinned out and DMA-transferred without imposing a load on the CPU 17. . For example, FIG.
When the storage area from the start address to the end address of the main memory 26 is to be transferred as shown in (2), the area OR1 corresponding to the offset value A is skipped and the value of the local counter LC1 changes from the initial value A to the final value A. Can be selected and transferred.
Accordingly, as shown in FIG. 7A, the image data P stored in the main memory 26 in the progressive (sequential scanning) format is used.
From 2, it is possible to extract (cut out) image data consisting of a horizontal line region from the start address to the end address and a vertical line region obtained by thinning out a region corresponding to the offset value A.

As shown in the image data P3 of FIG. 7B, by increasing the offset value A by one horizontal line from the value of FIG. 7A, the image data of the interlaced (interlaced scanning) format is obtained. DMA transfer can also be performed.
Therefore, the progressive image signal processed by the RPU 14 and the CPU 17 is temporarily stored in the main memory 26, and the interlaced image data is DMA-transferred to the display module 20 by the above-described operation procedure and displayed on the LCD 23. It becomes possible.

Embodiment 3 Next, FIG. 8 is a schematic diagram showing a circuit configuration of a DMA controller (data transfer control device) 24 according to Embodiment 3 of the present invention, and FIGS.
FIG. 3 is a diagram illustrating a transfer process by the DMA controller. In FIG. 8, symbols and blocks denoted by the same reference numerals as those shown in FIGS. 3 and 4 have substantially the same functions and will not be described in detail.

The DMA channel CHn of the third embodiment
Is a local counter LC2 that executes a counting process in synchronization with the address increment operation of the address counter AC1 in addition to the configuration of the DMA channel of the second embodiment.
It has. Further, the comparator CMP3 determines the value of the output signal of the local counter LC2 and the value of the register LEREG2.
Is compared to the final value B, and outputs an "H" level comparison signal to the selector SEL3 and the OR element 50 when both signals match, and "L" level when both signals do not match. The selector SEL3 is controlled by a comparison signal output from the comparator CMP3, selects a value of "0" when the level of the comparison signal is "L", and selects a value of "0" when the level of the comparison signal is "H". Selects the offset value B stored in the register OREG2 and outputs it to the adder AD2. In the present embodiment, the adder AD2 is used on the assumption that the destination address is incremented in the positive direction. However, when the destination address is incremented in the negative direction, the adder AD2 performs subtraction. It is replaced with a vessel.

The OR element 50 performs a logical OR operation on the comparison signal from the comparator CMP3 and the comparison signal from the comparator CMP2 and outputs the result to the address counter AC1.

The operation of the DMA controller 24 having such a DMA channel CHn will be described in detail below.

As in the first and second embodiments, when a DMA transfer request is issued from the internal module MLn to the arbiter 45, the arbiter 45 sets the internal module MLn.
ACK signal to DMA channel CHn assigned to
Is sent. This operation signal ACK is input to the AND element 44 of the DMA channel CHn shown in FIG. Also AN
The D element 44 performs a logical AND operation of the operation signal ACK and the output signal of the OR element 42, and when both signals are at the “H” level, outputs the “H” level enable signal to the address counter AC1 and the local counter. Output to LC1 and LC2 to execute the increment operation and the counting operation. The address counter AC1 and the local counters LC1 and LC2 are supplied with a clock signal (not shown) that causes the destination address to be incremented and counted at the same timing.

Similarly to the first and second embodiments, the CPU 17 stores start addresses A, EREG2 in registers SREG1, SREG2 and EREG1, EREG2, respectively.
B and end addresses A and B are transferred and stored. Further, the CPU 17 issues a control signal to the address counter AC1 to load the start address A selected by the selector SEL1, and the address counter AC1 receiving the control signal loads the start address A and starts from the start address A. Is generated and output to the comparator CMP1 and the arbiter 45. The local counters LC1 and LC2 generate and output count values counted from predetermined initial values A and B, respectively, in synchronization with the increment operation of the address counter AC1.

Similarly to the first and second embodiments, the arbiter 45 receiving the destination address controls the memory control circuit MC1 to store the data stored in the storage element corresponding to the destination address. DMA transfer is performed to the module MLn, or data is transferred from the internal module MLn to the storage element by DMA transfer and stored.

When the count value of the local counter LC1 coincides with the final value A stored in the register LEREG1, the comparator CMP2 outputs an "H" level signal, and the selector SEL2 which has received the signal outputs the register OR.
The offset value A stored in EG1 is selected and the adder AD is selected.
Output to 1. The local counter LC1 has a comparator C
When the MP2 outputs the “H” level signal, the count value is reset to the initial value A. Further, the adder AD1 outputs an added value obtained by adding the address output from the address counter AC1 and the offset value A to the adder AD2. The adder AD2 adds the added value and the value output from the selector SEL3 and outputs the result to the address counter AC1. The address counter AC1 outputs the "H" level signal generated by the comparator CMP2 via the OR element 50. Receiving
The added value output from the adder AD2 is loaded, and a destination address sequentially increased from the added value is generated and output.

On the other hand, when the count value of the local counter LC2 coincides with the final value B stored in the register LEREG2, the comparator CMP3 outputs an "H" level signal, and the selector SEL3 having received the signal outputs the register O
Select the offset value B stored in REG2 and adder A
Output to D2. The local counter LC2 resets the count value to the initial value B when the comparator CMP3 outputs the “H” level signal. The adder AD2 adds the value output from the adder AD1 and the offset value B and outputs the result to the address counter AC1. The address counter AC1 outputs "H" output from the comparator CMP3 via the OR element 50. Upon receiving the level signal, the added value output from the adder AD2 is loaded, and the destination address sequentially incremented from the added value is generated and output.

Next, the DM for the storage area A is
After the A transfer is completed, the DMA transfer to the storage area B is continued in the same procedure.

As described above, in the third embodiment, by adjusting the final value B and the offset value B, the CPU
The image data can be DMA-transferred by further thinning out the image data without imposing a load on the image data. For example, as shown in FIG. 9, when the storage area from the start address to the end address of the main memory 26 is transferred, the area OR2 corresponding to the offset value B is skipped, and the value of the local counter LC2 is changed from the initial value B to the final value. .. Corresponding to the period up to B, and further, in each transfer region TR2, a region O corresponding to the offset value A is selected.
A transfer area TR corresponding to a period in which the value of the local counter LC1 jumps from R1 to the final value B from the initial value B.
1, TR1,... Can be selected for DMA transfer. This makes it possible to select a plurality of image areas from the image data, reduce them to an arbitrary size, and display them.

Specifically, as shown in FIG.
From the image data P4 stored in the main memory 26 in the progressive format, the area OR corresponding to the offset value B is obtained.
2 can be extracted (cut out) from the horizontal line areas TR1,... Corresponding to the offset value A in the vertical line area TR2 in which 2 is thinned out.

As shown in FIG. 10 (b), by increasing the offset value B by one or more horizontal lines from the value in FIG. 10 (a), a predetermined number of vertical lines and horizontal lines are thinned out. Image data can also be extracted.

[0060]

As described above, according to the data transfer control device according to the first aspect of the present invention and the data transfer method according to the seventh aspect, a plurality of sets of the start address and the end address are prepared. Since these sets can be sequentially selected by the switching means, data can be sequentially transferred to a plurality of storage areas on the main memory without imposing a load on the CPU. For this reason, the load on the CPU can be suppressed to a small value even if data having a small capacity is frequently transferred. Also C
As the load on the PU is reduced, the CPU can be used efficiently by executing image processing on software, and the processing speed of image data can be improved.

According to the second and eighth aspects, since a plurality of storage areas on the main memory can be cyclically used, the main memory can be used efficiently. The CPU does not need to generate a control signal for cyclically switching the set of the start address and the end address.
The load on U can be reduced, and the CPU can be used efficiently.

According to the third and fifth aspects and the ninth and eleventh aspects, by adjusting the predetermined value and the offset value, the image data stored in the main memory or the like can be thinned out without imposing a load on the CPU. Data transfer becomes possible.

Claims 4 and 6 and claims 10 and 1
According to 2, it is possible to thinly thin out image data and transfer data without imposing a load on the CPU.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a digital still camera used in an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a DMA controller according to Embodiment 1 of the present invention.

FIG. 3 is a diagram illustrating a DM of the DMA controller according to the first embodiment;
FIG. 3 is a diagram illustrating a circuit configuration of an A channel.

FIG. 4 is a diagram illustrating a transfer process of a DMA controller according to the first embodiment.

FIG. 5 is a diagram showing a circuit configuration of a DMA channel of a DMA controller according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a transfer process by a DMA controller according to the second embodiment.

FIG. 7 is a diagram illustrating a transfer process by a DMA controller according to the second embodiment.

FIG. 8 is a diagram showing a circuit configuration of a DMA channel of a DMA controller according to Embodiment 3 of the present invention.

FIG. 9 is a diagram illustrating a transfer process by a DMA controller according to the third embodiment.

FIG. 10 is a diagram illustrating a transfer process by a DMA controller according to a third embodiment.

FIG. 11 is a schematic configuration diagram of a general digital still camera.

[Explanation of symbols]

 ML0, ML1 Internal module SREG1, SREG2 register EREG1, EREG2 register OREG1, OREG2, CREG1 register LEREG1, LEREG2 register AD1, AD2 Adder SEL1-SEL4 Selector AC1 Address counter MC1 Memory control circuit CMP1-CMP3 Comparator LC1, LC2 Local counter CH DMA channel

Claims (12)

[Claims] 1. A data transfer control device for controlling data transfer via a bus between a main memory for storing an image signal output from an image sensor and an internal module, wherein each of a plurality of storage areas in the main memory is provided. A register for storing a plurality of pairs of a start address and an end address, a selection circuit for selecting one set of a start address and an end address from the plurality of sets, and a start address output from the selection circuit as a starting point,
An address counter that generates and outputs a destination address that sequentially changes until reaching an end address that is paired with the start address; and a storage area of the main memory that controls the main memory and acquires the bus to correspond to the destination address. And a memory control circuit for executing data transfer between the internal modules, and when a destination address generated by the address counter matches the end address, a next set of start addresses from the plurality of sets Address transfer means for controlling the selection circuit so as to select an end address. 2. The data transfer control device according to claim 1, wherein the address switching means switches the set of the start address and the end address cyclically. 3. The data transfer control device according to claim 1, wherein: a counting circuit that calculates a count value counted in synchronization with a change in the destination address in the address counter; A second selection circuit that selects a zero value until the counted value reaches a predetermined value, and selects an offset value when the counted value reaches the predetermined value; An addition / subtraction circuit that outputs an addition / subtraction value obtained by adding / subtracting the offset value or the zero value and a destination address output from the address counter to the address counter, wherein the counting circuit sets the count value to the predetermined value. When the count value is reached, the count value is reset, and the address counter generates and outputs a sequentially changing destination address starting from the addition / subtraction value. Data transfer control device. 4. The data transfer control device according to claim 3, wherein: a second counting circuit that calculates a count value counted in synchronization with a change in a destination address in the address counter; and the second counting circuit. A third selection circuit that selects a zero value until the count value output from the counter reaches a predetermined value, and selects a second offset value when the count value reaches the predetermined value; A second addition / subtraction circuit for adding / subtracting the second offset value or the zero value output from the selection circuit and the addition / subtraction value output from the addition / subtraction circuit according to claim 3 and outputting the result to the address counter; The second counting circuit resets the count value when the count value reaches the predetermined value, and the address counter generates the addition / subtraction value output from the second addition / subtraction circuit. Sequentially generates a destination address changes as the data transfer control device. 5. A data transfer control device for controlling data transfer via a bus between a main memory for storing an image signal output from an image sensor and an internal module, the data transfer control device comprising: An address counter that generates and outputs a destination address that changes sequentially from the address of the address counter, a counting circuit that calculates a count value that is counted in synchronization with the change of the destination address in the address counter, and a counter that is output from the counting circuit. A selection circuit that selects a zero value until the numerical value reaches a predetermined value, and selects an offset value when the count value reaches the predetermined value, and the offset value or the zero value output from the selection circuit. An addition / subtraction circuit for outputting an addition / subtraction value obtained by adding / subtracting the destination address output from the address counter to the address counter. A memory control circuit that controls the main memory and acquires the bus to execute data transfer between a storage area of the main memory corresponding to the destination address and the internal module; A data transfer control device, wherein the circuit resets the count value when the count value reaches the predetermined value, and the address counter generates a sequentially changing destination address starting from the addition / subtraction value. 6. The data transfer control device according to claim 5, wherein a second counting circuit that calculates a count value counted until reaching a predetermined value in synchronization with a change in the destination address in the address counter; A third selection circuit that selects a zero value until the count value output from the second count circuit reaches a predetermined value, and selects a second offset value when the count value reaches the predetermined value; A second adding / subtracting unit for adding / subtracting the second offset value or the zero value output from the third selection circuit and the addition / subtraction value output from the addition / subtraction circuit according to claim 5, and outputting the result to the address counter. And the second counter circuit resets the count value when the count value reaches the predetermined value, and the address counter outputs from the second adder / subtractor circuit. The generating a destination address which sequentially changes the subtraction value as a starting point, the data transfer control device. 7. A data transfer method for transferring data via a bus between a main memory for storing an image signal output from an image sensor and an internal module, comprising: (a) a plurality of storages in the main memory; (B) selecting one set of start address and end address from the plurality of sets stored in step (a), and c) generating, starting from the start address selected in the step (b), a destination address that sequentially changes until reaching an end address paired with the start address; (d) controlling the main memory and Acquiring a bus and executing data transfer between the storage area of the main memory corresponding to the destination address and the internal module; and (e) the destination generated in the step (c). When the destination address matches the end address, the next set of start address and end address is selected from the plurality of sets in the step (b), and the steps (c) and (d) are executed. A data transfer method. 8. The data transfer method according to claim 7, wherein, in the step (e), the next set is cyclically selected from the plurality of sets. Method. 9. The data transfer method according to claim 7, wherein (f) calculating a count value in synchronization with a change in the destination address generated in the step (c); g) selecting a zero value until the count value calculated in the step (f) reaches a predetermined value, selecting an offset value when the count value reaches the predetermined value, and selecting the offset value in the step (f). Resetting a count value; and (h) calculating an addition / subtraction value obtained by adding / subtracting the zero value or the offset value selected in the step (g) and the destination address generated in the step (c). A data transfer method, further comprising: in the step (c), generating a destination address that sequentially changes starting from the addition / subtraction value calculated in the step (h). 10. The data transfer method according to claim 9, wherein (i) calculating a second count value counted in synchronization with a change in the destination address generated in the step (c); (J) selecting a zero value until the second count value of the step (i) reaches a predetermined value; selecting a second offset value when the count value reaches the predetermined value; (I) resetting the second count value, and (k) adding the zero value or the second offset value selected in the step (j) and the addition / subtraction value calculated in the step (h). Calculating the calculated addition / subtraction value, wherein in the step (c), a destination address that sequentially changes starting from the addition / subtraction value calculated in the step (k) is generated. 11. A data transfer method for transferring data via a bus between a main memory for storing an image signal output from an image sensor and an internal module, comprising:
1) generating a destination address that sequentially changes starting from a predetermined address in a storage area of the main memory;
-1) calculating a count value counted in synchronization with the change in the destination address generated in the step (c-1);
-1) A zero value is selected until the count value calculated in the step (f-1) reaches a predetermined value, and an offset value is selected when the count value reaches the predetermined value. f
-1) resetting the count value, and (h-1) adding or subtracting the zero value or the offset value selected in the step (g-1) and the destination address generated in the step (c-1). (D-1) controlling the main memory and acquiring the bus to transfer data between the storage area of the main memory corresponding to the destination address and the internal module. Performing the step (c-1), wherein in the step (c-1), a destination address that sequentially changes starting from the addition / subtraction value calculated in the step (h-1) is generated. 12. The data transfer method according to claim 11, wherein (i-1) calculating a second count value in synchronization with a change in the destination address generated in the step (c-1). And (j-1) selecting a zero value until the second count value of the step (i-1) reaches a predetermined value, and selecting a second value when the count value reaches the predetermined value. Selecting an offset value and resetting the second count value in step (i-1); and (k-1) the zero value or the second offset value selected in step (j-1). And the step (h-
A step of calculating an addition / subtraction value obtained by adding / subtracting the addition / subtraction value calculated in 1), wherein the step (c-1) sequentially changes the addition / subtraction value calculated in the step (k-1) from a starting point. A data transfer method that generates a destination address to perform.