JPH0427686B2 - - Google Patents

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Publication number
JPH0427686B2
JPH0427686B2 JP58059674A JP5967483A JPH0427686B2 JP H0427686 B2 JPH0427686 B2 JP H0427686B2 JP 58059674 A JP58059674 A JP 58059674A JP 5967483 A JP5967483 A JP 5967483A JP H0427686 B2 JPH0427686 B2 JP H0427686B2
Authority
JP
Japan
Prior art keywords
resist
pattern
radiation
synchrotron radiation
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58059674A
Other languages
Japanese (ja)
Other versions
JPS59184525A (en
Inventor
Shingo Ichimura
Masahiro Hirata
Masatoshi Ono
Koichiro Ootori
Hiroshi Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58059674A priority Critical patent/JPS59184525A/en
Publication of JPS59184525A publication Critical patent/JPS59184525A/en
Publication of JPH0427686B2 publication Critical patent/JPH0427686B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 この発明は、微細構造を有するLSI素子などの
製造過程において用いられているマスクパターン
の大量転写に好適なパターンの形成方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern forming method suitable for mass transfer of mask patterns used in the manufacturing process of LSI elements having fine structures.

従来のマスクパターンの転写方法を、半導体素
子の作成工程を例にとつて第1図a〜fに基づい
て順を追つて説明する。
A conventional method for transferring a mask pattern will be explained step by step based on FIGS.

(1) 素子作製に用いるシリコン等の半導体結晶基
板1上に酸化シリコン等の絶縁体層2を成長さ
せる。
(1) An insulator layer 2 made of silicon oxide or the like is grown on a semiconductor crystal substrate 1 made of silicon or the like used for device fabrication.

(2) 絶縁体層2上に、電子線あるいはX線など露
光に用いられる露光用ビーム5に感光するレジ
スト3を塗布する(第1図a参照)。
(2) A resist 3 that is sensitive to an exposure beam 5 used for exposure, such as an electron beam or an X-ray, is applied onto the insulator layer 2 (see FIG. 1a).

(3) レジスト3上に転写用パターンを描画したマ
スク4を置く。
(3) Place a mask 4 with a transfer pattern drawn on the resist 3.

(4) マスク4側から、電子線、イオン線、紫外線
(X線)などの露光用ビーム5を照射する。こ
の際、電子線、イオン線、X線などの様に露光
用ビーム5と大気との相互作用が大きい場合に
は、高い真空状態に排気した真空装置6内で露
光を行う(第1図a参照)。
(4) An exposure beam 5 such as an electron beam, ion beam, or ultraviolet ray (X-ray) is irradiated from the mask 4 side. At this time, if the interaction between the exposure beam 5 and the atmosphere is large, such as with an electron beam, ion beam, or X-ray, exposure is performed in a vacuum device 6 evacuated to a high vacuum state (see Figure 1a). reference).

(5) 露光した上記半導体結晶基板1を大気中にと
り出し、マスク4を外した後、化学的現像液7
を作用させる。この時、用いたレジスト3がポ
ジ型であれば露光用ビーム5との反応部分が、
また、レジスト3がネガ型であれば露光用ビー
ム5との未反応部分が、それぞれ除去されて、
所望のパターンが転写される(第1図c参照)。
(5) After taking out the exposed semiconductor crystal substrate 1 into the atmosphere and removing the mask 4, a chemical developer 7 is applied.
to act. At this time, if the resist 3 used is a positive type, the part that reacts with the exposure beam 5 will be
Furthermore, if the resist 3 is of negative type, the unreacted portions with the exposure beam 5 are removed.
The desired pattern is transferred (see Figure 1c).

(6) 半導体結晶基板1を再度真空装置6内に入
れ、イオン線などのエツチング用ビーム8を照
射して、前記工程5によりレジスト3が除去さ
れた部分の絶縁体層2をとり除く(第1図d参
照)。
(6) Place the semiconductor crystal substrate 1 into the vacuum device 6 again and irradiate it with an etching beam 8 such as an ion beam to remove the insulating layer 2 in the portion where the resist 3 was removed in step 5 (first (see figure d).

(7) 前記工程6により絶縁体層2が除去され、下
地の半導体結晶基板1が曝された箇所に、イオ
ンインプランテーシヨン。拡散などの方法によ
り他元素を注入し、半導体素子の活性化処理9
を行う(第1図e参照)。
(7) Ion implantation is performed at the location where the insulator layer 2 has been removed in step 6 and the underlying semiconductor crystal substrate 1 has been exposed. Activation treatment of semiconductor elements by implanting other elements by methods such as diffusion 9
(See Figure 1e).

(8) 残つているレジスト3をはく離液、あるいは
プラズマイオン照射等により除去する(第1図
f参照)。
(8) The remaining resist 3 is removed using a stripping solution or plasma ion irradiation (see Figure 1 f).

上記(1)〜(8)の工程において、従来は、高い真空
度を要する電子線、イオン線、X線等の露光用ビ
ーム5による露光(第1図b参照)やエツチング
用ビーム8によるイオンビームエツチング(第1
図d参照)およびイオンインプランテーシヨンな
どの活性化処理9(第1図e参照)の工程と、大
気中での化学的現像処理(第1図c,f参照)の
工程とが共存しているため、真空排気の観点から
多大な煩雑さを伴つていた。また、レジスト3へ
のパターンの転写特性の面では、転写像の分解能
が、単にレジスト3と露光用ビーム5の反応特性
だけではなく、露光反応後のレジスト3と化学的
現像液7との相互作用特性に大きく影響されるた
め、現像だれ等の問題を生じると同時に、レジス
ト3の評価、選択において複雑さ、曖昧さ、ま
た、種々の制限条件をもたらしていた。
In the steps (1) to (8) above, conventionally, exposure using an exposure beam 5 such as an electron beam, ion beam, or Beam etching (1st
d) and ion implantation (see Fig. 1 e), and chemical development in the atmosphere (see Fig. 1 c, f) coexist. Therefore, it was accompanied by great complexity from the viewpoint of vacuum evacuation. In addition, in terms of the transfer characteristics of the pattern to the resist 3, the resolution of the transferred image is determined not only by the reaction characteristics of the resist 3 and the exposure beam 5, but also by the interaction between the resist 3 and the chemical developer 7 after the exposure reaction. Since it is greatly influenced by the action characteristics, problems such as development sag occur, and at the same time, it causes complexity, ambiguity, and various limiting conditions in the evaluation and selection of the resist 3.

この発明は、上述の点にかんがみてなされたも
ので、強い強度を有するシンクロトロン放射光を
レジストに照射し、レジストを直接解離、脱離さ
せて、上記のような問題点を生み出す根本原因で
ある化学現像工程を省略し、さらに現在半導体製
造工程で要求の高まつているプロセスのドライ
化、真空内での一貫処理化を促進するパターン形
成方法を提供することを目的とする。以下、この
発明の一実施例を図面を用いて説明する。
This invention was made in view of the above-mentioned points, and it is possible to eliminate the root cause of the above-mentioned problems by irradiating the resist with high-intensity synchrotron radiation light to directly dissociate and desorb the resist. It is an object of the present invention to provide a pattern forming method that eliminates a certain chemical development step and further promotes dry processing and integrated processing in vacuum, which are currently increasingly required in semiconductor manufacturing processes. An embodiment of the present invention will be described below with reference to the drawings.

シンクロトロン放射光は、紫外線、X線などの
従来の露光用ビームに比較し、輝度(単位時間、
単位立体角当りの放出エネルギー量)が数桁以上
高く、かつX線領域から紫外線領域までの幅広い
波長分布を有している。このような従来のビーム
と異なる長所を有するシンクロトロン放射光を高
分子レジストに照射すると、単にレジスト分子鎖
の切断、架橋反応だけでなく、放射光により直接
レジスト高分子の解離、脱離反応が起る。
Synchrotron synchrotron radiation has lower brightness (unit time,
The amount of emitted energy per unit solid angle) is several orders of magnitude higher, and it has a wide wavelength distribution from the X-ray region to the ultraviolet region. When a polymer resist is irradiated with synchrotron radiation, which has advantages different from conventional beams, it not only causes the scission and crosslinking reactions of resist molecular chains, but also the direct dissociation and elimination reactions of resist polymers. It happens.

第2図はシンクロトロン放射光の照射により直
接レジスト高分子の解離、脱離反応が起る一例を
示す図である。同図において、縦軸は放射光を照
射した際、レジストから放出される二次電子の強
度Hを示し、横軸はレジストに付与された放射光
エネルギー総量E(アンペア・秒:便宜上、電子
蓄積リングの蓄積電流×照射時間を単位として示
した値)を示したものである。同図から明らかな
ように、放射光の単位時間あたりのエネルギー付
与量が大きい(同図X点から右側参照)場合に
は、レジストからの二次電子強度は線型に増加す
る。このレジストからの二次電子強度変化はレジ
ストの膜厚変化、すなわち放射光によるレジスト
高分子の直接解離・脱離現像と対応していること
が、タリステツプを用いたレジスト膜厚測定結果
から明らかになつている。たとえばレジストとし
て、EBR−9(東レ、ポリトリフルオロエチルα
−クロルアクリレート)を用いた場合の膜厚変化
は、110A・secの総照射量(便宜上、電子蓄積リ
ングの蓄積電流×照射時間を単位として示した
値)の時〜0.9μmであつた。
FIG. 2 is a diagram showing an example in which a dissociation and desorption reaction of a resist polymer occurs directly by irradiation with synchrotron radiation light. In the figure, the vertical axis shows the intensity H of secondary electrons emitted from the resist when it is irradiated with synchrotron radiation, and the horizontal axis shows the total amount of synchrotron energy E (ampere-seconds: for convenience, the electron accumulation (The value expressed in units of accumulated current of the ring x irradiation time). As is clear from the figure, when the amount of energy imparted by the synchrotron radiation per unit time is large (see the right side from point X in the figure), the intensity of secondary electrons from the resist increases linearly. It is clear from the results of resist film thickness measurement using Talystep that this change in the intensity of secondary electrons from the resist corresponds to a change in the resist film thickness, that is, the direct dissociation and desorption development of the resist polymer by synchrotron radiation. It's summery. For example, as a resist, EBR-9 (Toray, polytrifluoroethyl α
-Chloracrylate), the film thickness change was ~0.9 μm at a total irradiation dose of 110 A·sec (for convenience, the value is expressed as the unit of storage current of the electron storage ring x irradiation time).

上記実施例においては、放射光を発生する電子
蓄積リングの電子電流をできる限り高く保ち、高
い輝度を有する放射光を利用した光エツチング過
程により、マスクパターンをレジスト上に直接転
写して所望のレジスト形状を得ることが可能とな
る。
In the above embodiment, the electron current of the electron storage ring that generates synchrotron radiation is kept as high as possible, and a mask pattern is directly transferred onto the resist by a photoetching process using synchrotron radiation with high brightness to form the desired resist. It becomes possible to obtain the shape.

レジストによつては、光エツチングと同時に進
行する分子鎖架橋のために第3図aに示すよう
に、わずかな膜厚が残存することがある。同図に
おいて、1.2μm膜厚のEBR−9のレジスト3につ
いて放射光照射部に0.3μm膜厚の分子鎖架橋層
(クロスリンク層)10が残る場合がある。この
場合は第3図bに示すように次の工程で、そのま
まイオンエツチングを施せば、クロスリンク層1
0は完全に除去され、しかも未照射部にはなお
0.9μm膜厚のレジスト3が残つている構造がえら
れる。従つて継続して開口部の基板をイオンエツ
チングする工程が何ら支障なく行うことができ、
クロスリンク層10によるわずかな膜残りは実用
上問題にならない。
Depending on the resist, a slight film thickness may remain as shown in FIG. 3a due to molecular chain crosslinking that occurs simultaneously with photoetching. In the figure, for the resist 3 of EBR-9 with a thickness of 1.2 μm, a molecular chain cross-linked layer (crosslink layer) 10 with a thickness of 0.3 μm may remain in the radiation irradiated area. In this case, as shown in Figure 3b, if ion etching is performed as is in the next step, the crosslink layer 1
0 is completely removed, and still remains in the unirradiated area.
A structure in which the resist 3 with a film thickness of 0.9 μm remains is obtained. Therefore, the process of ion etching the substrate in the opening can be carried out without any problem.
A slight amount of film remaining due to the cross-link layer 10 does not pose a practical problem.

上記実施例によれば、上述の様にすべて真空内
での一貫したプロセスとしてパターン転写を行う
ことができるため、くり返し真空排気をする煩雑
さから解放されて生産効率の向上を期待できる。
特に今後必要性が増すであろう三次元的構造を有
する半導体素子製造では、従来の方法に従えば真
空排気操作に伴う煩雑さもますます増加すること
になるのに対し、この実施例では工程省略化の価
値は一層高まるものと考えられる。
According to the above-mentioned embodiment, since the pattern transfer can be performed as a consistent process in vacuum as described above, it is possible to eliminate the trouble of repeatedly evacuation and improve production efficiency.
In particular, in the production of semiconductor devices with three-dimensional structures, which will become increasingly necessary in the future, if conventional methods were followed, the complexity associated with evacuation operations would increase, but this example omits the process. It is thought that the value of this technology will further increase.

また、従来の化学的現像過程では、レジスト高
分子鎖の切断、架橋に伴う現像速度変化を利用し
てエツチングを行うため、露光用ビーム5(第1
図)による励起された二次電子による露光部周辺
へのエネルギーの散逸が現像だれを生じ、マスク
パターンの転写分解能を高める上で大きな問題と
なつていたのに対し、上記実施例の方法は高いエ
ネルギー密度を必要とするレジストの解離、脱離
反応を利用するものであり、第2図X点より左側
に示すように、低いエネルギー密度では光エツチ
ングが検出できない程度に押えられることから二
次電子散逸部の現像ダレの効果をより低減でき
る。従つて従来よりも微細なパターン転写が可能
になる。
In addition, in the conventional chemical development process, the exposure beam 5 (the first
Dissipation of energy to the periphery of the exposed area by the excited secondary electrons due to It utilizes dissociation and desorption reactions in the resist that require energy density, and as shown to the left of point The effect of development sag in the dissipation area can be further reduced. Therefore, finer pattern transfer than before is possible.

上記の実施例では半導体結晶基板1を用いた
が、これはその他の基板であつてもよい。また、
レジスト3はポジ型レジストに限らずネガ型レジ
スト、あるいは有機高分子系膜等、要するに感放
射線薄膜層であれば全く同様の効果が得られる。
Although the semiconductor crystal substrate 1 is used in the above embodiment, it may be any other substrate. Also,
The resist 3 is not limited to a positive resist, but may be a negative resist, an organic polymer film, or the like, in short, the same effect can be obtained as long as it is a radiation-sensitive thin film layer.

なお、従来、紫外域に対する増感剤を添加した
ポリメチルメタクリレート(PMMA)にエキシ
マレーザ光を照射してパターンを形成した例が報
告されている(材原他:応用物理52巻1号(1983
年)P83)が、この発明は増感剤を添加しない市
販の感放射薄膜層に適用でき、照射部分のほとん
ど全部が除去できる点で、全く相違している。ま
た、エキシマ・レーザ光の波長は、もつとも短い
ものでも190nmであり、一般にこの種のマスク近
接型のパターン転写において、分解能を制約する
波動光学的ぼけの量dが、波長をλ、マスクと基
板の間隔をgとするとき、 d=0.4√・g2 ……(1) で与えられることを考えると、λ=190nmのレー
ザ光を用いてg=100μmとして転写を行つた場
合、ぼけ量dは(1)式より1.7μmとなる。
It has been reported that a pattern was formed by irradiating excimer laser light on polymethyl methacrylate (PMMA) containing a sensitizer for the ultraviolet region (Maihara et al.: Applied Physics Vol. 52, No. 1 (1983).
However, this invention is completely different in that it can be applied to a commercially available radiation-sensitive thin film layer without the addition of a sensitizer, and almost all of the irradiated area can be removed. Furthermore, the wavelength of excimer laser light is at most 190 nm, and in general, in this type of mask-proximity pattern transfer, the amount of wave optical blur d that limits the resolution is λ, the wavelength is λ, and the mask and substrate When the interval between is g, d=0.4√・g2...(1) Considering that it is given by, if the transfer is performed using a laser beam of λ=190nm and g=100μm, the amount of blur d is From formula (1), it is 1.7μm.

以上詳細に説明したように、この発明に係るパ
ターンの形成方法は、基板表面に形成された感放
射線薄膜層の所望の箇所にシンクロトロン放射光
を照射し、感放射線薄膜層を直接除去するように
したので、従来のエツチング方法で問題となつた
二次電子散逸部分の現像だれの効果を低減でき、
そのため従来よりも微細なパターン転写が可能で
ある。さらに、この発明は従来の現像液に対する
反応特性も考え併せたレジストの評価から、単に
放射光に対する反応特性のみに着目すればよいレ
ジスト評価への道を開くものであり、実際のパタ
ーン転写工程で用いられるレジストの選択上、融
通通性を高めることができる等の優れた利点を有
する。
As explained in detail above, the pattern forming method according to the present invention involves irradiating synchrotron radiation onto a desired location of a radiation-sensitive thin film layer formed on a substrate surface and directly removing the radiation-sensitive thin film layer. As a result, the effect of development sag in the secondary electron dissipation area, which was a problem with conventional etching methods, can be reduced.
Therefore, finer pattern transfer than before is possible. Furthermore, this invention opens the way from the conventional evaluation of resists that also takes into account the reaction characteristics to developing solutions to the evaluation of resists that only needs to focus on the reaction characteristics to synchrotron radiation. It has excellent advantages such as increased flexibility in selecting the resist used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜fは従来の半導体素子の製造工程を
説明するための図、第2図はシンクロトロン放射
光によるレジストの光エツチング現像の測定結果
を示す図、第3図a,bはクロスリンクにより分
子鎖架橋層が存在する場合のパターン形成方法を
説明するための図である。 図中、1は半導体結晶基板、2は絶縁体層、3
はレジスト、4はマスク、5は露光用ビーム、6
は真空装置、7は化学的現像液、8はエツチング
用ビーム、9は活性化処理、10はクロスリンク
層である。
Figures 1 a to f are diagrams for explaining the conventional manufacturing process of semiconductor devices, Figure 2 is a diagram showing the measurement results of resist photoetching development using synchrotron radiation, and Figures 3 a and b are cross-sectional views. FIG. 3 is a diagram for explaining a pattern forming method when a molecular chain crosslinked layer exists due to links. In the figure, 1 is a semiconductor crystal substrate, 2 is an insulator layer, and 3 is a semiconductor crystal substrate.
is a resist, 4 is a mask, 5 is an exposure beam, 6
7 is a vacuum device, 7 is a chemical developer, 8 is an etching beam, 9 is an activation process, and 10 is a crosslink layer.

Claims (1)

【特許請求の範囲】[Claims] 1 基板表面に形成した感放射線薄膜層に対し、
その表面の所望箇所にのみシンクロトロン放射光
を照射し、前記所望箇所のレジスト層を直接除去
して所要の微細パターンを形成することを特徴と
するパターンの形成方法。
1 For the radiation-sensitive thin film layer formed on the substrate surface,
A method for forming a pattern, which comprises irradiating synchrotron radiation only onto a desired location on the surface and directly removing the resist layer at the desired location to form a desired fine pattern.
JP58059674A 1983-04-05 1983-04-05 Formation of pattern Granted JPS59184525A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58059674A JPS59184525A (en) 1983-04-05 1983-04-05 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58059674A JPS59184525A (en) 1983-04-05 1983-04-05 Formation of pattern

Publications (2)

Publication Number Publication Date
JPS59184525A JPS59184525A (en) 1984-10-19
JPH0427686B2 true JPH0427686B2 (en) 1992-05-12

Family

ID=13119972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58059674A Granted JPS59184525A (en) 1983-04-05 1983-04-05 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS59184525A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022071380A (en) * 2020-10-28 2022-05-16 日本ゲームカード株式会社 Paper sheet carrying device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022071380A (en) * 2020-10-28 2022-05-16 日本ゲームカード株式会社 Paper sheet carrying device

Also Published As

Publication number Publication date
JPS59184525A (en) 1984-10-19

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