JPH04274614A - Pulse circuit - Google Patents

Abstract

PURPOSE:To prevent a notch from being caused in an output pulse when an output pulse width wider than a basic pulse width is generated. CONSTITUTION:Three kinds of pulses, a basic pulse A, a 1st delay pulse C and a 2nd delay pulse B to cover a portion which are not covered by the pulses A, C in terms of timing are inputted to a 3-input NAND circuit 5, from which a synthesis pulse D is generated and it is fed to an inverter 6, from which an inverted final output pulse E is outputted. Since the 2nd delay pulse B covers the gap portion between the basic pulse A and the 1st delay pulse C, a synthesis pulse in which no notch is caused for the portion is obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse circuit, and more particularly to a pulse circuit that changes pulse width.

0002

[Prior Art] Conventional pulse circuits process the pulse width of an input basic pulse to widen the pulse width.
It is configured as shown in FIG.

By inputting the basic pulse A into a series circuit of a plurality of inverters 1 to 4, a delayed pulse C is generated by delaying the basic pulse A. This delayed pulse C and basic pulse A are connected to a two-input AND circuit (hereinafter referred to as an "AND circuit").
(referred to as a "NAND circuit") 51 to generate an inverted composite pulse D. By inverting this inverted composite pulse D with an inverter 6, a final output pulse E having a wider pulse width than the basic pulse A is produced.

The operation of the pulse circuit shown in FIG. 3 will be explained in detail with reference to the timing chart shown in FIG.

By inputting the basic pulse A and the delayed pulse C to the 2-input NAND circuit 51, if either the basic pulse A or the delayed pulse C is "L" (low level), the 2-input NAND circuit 51 The circuit 51 outputs "H" (high level). Therefore, as a result, 2 inputs N
The AND circuit 51 outputs an inverted composite pulse D having the opposite polarity of the basic pulse A and the delayed pulse C. Next, since the inverted composite pulse D has the opposite polarity to the basic pulse A,
The polarity of the inverted composite pulse D is inverted by the inverter 6,
It has the same polarity as the basic pulse A and is output as the final output pulse E.

[0006]

[Problems to be Solved by the Invention] In the conventional pulse circuit described above, only the basic pulse A and the delayed pulse C are
It is synthesized by an ND circuit. Therefore, when the pulse width of basic pulse A is wider than the delay time width of delayed pulse C, as in the case of the timing chart in FIG. 4, the pulse periods of basic pulse A and delayed pulse C overlap. In this case, a normal composite pulse E (without a "bump" to be described later) can be output. However, as in the case of FIG. 5, when the pulse width of basic pulse A is narrower than the delay time width of delayed pulse C, the pulse periods of basic pulse A and delayed pulse C do not overlap and the pulse periods of both pulses are different. A gap is created in between, and in this gap, neither of the two inputs of the two-input NAND circuit 51 becomes "L" during pulse synthesis. Therefore, there is a problem in that a composite pulse E having a "bump" as shown in the figure is output at that portion.

The present invention has been made in view of such problems, and provides a pulse circuit that can output a normal pulse with a wider pulse width of the basic pulse even when the pulse width of the basic pulse is narrow. The purpose is to

[0008]

[Means for Solving the Problems] A pulse circuit according to the present invention includes a plurality of inverters, a first delayed pulse in which the basic pulse is delayed by at least a part of the plurality of inverters, and a first delay pulse in which the basic pulse is delayed by at least a part of the plurality of inverters; The fundamental pulse is delayed by a part of the inverter of
a second pulse timing with a pulse timing intermediate to the delayed pulse of
and a logic gate circuit to which the basic pulse is input, and is characterized in that it generates a pulse having a wider pulse width than the basic pulse.

[0009]

[Operation] In the pulse circuit of the present invention, by inputting another delayed pulse into the 3-input NAND circuit to which the fundamental pulse and the delayed pulse are inputted, a "hump" is generated. ” to prevent the occurrence of

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows the configuration of a pulse circuit according to an embodiment of the present invention.

The pulse circuit shown in FIG. 1 has a 3-input NAND circuit 51 in place of the 2-input NAND circuit 51 in the configuration shown in FIG.
The configuration is such that the output of the intermediate inverter 2 is inputted to the three-input NAND 5 along with the basic pulse A and the output delayed pulse C of the final stage inverter 4.

[0013] In such a configuration, 3-input NAND
In addition to the basic pulse A and the first delayed pulse C delayed by the inverter circuits 1 to 4, the circuit 5 has a delay time of 1/2 of that of the first delayed pulse C and the same polarity for correction purposes. input the second delayed pulse B of . As a result, during pulse synthesis, one of the inputs of the 3-input NAND circuit 5
Since the “L” potential is always input to the 3-input NAN
The output pulse D of the D circuit 5 is a pulse without a "bump". Since the pulse D has a polarity opposite to that of the basic pulse A, the inverter 6 generates a final output pulse E having the same polarity.

In this way, by inputting the second delayed pulse B of the same polarity having a pulse timing between the basic pulse A and the first delayed pulse C to the 3-input NAND circuit 5, it is possible to , Since the "L" potential is input to at least one input of the 3-input NAND circuit 5, even when the pulse width of the basic pulse A is narrow, the output pulse E has a "L" potential.
No more bumps.

The present invention is not limited to the embodiments described above; for example, a larger number of inverters may be connected in cascade to delay the fundamental pulse; in such a case, the second The delayed pulse may be extracted and input to a multi-input NAND circuit. In addition, the present invention can be implemented with various modifications.

[0016]

As described above, according to the present invention, in the three-input NAND circuit to which the basic pulse and the delayed pulse are input, another delayed pulse is input in the gap between the pulse periods of the basic pulse and the delayed pulse. By doing so, it is possible to provide a pulse circuit that can output a normal pulse with a wider pulse width of the basic pulse even when the pulse width of the basic pulse is narrow.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a pulse circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing pulse timing of each part in FIG. 1;

FIG. 3 is a circuit diagram showing the configuration of an example of a conventional pulse circuit.

FIG. 4 is a diagram showing pulse timing of each part in FIG. 3;

FIG. 5 is a diagram showing the pulse timing of each part when there is a problem in FIG. 3;

[Explanation of symbols]

1 to 4; Delay inverter 5; NAND circuit 6; Inverter for polarity reversal

Claims (2)

[Claims] 1. A plurality of inverters, a first delayed pulse in which the fundamental pulse is delayed by at least some of the plurality of inverters, and a first delayed pulse in which the fundamental pulse is delayed by some of the plurality of inverters; A second delayed pulse having a pulse timing intermediate between the basic pulse and the first delayed pulse, and a logic gate circuit to which the basic pulse is input, the second delayed pulse having a pulse width wider than the basic pulse. A pulse circuit characterized by generating. 2. The plurality of inverters are connected in cascade so that a basic pulse is inputted to one end thereof, and a first delayed pulse is outputted from the other end, and a plurality of second delayed pulses are outputted from a plurality of intermediate points. 2. The pulse circuit according to claim 1, wherein the plurality of second delayed pulses are supplied to the logic gate circuit together with the basic pulse and the first delayed pulse.