JPH04273665A - Pll circuit for video signal - Google Patents

Abstract

PURPOSE:To match the phase of a horizontal synchronizing signal with a phase of an internal horizontal synchronizing signal by generating a frequency division start signal generating the internal horizontal synchronizing signal from a selected head pulse and generating the internal horizontal synchronizing signal according to the frequency division start signal. CONSTITUTION:A differentiating circuit 2 outputs a 1st head pulse representing a head position of an input horizontal synchronizing signal 10. A phase difference monitor circuit 8 monitors a phase difference of a phase difference signal 60 and outputs and head pulse selection signal 80 to select a 1st head pulse 40 when the setting range is exceeded and to select a 2nd head pulse 45 when the difference is within the set range. A head pulse selection circuit 9 uses the head pulse selection signal 80 to either the 1st head pulse 40 or the 2nd head pulse 45 and generates a start point signal 90 to set a frequency division start point of a frequency divider circuit 4 based on the selected head pulse.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention provides an input horizontal synchronizing signal having a frequency fH and an internal horizontal synchronizing signal having a frequency fH, which is obtained by dividing a sampling clock having a frequency f0 that samples an input video signal, and an internal horizontal synchronizing signal having a frequency fH0, which is generated by dividing the sampling clock.
The present invention relates to a video signal PLL circuit that generates a sampling clock and an internal horizontal synchronization signal such that 0=nfH (n is an integer) and fH0=fH (same phase).

0002

2. Description of the Related Art In a conventional example, a sampling clock with a frequency f0 for sampling an input video signal and an internal horizontal synchronization signal with a frequency fH0 generated by dividing the sampling clock are combined with an input horizontal synchronization signal with a frequency fH and f0=
When generating a sampling clock and an internal horizontal synchronization signal such that nfH (n is an integer) and fH0 = fH (same phase), the first phase comparison signal is generated from the input horizontal synchronization signal as shown in Figure 3. a first comparison signal generation circuit 1 that generates a sampling clock, a voltage controlled oscillator 3 that generates a sampling clock, a frequency divider circuit 4 that divides the sampling clock into 1/n to generate an internal horizontal synchronization signal, and an internal horizontal synchronization signal. a second comparison signal generation circuit 5 that generates a second phase comparison signal from the signal; and a phase comparison circuit 6 that compares the phases of the first comparison signal generation circuit 1 and the second comparison signal generation circuit 5 and generates a phase difference signal. , has a phase difference conversion circuit 7 that generates a control signal for the oscillation frequency of the voltage controlled oscillator 3 from the phase difference signal.

0003

[Problem to be Solved by the Invention] As described above, in the conventional circuit, when the frequency of the sampling clock output from the voltage controlled oscillator deviates by a large amount from f0 because the frequency division start point is not set in the frequency dividing circuit. Alternatively, when a new video signal is input, there is a drawback that the input horizontal synchronization signal and internal horizontal synchronization signal are largely out of phase by the time f0=nfH (n is an integer) and fH0=fH (same phase). . In particular, in devices that convert image signals into digital signals, compress the bandwidth, and then transmit the data, a range that can be seen on the screen (excluding synchronization, color burst signals, etc.) is set as a means of bandwidth compression, and data within that range is transmitted. During transmission, the phase shift between the input horizontal synchronization signal and the internal horizontal synchronization signal will appear on the screen as a shift in the range.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate such drawbacks and to provide a PLL circuit for video signals having means for shortening the phase alignment time between a horizontal synchronizing signal and an internal horizontal synchronizing signal.

[0005]

[Means for Solving the Problems] The present invention provides a terminal for inputting an input horizontal synchronizing signal of frequency fH, which is a horizontal synchronizing signal of an input video signal, and a first terminal for generating a first phase comparison signal from the input horizontal synchronizing signal. A phase comparison signal generation circuit and a frequency f0 for sampling the input video signal (where f0=n・f
A voltage controlled oscillator that generates a sampling clock of H (n is an integer)), an internal horizontal synchronization signal of frequency fH0 (where fH0 = fH) generated by dividing the sampling clock by 1/n, and the start position of this signal. a frequency divider circuit that generates a second leading pulse that indicates the phase difference between the first phase comparison signal and the second phase comparison signal; A P for video signals comprising a phase comparison circuit that performs comparison and generates a phase difference signal, and a phase difference conversion circuit that generates a control signal for the oscillation frequency of the voltage controlled oscillator from the phase difference signal.
The LL circuit includes a differentiating circuit that generates a first leading pulse indicating the leading position of the input horizontal synchronizing signal, and a differential circuit that monitors a phase difference signal and selects either the first leading pulse or the second leading pulse according to the amount of this phase difference. a phase difference monitoring circuit that generates a leading pulse selection signal, and a phase difference monitoring circuit that selects either the first leading pulse or the second leading pulse based on the leading pulse selection signal, and divides the frequency of the frequency dividing circuit from the selected leading pulse. The present invention is characterized by comprising a leading pulse selection circuit that generates a starting point signal for setting a starting point.

[0006]

[Operation] Detects the first pulse indicating the beginning of the input horizontal sync signal and the internal horizontal sync signal, and detects the phase difference between the input horizontal sync signal and the internal horizontal sync signal in the phase comparison circuit. In addition to controlling the oscillation frequency of the voltage-controlled oscillator that generates the sampling clock according to the
One of the two leading pulses is selected, and a frequency division start signal for a frequency dividing circuit that generates an internal horizontal synchronizing signal is generated from the selected leading pulse. The frequency dividing circuit divides the frequency of the sampling clock according to the frequency division start signal to generate an internal horizontal synchronization signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a PLL circuit for video signals according to the present invention.

As shown in FIG. 1, this embodiment has a terminal for inputting an input horizontal synchronizing signal 10 of frequency fH which is a horizontal synchronizing signal of an input video signal, and a terminal for inputting a first phase comparison signal 50 from the input horizontal synchronizing signal 10. a first comparison signal generation circuit 1 that generates a signal, a voltage controlled oscillator 3 that generates a sampling clock 30 of a frequency f0 (where f0 = n·fH (n is an integer)) that samples an input video signal, and a sampling clock 30 that samples an input video signal. The frequency fH0 (
However, a frequency divider circuit 4 that generates an internal horizontal synchronizing signal 20 of fH0=fH) and a second leading pulse 45 indicating the leading position of this signal, and a frequency dividing circuit 4 that generates a second phase comparison signal 55 from the internal horizontal synchronizing signal 20. two comparison signal generation circuits 5; a phase comparison circuit 6 that compares the phases of the first phase comparison signal 50 and the second phase comparison signal 55 and generates a phase difference signal 60; and the voltage controlled oscillator 3 based on the phase difference signal 60. and a phase difference conversion circuit 7 that generates a control signal 70 with an oscillation frequency of 2, and a leading pulse selection signal 80 that monitors the phase difference signal 60 and selects either the first leading pulse 40 or the second leading pulse 45 according to the phase difference amount.
The phase difference monitoring circuit 8 generates a phase difference monitoring circuit 8, and the first pulse selection signal 80 selects either the first leading pulse 40 or the second leading pulse 45, and the frequency dividing circuit 4 divides the frequency from the selected leading pulse. It includes a leading pulse selection circuit 9 that generates a starting point signal 90 for setting a starting point.

Next, the operation of this embodiment will be explained. First, the first comparison signal generation circuit 1 outputs the first phase comparison signal 50 from the input horizontal synchronization signal 10. Further, the differentiating circuit 2 outputs a first leading pulse 40 indicating the beginning of the horizontal synchronizing signal from the input horizontal synchronizing signal 10. On the other hand, the sampling clock 30 generated by the voltage controlled oscillator 3 is supplied to the frequency dividing circuit 4.
The internal horizontal synchronizing signal 20 is frequency-divided by 1/n and a second leading pulse 45 indicating the leading end of the internal horizontal synchronizing signal is output. In the second comparison signal generation circuit 5, the internal horizontal synchronization signal 20
A second phase comparison signal 55 is output from. Phase comparison circuit 6
Then, the first phase comparison signal 50 and the second phase comparison signal 55 are compared in phase, and the phase difference signal 60 is output. The phase difference conversion circuit 7 converts the phase difference signal 60 into the voltage controlled oscillator 3.
A control signal 70 is output for controlling the oscillation frequency of the oscillation frequency. The oscillation frequency of the voltage controlled oscillator 3 is changed by the control signal 70. The phase difference monitoring circuit 8 monitors the amount of phase difference of the phase difference signal 60, and when the amount of phase difference exceeds a preset range, a leading pulse selection circuit 9 (described later) selects the first leading pulse 40. , and when the amount of phase difference is within a preset range, a leading pulse selection signal 80 for selecting the second leading pulse 45 is output. In the leading pulse selection circuit 9, the leading pulse selection signal 8
0, the first leading pulse 40 and the second leading pulse 45 are selected, and a starting point signal 90 for setting the frequency division start point of the frequency dividing circuit 4 is output from the selected leading pulse. That is, input horizontal synchronization signal 10 and internal horizontal synchronization signal 2
0, the frequency division start point of the frequency divider circuit 4 is forcibly set to the top position of the input horizontal synchronization signal 10, in other words, the start point of the internal horizontal synchronization signal 20 is forcibly set. This brings the input horizontal synchronization signal 10 and the internal horizontal synchronization signal 20 into phase. FIG. 2 shows its operation timing.

0010

Effects of the Invention As explained above, the present invention forcibly sets the starting point of the internal horizontal synchronizing signal, so it can be used even if the frequency of the sampling clock deviates from f0 or when a new video signal is input. When the input horizontal synchronizing signal and internal horizontal synchronizing signal are largely out of phase, the input horizontal synchronizing signal and internal horizontal synchronizing signal are This has the effect of reducing the phase difference.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing diagram showing the operation of the embodiment of the present invention.

FIG. 3 is a block configuration diagram showing the configuration of a conventional example.

[Explanation of symbols]

1 First comparison signal generation circuit 2 Differential circuit 3 Voltage controlled oscillator 4 Frequency divider circuit 5 Second comparison signal generation circuit 6 Phase comparison circuit 7 Phase difference conversion circuit 8 Phase difference monitoring circuit 9 Leading pulse selection circuit 10 Input horizontal synchronization signal 20 Internal horizontal synchronization signal 30 Sampling clock 40 First leading pulse 45 Second leading pulse 50 First phase comparison signal 55 Second phase comparison signal 60 Phase difference signal 70 Control signal 80 Start pulse selection signal 90 Start point signal

Claims (1)

[Claims] 1. A terminal for inputting an input horizontal synchronizing signal having a frequency fH, which is a horizontal synchronizing signal of an input video signal; a first phase comparison signal generation circuit for generating a first phase comparison signal from the input horizontal synchronizing signal; A voltage controlled oscillator generates a sampling clock with a frequency f0 (where f0=n・FH (n is an integer)) for sampling a video signal, and a voltage controlled oscillator generates a sampling clock with a frequency fH0 (where f0=n・FH (n is an integer)), which is generated by dividing the sampling clock by 1/n.
However, a frequency dividing circuit that generates an internal horizontal synchronizing signal of fH0=fH) and a second leading pulse indicating the leading position of this signal, and a second phase comparison signal generator that generates a second phase comparison signal from the internal horizontal synchronizing signal a phase comparison circuit that compares the phases of a first phase comparison signal and a second phase comparison signal to generate a phase difference signal; and a phase difference circuit that generates a control signal for the oscillation frequency of the voltage controlled oscillator from the phase difference signal. A PLL circuit for video signals includes a conversion circuit, a differentiation circuit that generates a first leading pulse indicating the leading position of an input horizontal synchronizing signal, and a differential circuit that monitors a phase difference signal and outputs the first leading pulse or the first leading pulse according to the amount of the phase difference. A phase difference monitoring circuit that generates a leading pulse selection signal that selects one of the two leading pulses, and a phase difference monitoring circuit that selects either the first leading pulse or the second leading pulse by the leading pulse selection signal, and selects either the first leading pulse or the second leading pulse, and A PLL circuit for a video signal, comprising a leading pulse selection circuit that generates a start point signal for setting a frequency division start point of the frequency dividing circuit from the pulse.