JPH04273140A - Semiconductor integrated circuit package - Google Patents

Semiconductor integrated circuit package

Info

Publication number
JPH04273140A
JPH04273140A JP3033771A JP3377191A JPH04273140A JP H04273140 A JPH04273140 A JP H04273140A JP 3033771 A JP3033771 A JP 3033771A JP 3377191 A JP3377191 A JP 3377191A JP H04273140 A JPH04273140 A JP H04273140A
Authority
JP
Japan
Prior art keywords
package
pattern
integrated circuit
semiconductor integrated
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3033771A
Other languages
Japanese (ja)
Inventor
Hitoshi Ishizuki
石附　仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3033771A priority Critical patent/JPH04273140A/en
Publication of JPH04273140A publication Critical patent/JPH04273140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make it possible to cut electrically a specific terminal with ease and remodel, allowing an IC package to be mounted on a printed board as it is, and further realize high density mount and improve equipment performance by cutting down a conductor surface on the surface of a package without removing said IC package from the printed board and lifting an outer terminal of the IC package from the printed board. CONSTITUTION:A signal pin of an integrated circuit is electrically connected with a package outer lead 4 by way of a surface conductor pattern 1 formed on the surface of the package while the surface conductor is partially extended in width and used as a remodel layout pad 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は半導体集積回路パッケー
ジに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit packages.

【０００２】0002

【従来の技術】従来、この種の半導体集積回路パッケー
ジ（以下ＩＣパッケージと呼ぶ）は、図３（ａ），（ｂ
）あるいは図４に示すように、ＩＣパッケージ内部を通
る導体パターンを介してＩＣの端子からＩＣパッケージ
外部端子部分と電気的に接続されており、その接続はい
っさい外部からは見えない構造となっていた。[Prior Art] Conventionally, this type of semiconductor integrated circuit package (hereinafter referred to as an IC package) is shown in FIGS. 3(a) and 3(b).
) Or, as shown in Figure 4, the terminals of the IC are electrically connected to the external terminals of the IC package via a conductor pattern that runs inside the IC package, and the connection is completely invisible from the outside. Ta.

【０００３】図３（ａ）ではパターン１４を切断するた
めにはＩＣパッケージを一度とりはずし、パターン１４
を切断しなければならない。また図４のようにＩＣパッ
ケージ１０の外側にパターン１４を出し、その端からス
ルーホールを介し内層パターンに接続している場合はＩ
Ｃパッケージ１０をとりはずさなくてもパターン１４を
切断することはできるが、パターン１４を外側に出した
分、ＩＣ１ケ当りの占有面積が大きくなるので、ＩＣパ
ッケージ１０間の距離が長くなり性能がおちると共にＩ
Ｃパッケージ１０が多ピン化された場合、すべてのピン
をパターンで外に引きだすことが困難となる。In FIG. 3(a), in order to cut the pattern 14, the IC package is removed once and the pattern 14 is cut.
must be cut. In addition, as shown in FIG. 4, if the pattern 14 is provided on the outside of the IC package 10 and connected to the inner layer pattern through a through hole from the end, the I
Although the pattern 14 can be cut without removing the C package 10, the area occupied by each IC increases as the pattern 14 is placed outside, which increases the distance between the IC packages 10 and reduces performance. As I fall I
When the C package 10 has a large number of pins, it becomes difficult to draw out all the pins in a pattern.

【０００４】0004

【発明が解決しようとする課題】上述した従来の半導体
集積回路パッケージは、ＩＣの端子はパッケージ内部に
構成されている導体パターンを介してＩＣパッケージの
外部端子と接続されているため、一度プリント配線板上
に実装してしまうと、パターンの改造が必要となった際
、不要パターンを切断するためにＩＣパッケージを取り
外し、改造しなければならない可能性があるため、改造
時間がかかりかつ信頼性が悪化する欠点がある。またプ
リント配線板上に改造用のパターンを持つのが一般的で
あるが、信号ピン数が多くなると改造用のパッドやスル
ーホールの領域がＩＣパッケージの領域よりも大きな領
域を必要とし、プリント配線板上への高密度実装の妨げ
となると共にＩＣパッケージ相互間の配線が長くなり、
性能が低下するという欠点がある。[Problems to be Solved by the Invention] In the conventional semiconductor integrated circuit package described above, since the terminals of the IC are connected to the external terminals of the IC package via the conductor pattern configured inside the package, it is difficult to connect the printed wiring once. If it is mounted on a board, when the pattern needs to be modified, the IC package may have to be removed and modified in order to cut out unnecessary patterns, which takes time and reduces reliability. There are flaws that worsen. In addition, it is common to have a pattern for modification on a printed wiring board, but as the number of signal pins increases, the area for pads and through holes for modification requires a larger area than the area of the IC package. This impedes high-density mounting on the board and increases the length of wiring between IC packages.
The disadvantage is that performance deteriorates.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体集積回路
パッケージはＩＣチップの端子とＩＣパッケージ外部の
端子とを電気的に接続するための導出パターンをパッケ
ージ表面に構成し、かつ前記導体パターンの一部の幅を
拡げることにより改造布線用のパッドとして使用できる
構造となっている。[Means for Solving the Problems] A semiconductor integrated circuit package of the present invention comprises a lead-out pattern on the package surface for electrically connecting terminals of an IC chip and terminals outside the IC package, and a lead-out pattern for electrically connecting terminals of an IC chip and terminals outside the IC package. By widening part of the width, it can be used as a pad for modified wiring.

【０００６】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図１（ａ），（ｂ）は本発明の一実施例を示す平面
図、および断面図である。ＩＣチップ５の端子７はチッ
プーパッケージ接続用導線６によりパッケージ内部パッ
ド８を経由してパッケージ内導体パターン３と接続され
ている。導体パターン３はパッケージの表面にある改造
用パッド２と表面導体パターン１を介してＩＣパッケー
ジ１０の外部リード線４と接続されている。つまりＩＣ
チップ５の端子７はパッケージリード線４と電気的に接
続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of the present invention. The terminals 7 of the IC chip 5 are connected to the internal package conductor pattern 3 via the package internal pads 8 by chip-package connecting conductors 6. The conductor pattern 3 is connected to the external lead wire 4 of the IC package 10 via the modification pad 2 on the surface of the package and the surface conductor pattern 1. In other words, I.C.
Terminals 7 of chip 5 are electrically connected to package lead wires 4.

【０００７】ＩＣパッケージ１０はプリント配線板１３
の上に実装され、ＩＣパッケージのリード線４はプリン
ト配線板１３上のパッド９に取りつけられる。プリント
配線板上ではパッド９よりでたパターンがスルーホール
１５に接続され、プリント板内層のパターン等を介して
、他の電子部品に接続される。ここでプリント板の内層
パターン断線による改造あるいは論理変更によりピン接
続が変わった時は現在のパターンをカットしあらたに布
線をする必要がある。[0007] The IC package 10 is a printed wiring board 13
The lead wires 4 of the IC package are attached to the pads 9 on the printed wiring board 13. On the printed wiring board, the pattern coming out from the pad 9 is connected to the through hole 15, and connected to other electronic components via the pattern on the inner layer of the printed wiring board. If the pin connections change due to modification due to disconnection of the inner layer pattern of the printed circuit board or logic change, it is necessary to cut the current pattern and rewire.

【０００８】図２（ａ），（ｂ）は本発明の一使用例を
示す平面図および断面図である。ＩＣパッケージ表面パ
ターン１を表面導体パターン切断部１１のように一部カ
ットすれば、切断は容易にできるようになる。また改造
布線を行うのにＩＣパッケージ表面の改造布線用パッド
２を使用することにより、容易にできる。FIGS. 2(a) and 2(b) are a plan view and a sectional view showing an example of the use of the present invention. Cutting can be easily performed by cutting a portion of the IC package surface pattern 1 like the surface conductor pattern cutting portion 11. Further, modification wiring can be easily performed by using the modification wiring pad 2 on the surface of the IC package.

【０００９】[0009]

【発明の効果】以上説明したように本発明は、ＩＣチッ
プの端子とパッケージ外部の端子とを電気的に接続する
ための導体パターンをパッケージ表面に構成し、さらに
前記導体パターン上に改造布線ができるようなパッドを
設けることにより、ＩＣパッケージをプリント板から外
したり、ＩＣパッケージの外部端子をプリント板より持
ち上げることなく、パッケージ表面の導体パターンを切
断するだけで特定の端子の電気的切断が容易に行え、さ
らに導体パターン上に設けたパッドを布線用パッドとす
ることにより、プリント板にＩＣパッケージを載せたま
ま、改造が可能となる効果がある。また、プリント板に
改造用パターンおよびパッドを設ける必要がなくなるた
め高密度実装に対応できる。As explained above, the present invention comprises a conductive pattern on the surface of the package for electrically connecting terminals of an IC chip and terminals outside the package, and further includes modified wiring on the conductive pattern. By providing pads that allow for electrical disconnection of specific terminals, it is possible to electrically disconnect specific terminals by simply cutting the conductor pattern on the surface of the package, without removing the IC package from the printed circuit board or lifting the external terminals of the IC package from the printed circuit board. This is easy to do, and furthermore, by using the pads provided on the conductor pattern as wiring pads, it is possible to modify the printed circuit board while the IC package is still mounted thereon. Furthermore, since there is no need to provide modification patterns and pads on the printed board, high-density mounting can be accommodated.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】（ａ），（ｂ）は本発明の一実施例を示す平面
図および断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view showing an embodiment of the present invention.

【図２】（ａ），（ｂ）は本発明の一使用例を示す平面
図および断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view showing an example of use of the present invention.

【図３】（ａ），（ｂ）は従来の第１の例を示す平面図
および断面図である。FIGS. 3(a) and 3(b) are a plan view and a sectional view showing a first conventional example.

【図４】従来の第２の例を示す平面図である。FIG. 4 is a plan view showing a second conventional example.

【符号の説明】[Explanation of symbols]

１　　　　表面導体パターン ２　　　　改造布線用パッド ３　　　　内部導体パターン ４　　　　パッケージ外部リード ５　　　　ＩＣチップ ６　　　　チップ−パッケージ接続線 ７　　　　ＩＣパッド ８　　　　パッケージ内部パッド ９　　　　プリント板パッド １０　　　　半導体集積回路パッケージ１１　　　　表
面導体パターン切断部 １２　　　　プリント板内層パターン １３　　　　プリント板 １４　　　　プリント板表面パターン １５　　　　プリント板内スルーホール１６　　　　Ｉ
Ｃ保護キャップ1 Surface conductor pattern 2 Modified wiring pad 3 Internal conductor pattern 4 Package external lead 5 IC chip 6 Chip-package connection line 7 IC pad 8 Package internal pad 9 Printed board pad 10 Semiconductor integrated circuit package 11 Surface conductor pattern cutting section 12 Printed board inner layer pattern 13 Printed board 14 Printed board surface pattern 15 Printed board internal through hole 16 I
C protection cap

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　集積回路の信号ピンがパッケージ表面
に構成されている導体パターンを経由し、パッケージ外
部のリードと電気的に接続され、導体パターンの一部は
巾を広げてあり、布線用のパッドとして使用できること
を特徴とする半導体集積回路パッケージ。Claim 1: A signal pin of an integrated circuit is electrically connected to a lead outside the package via a conductor pattern formed on the surface of the package, and a part of the conductor pattern is widened, and is used for wiring. A semiconductor integrated circuit package characterized in that it can be used as a pad.
JP3033771A 1991-02-28 1991-02-28 Semiconductor integrated circuit package Pending JPH04273140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3033771A JPH04273140A (en) 1991-02-28 1991-02-28 Semiconductor integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3033771A JPH04273140A (en) 1991-02-28 1991-02-28 Semiconductor integrated circuit package

Publications (1)

Publication Number Publication Date
JPH04273140A true JPH04273140A (en) 1992-09-29

Family

ID=12395716

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3033771A Pending JPH04273140A (en) 1991-02-28 1991-02-28 Semiconductor integrated circuit package

Country Status (1)

Country Link
JP (1) JPH04273140A (en)

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