JPH04271291A - Capstan servo controller - Google Patents

Abstract

PURPOSE:To shorten response time in phase control of capstan by providing a speed offset means for compensating the speed control when phase error information outputted from a phase comparing means exceeds a preset phase error threshold. CONSTITUTION:A reference signal outputted from a reference signal generating circuit 21 is subjected to phase shift by the amount of tracking variation through a variable delay circuit 15 and then fed, as a capstan phase control reference signal (e), to a phase control circuit 35. On the other hand, a control signal recorded on a magnetic tape is reproduced through a control head 12 and then processed through a control signal reproducing unit 13 and fed, as a reproduction control signal (f), to the phase control circuit 35. The phase control circuit 35 operates the phase difference (g) between the reproduced control signal (f) and the capstan phase control reference signal (e) and delivers speed offset data (h), corresponding to phase difference thresholds set in step by a speed offset command unit 36, to a speed command signal generator 8 thus modifying a target speed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capstan servo control device that replaces capstan phase control information with speed control information to control a motor and shorten the capstan servo pull-in time.

0002

2. Description of the Related Art In a helical scan magnetic recording/reproducing device (hereinafter referred to as a VTR) using a magnetic tape as a recording medium, a video signal is recorded on a video track formed diagonally on the magnetic tape. - the signal is recorded. When reproducing a video signal from such a magnetic tape, the rotational phase of the capstan motor is controlled according to the phase difference between the control signal and a separately generated capstan phase reference signal. The aim is to stabilize the running speed of the vehicle.

[0003] VTRs are designed to have multiple functions, high image quality, and improved dubbing performance.
began to attract attention. An example of this is “Propose”.
dAmerican National Stan
dard” V16.87-441 and “Television Society Journal” Vol. 42, No. 5 (1988) pp. 498
- D recording a composite video signal at 502;
-2 format standard VTR is described. This VTR can reproduce beautiful images without noise in a wide variety of variable speed reproductions. Furthermore, it is equipped with advanced editing functions such as insert and assemble, greatly improving usability.

0004

[Problems to be Solved by the Invention] However, the above-mentioned prior art does not take into account the responsiveness of the capstan, especially the shortening of the pull-in time of phase control, and the responsiveness of the tape running to the operation is poor. There was also the problem that the image output time from stop to playback becomes long.

An object of the present invention is to solve this problem by shortening the capstan phase pull-in time, improving the responsiveness of tape running to operations, and improving the capstan phase so that images and sounds can be output immediately from stop to playback. An object of the present invention is to provide a capstan servo control device equipped with a control circuit.

[0006]

[Means for Solving the Problems] In order to achieve the above object, a control signal reproduced from a tape and a phase control reference signal are compared through a phase comparison means when the capstan is in a phase control operation state. When controlling the rotational phase of the capstan motor by means of a motor, a means for detecting that the capstan speed has sufficiently approached the target speed, a phase control means for operating by confirming the detection signal, and an output from the phase comparison means. A speed offset means is provided for compensating for the phase error information by the speed control means when the phase error information exceeds a preset phase error threshold. Note that the speed offset means described above is operated in the operating range of the phase control means.

Furthermore, means is provided for stopping the operation of the speed offset means when the early reproduction control signal is not detected for a certain period of time. This prevents the speed offset means from malfunctioning.

[0008] Furthermore, when performing phase control in a state where the capstan phase is slightly shifted (referred to as a phase unlocked state), there is provided a means for determining whether the current speed control means is in the acceleration direction or the deceleration direction. , means for determining whether the phase control means is in advanced phase control or lagging phase control, and a determination signal of speed control and phase control based on the determination signal output from the speed control and the determination signal output from the phase control. Means is provided for detecting the acceleration/deceleration direction and lowering the gain of the speed control if the acceleration/deceleration direction of the speed control during the phase control operation is different from the acceleration/deceleration direction of the phase control.

The present invention also includes means for starting phase control operation from near the target phase after the capstan speed sufficiently approaches the target value, and means for slightly shifting the target speed from the original target speed before starting the phase control operation. The device is provided with means for starting the capstan at a speed that has been set, and means for switching the target speed to the original speed when the vicinity of the target phase is detected.

[0010] Furthermore, the apparatus is provided with an integrating means for accumulating the polarity of the speed acceleration/deceleration signal for speed control, and means for using the integrated information as a capstan phase control signal during recording.

[0011]

[Operation] When transitioning from a stopped state to normal playback, the phase control means starts from a state sufficiently close to the target speed (velocity lock-in), and controls the control signal and phase control reference reproduced from the tape. If the phase difference with the signal is greater than or equal to a preset phase difference, the phase difference information is converted into speed control information, and a speed offset is added to the target command speed. This allows the phase control signal to be replaced with the speed control signal, thereby increasing responsiveness. Furthermore, since capstan phase control can be realized without passing through a phase compensation filter or the like in the phase control loop, the phase lock-in time of the capstan can be made faster. Further, in order to prevent malfunction of the speed offset means, means is provided for stopping the operation of the speed offset means when the reproduction controller signal is not detected for a certain period of time.

Next, when the polarity of the acceleration/deceleration control of the speed control means and the polarity of the acceleration/deceleration control of the phase control means do not match, the gain of the phase control means is lowered. By doing so, it is possible to reduce the operating region of the phase control that causes disturbance in the speed control, and it is possible to shorten the capstan phase pull-in time.

Furthermore, the capstan phase control start timing is set near the target phase, and the speed control target value at that time is:
Drives at a speed slightly different from the original target value. After that, when it locks into the target position, it operates to switch to the original target value. This allows the phase control pull-in time to be shortened.

As described above, by shortening these phase control response times, the responsiveness of the capstan is improved, and the image output and audio output times from stop to playback can be shortened.

[0015]

Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 to 10. In FIG. 1, 1 is a magnetic tape, 2 is a capstan, 3 is a capstan motor, 4 is a capstan rotation speed detector, 5 is a capstan speed control circuit, 6 is an adder, and 8 is a reproduction circuit speed command. A signal generator, 10 a speed command input terminal, 12 a control signal reproducing head,
13 is a control signal reproducing circuit, 15 is a variable delay means for tracking, 16 is a tack rotation phase detection head, 1
7 is a drum motor rotation speed detector, 18 is an adder, 19
2 is a drum speed control circuit; 20 is a drum phase control circuit;
1 is a reference signal generation circuit, 35 is a capstan phase control circuit, and 36 is a speed offset.

Next, its operation will be explained. The magnetic tape 1 is transferred by a capstan motor 3 which rotates a capstan 2. Drive control of the capstan motor consists of speed control and phase control, and the speed control will be explained first. The rotation unit of the capstan motor 3 is finely and evenly magnetized, and a capstan rotation speed detector 4 is placed close to the magnetized rotation unit, and a capstan rotation speed detector 4 generates a pulse proportional to the rotation speed of the capstan motor. A signal a (referred to as a CFG signal) is output by electromagnetic conversion. To designate the running speed of the capstan, a speed command is input from the input terminal 10. For example, for normal playback, a 1x speed command is input, and for slow playback, a 1/nx speed command is input. This speed command signal is input to the speed command signal generator 8, which outputs capstan target speed data (cycle data d of CFG signal a). Capstan speed control circuit 5
inputs the CFG signal a output from the capstan motor and converts the input CFG signal a into period time data. Next, the cycle data d of the CFG signal a output from the speed command signal generator 8 is input, and the difference cycle between the cycle data of the CFG signal a and the cycle data d of the CFG signal a is calculated. do. The differential period data is subjected to frequency-voltage conversion (f-v
After adding a gain, the capstan speed control signal m is output as a capstan speed control signal m.

Next, the capstan phase control operation will be explained. The reference signal output from the reference signal generation circuit 21 undergoes a phase shift of the amount of tracking change in the variable delay circuit 15, and is sent to the phase control circuit 35 as a capstan phase control reference signal e. On the other hand, during recording, control signals recorded in advance at equal intervals on the lower end of the magnetic tape in the longitudinal direction using a reference signal 21 are transferred to the control head 12 during reproduction.
The playback control signal is reproduced by the control signal reproducing device 13, sufficiently amplified by the control signal reproducing device 13, and further subjected to processing such as waveform shaping.
It is sent to the phase control circuit 35 as a signal f. The phase control circuit 35 calculates the phase difference between the reproduction control signal f and the capstan phase control reference signal e, and performs f-v conversion.
After adding phase compensation and gain, it is sent to the adder 6 as a phase control signal. The adder 6 adds the speed control signal m and the phase control signal o at an addition ratio G1, and controls the capstan motor with the addition control output.

Next, drive control of the drum motor will be explained. A pulse signal (DFG signal s) having a frequency proportional to the rotational speed of the drum motor 60 is generated by a DFG signal detector and sent to the drum speed control device 19. On the other hand, drum target period data t is sent from the speed command signal generator 8 to the drum speed controller 19. The drum speed control device 19 calculates the period of the DFG signal s, and calculates the difference between the DFG period data and the drum target period data t as f.
-v conversion and sent to the adder 18 as a drum speed control signal u.

Next, the phase difference calculation output between the output signal r from the rotation information detector 16 for detecting the rotational phase of the drum motor 60 and the output pulse x from the reference signal generator 21 is used as the drum phase control signal v. It is sent to adder 18. The adder 18 adds the speed control signal u and the phase control signal v at an addition ratio G2
The drum motor is controlled by the addition control output.

Next, the improvement in responsiveness of the capstan motor according to the present invention will be explained with reference to the same drawing. Magnetic recording and reproducing devices (referred to as VTRs) are capable of shortening the display time from a stopped state to normal playback, and high-speed search of editing points during editing.
In order to achieve this, the tape must have a high moving speed and acceleration, and a fast response to commands. Among these, the capstan response time, especially the capstan phase control response time, plays an important role. V
The frequency of the TR's capstan phase control reference signal is usually the video frame frequency, so the phase sampling frequency is as low as several tens of Hz, and it takes more than 1 s to complete the capstan phase acquisition. In some cases, Furthermore, since the phase control device 35 is provided with an integrating means such as a phase compensation circuit, the responsiveness is reduced.

FIG. 2 shows a waveform diagram of capstan phase control. In the capstan phase control device, the phase difference g between the falling edge of the capstan phase reference signal e and the reproduction control signal f is constantly calculated. For example, the time it takes for the phase difference g between the fall of the capstan phase reference signal e and the reproduction control signal f after speed lock-in to reach the target phase is longer at T2 than at T1, and further at T3 than at T2. becomes longer.

In this embodiment, phase control is partially supplemented with speed control to shorten the capstan phase pull-in time. The phase difference output from the phase control device 35 performs speed control by shifting the current target speed by several percent in accordance with, for example, phase difference threshold values set in stages. The threshold value determination is performed by the speed offset command device 36, and the speed offset data h is sent to the speed command signal generator which outputs the current target speed command to change the target speed.

To explain with reference to FIG. 2, at the start of phase control during normal playback, the final target speed is 1x speed, but the phase difference between the falling edge of the capstan phase reference signal e and the playback control signal f. g is the delayed phase and the threshold is T1
Since it is less than T2, it is converted into a speed command that is 5% higher than the final target speed. Also, since the phase difference g is a lagging phase and the threshold value is greater than or equal to T2 and less than T3, it is converted into a speed command that is 8% higher than the final target speed. Further, since the phase difference g is a delayed phase and the threshold value is T3 or more, it is converted into a speed command that is 10% higher than the final target speed. Although the phase difference g has been explained here for a lagging phase, similar means are used to control the final target speed command so as to lower it by several percent for an advanced phase. By doing this, the phase control rule
A speed control loop that does not use an integrating means such as a phase compensation circuit
can supplement the phase control correction operation. As a result, the response of phase control is improved, and it is possible to realize a faster image output time from stop to playback.

Next, a second embodiment will be explained using FIGS. 3 and 4. In FIG. 3, blocks similar to those in FIG. 1 are indicated by the same symbols. Further, the explanation of functions similar to those in FIG. 1 will be omitted here.

37 is a variable gain device, and 38 is an acceleration/deceleration determination circuit. In this embodiment, the gain of the capstan speed control system during the capstan phase control pull-in period is changed to increase the speed of phase control.

First, the manner in which the capstan phase control operation operates as a disturbance in speed control will be explained using FIG. 4. In FIG. 4, the horizontal axis shows time and the vertical axis shows the capstan rotation speed, and shows the rise of the capstan rotation speed from stop to normal playback.

V0 represents the target speed, W1 represents the target phase lock-in range, and W2 represents the target speed lock-in range. Here, the lock-in range refers to a state in which the capstan speed is stable within the above speed range.

Since the acceleration/deceleration control signals for capstan phase control and speed control act independently, for example, even though speed control is in an acceleration state, phase control is in a lead phase with respect to the target phase. When the vehicle is in a deceleration state, speed control and phase control are in contradictory control states. Therefore, in the phase control, the speed control becomes a disturbance signal, and the phase pull-in time becomes longer. Therefore, in the case of a control state where speed control and phase control conflict with each other as described above, the gain of either speed control or phase control is controlled to be changed.

A period in which waveform i is at Hi level indicates that the capstan speed is locked in. The phase control operation is started from this speed lock-in point i1. The phase control operation is stopped during a period in which the speed is not locked in (a period in which the waveform i is Low). Waveform j is a signal indicating phase lock-in, and becomes Hi level when entering the W1 range (phase lock-in). Waveform k is a signal indicating an acceleration/deceleration command for phase control, and has a low level period (DW1,
DW2) is deceleration control, and the Hi level period (UP1)
indicates the acceleration control period. The waveform v1 is a signal indicating an acceleration/deceleration command for speed control, and similarly to the waveform k, a low level period is a deceleration control, and a high level period is an acceleration control period. Here, as shown in the waveform k1, there is a period in which the acceleration/deceleration commands for phase control and speed control conflict with each other. GW of waveform k1
1 period and GW2 period correspond to that period. In this embodiment, the speed control gain is lowered only during the GW1 period and the GW2 period of the waveform k1.

The operation and signal flow will be explained using FIG. An acceleration/deceleration signal k1 is sent from the speed control device 5 to the acceleration/deceleration determination circuit 38, and an acceleration/deceleration signal k is also sent from the phase control device 35 to the acceleration/deceleration determination circuit 38. If the acceleration/deceleration states of the speed control and phase control do not match, the acceleration/deceleration determination circuit 38 sends a control signal k1 to the variable gain circuit 37 in order to lower the gain of the speed system. In this way, even if the acceleration/deceleration states of speed control and phase control are contradictory, disturbance of speed control to phase control can be reduced, and capstan phase pull-in can be performed at high speed.

[0031]The velocity system gain is returned to the normal velocity gain when the phase lock-in is completed. Further, this embodiment is made to operate only during the capstan phase pull-in process.

Next, a third embodiment of the means for increasing the speed of phase control pull-in will be described with reference to FIGS. 5, 6, and 7.

In FIG. 5, functional parts similar to those in FIG. 1 are designated by the same reference numerals. Further, the explanation of the same operation as in FIG. 1 will be omitted here. 39, 40 are switches, 41 is a phase difference detection circuit, 4
2 is a phase difference setting circuit, 43 is an AND circuit, 44 is a capstan phase unlock detection circuit, and 45 is an adjust (ADJ) circuit that sets the capstan phase control to an adjusting state (stops the phase control).

In this embodiment, the final target speed command is shifted by only several tens of percent only during the period from capstan activation to phase lock-in, and the capstan phase is rotated at high speed with respect to the target phase. The capstan phase control starts near the target phase, and when it is far from the target phase, it is controlled to the adjusted state.

The above operation will be explained with reference to FIG. The phase control device 5 controls the capstan phase reference signal e and the playback control.
The phase difference data g2 with respect to the signal f is sent to the phase difference detection circuit 41. On the other hand, the phase difference value setting circuit 42 sends a preset phase difference threshold value a2 to the phase difference detection circuit 41.
Send to. In the phase difference detection circuit 41, phase difference data g
2 and the phase difference threshold a2, and the phase difference data g2
If is larger, a Hi level signal e2 is sent to the AND circuit 43.

Next, in order to determine whether or not the capstan phase is locked in to the target phase, the phase control output signal f2 is input to the UNLOCK detection circuit 44, and a phase lock-in state (Hi level) determination signal is input. d2 is output to the AND circuit 43.

The speed command signal generator 8 sends a Hi level signal c2 to the AND circuit 43 when in the mode (speed) for performing capstan phase control.

The AND circuit 43 output signal b2 becomes Hi level only when capstan high-speed phase pull-in is performed.
The switch 39 is turned on and the switch 40 is turned off.

The switch 39 transmits a speed offset command of, for example, -20 percent to the current target speed from the speed offset circuit 36 to the speed command generator 8. When the switch 40 is OFF, the capstan phase control is adjusted, and when the switch 40 is ON, the phase control output is transmitted to the adder 6.

Next, the process from capstan activation to phase lock-in will be explained using the waveform diagram of FIG. 6. Waveform e
is a signal indicating the capstan reference phase. Waveform m1 shows a phase control waveform when performing high-speed phase pull-in. Since the normal phase control waveform is controlled so that the reproduction control signal coincides with the falling edge of waveform e, it produces a trapezoidal slope output as shown in waveform m2. In other areas, maximum acceleration (Hi level) or maximum deceleration (Low level) is output around the rising edge of waveform e.

Waveform m1 shows that when the capstan speed is locked in, if the speed is not within the range indicated by WL, the phase control output is adjusted and the phase control output is
FF. The speed control at this time is performed at 0.8 times the final target speed of 1 times. When the speed range indicated by WL is reached, the speed control is switched to 1x speed,
Turn on the phase control output.

FIG. 7 shows a flowchart of the operation of FIG. 5. When the capstan is activated 50, the state of speed lock-in 51 is first checked, and if speed lock-in is not achieved, the capstan phase control output 52 is adjusted. If it is locked in, check that the capstan phase is within the WL range of waveform m1 in 53, and
If it is outside the L range, the normal playback mode starts from 57 STOP.
Determine whether to migrate the code. This is because capstan high-speed phase pull-in control is performed only for normal playback from STOP.

When it is confirmed that the mode has changed from STOP to normal playback mode, the speed command signal d of 58 is set to 0.8 times the speed, and capstan driving is continued. Thereafter, when the capstan phase reaches within the WL range, the speed command signal d at 54 is returned to 1x speed, a phase control signal is output, and after confirming the capstan phase lock-in at 55, the process ends at EXIT at 56.

Next, another embodiment will be explained using FIGS. 8, 9, and 10.

In this figure, the same parts as in FIG. 1 are denoted by the same reference numerals. Further, in this figure, description of the same functions as in FIG. 1 will be omitted.

In FIG. 8, 7 is an integrator, 9 is a recording/reproduction switching signal input terminal, and 11 is a switch circuit. This embodiment relates to a capstan phase control device for a recording system. Although not shown in the figure, phase control of a recording system is generally performed by changing the capstan rotation frequency signal (CFG signal a) to n
The frequency is divided, and the phase difference between the CFG signal a and the reference signal output from the reference signal generator 21 is used as a control signal. However, in the above phase control, it is necessary that the frequency division value of the CFG signal a and the frequency of the reference signal must match. Complex control was required to maintain the continuity of the recording phase from the reproduction phase at the connection recording point. However, the above problem can be solved by using, for example, the integral value of the acceleration/deceleration signal for speed control as the capstan phase control during recording.

The signal b output from the speed control device 5 is a control signal b that outputs whether the rotational speed of the capstan is faster or slower than the target speed. The control signal b
is successively integrated with respect to the control center voltage by the integrator 7. The control center voltage here refers to the control voltage when the capstan rotates around the target speed without any disturbance. The integrator output signal c is sent to the adder 6 via the switch circuit 11.

Next, FIG. 9 shows a block diagram of an embodiment of the integrator 7 and the speed control device 5, and the capstan phase control operation of the recording system will be explained.

In FIG. 9, 22 is a period measuring circuit, 23
24 is a comparator, 25 and 31 are gain calculation devices, 26 is a frequency-voltage conversion device, 27 is a sign discrimination circuit, 28 is an integrator, 29 is a control center voltage generation circuit, and 30 is an adder. , 32 is an input terminal for CFG signal a, 33
34 is a speed command signal input terminal, and a capstan control signal output terminal.

CFG signal a input from input terminal 32
The period measurement circuit 22 performs period measurement. On the other hand, the speed command signal d input from the input terminal 33 is used to calculate target CFG cycle data in the target cycle calculation circuit 23. The comparator 24 sends a difference signal between the CFG cycle data and the target CFG cycle data corresponding to the speed command to the gain calculation circuit 25 and the code identification circuit 27. Gain calculation circuit 2
Reference numeral 5 changes the gain of the speed control signal in accordance with the speed command, and the output signal from the gain calculation circuit 25 is sent to the adder 6 by the frequency-voltage conversion device 26.

On the other hand, the code identification circuit 27 discriminates acceleration/deceleration of speed control, and outputs a Hi pulse signal b3 for acceleration control and a Low pulse signal for deceleration control, for example. The integrator 28 successively integrates the output signal b3 of the code identification circuit 27.

In the waveform diagram of FIG. 10, the period of the CFG signal a is larger than the target CFG period T0. Therefore, speed control works in the acceleration direction, and the output of the integrator 28 rises stepwise as shown by waveform c3. Here, the integral output c
3 is added to the output voltage d3 of the control center voltage generation circuit 29. The output of the adder 30 is sent to the gain calculation circuit 31
After adding a gain thereto, the frequency-voltage converter 61 sends the signal to the adder 6 . As described above, by integrating the acceleration/deceleration signal of the speed control system, the integrated signal can be used as the capstan phase control signal during recording.

[0053]

[Effects of the Invention] According to the present invention, during the period from the start to the completion of capstan phase control, a portion of the phase control output signal is corrected and controlled by the speed control signal, thereby shortening the capstan phase pull-in time. I can do that. As a result, it is possible to shorten the image output time from when the magnetic tape is stopped to normal playback, and to perform a high-speed search for editing points during editing.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing an embodiment of a tape travel control system according to the present invention.

FIG. 2 is a waveform diagram showing the operation of main parts in FIG. 1;

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a waveform diagram showing operational waveforms of main parts of FIG. 3;

FIG. 5 is a diagram showing another embodiment of the present invention.

FIG. 6 is a servo signal waveform diagram.

FIG. 7 is a flowchart showing the capstan high-speed phase pull-in process of FIG. 5;

FIG. 8 is a diagram showing another embodiment of the present invention.

FIG. 9 is a circuit diagram showing a specific example of the main parts of FIG. 8;

FIG. 10 is a waveform diagram showing the operation of the main parts of FIG. 8;

[Explanation of symbols]

1. magnetic tape, 3. capstan motor, 4. capstan rotation frequency detector, 5. capstan speed control device, 6. adder, 7. integral circuit, 8. speed command signal generator, 11. switch circuit, 12. control playhead, 13. control signal regenerator, 14. capstan phase control device, 15. variable delay device, 16. drum rotation phase detector, 17. drum rotation frequency detector, 19. drum speed controller, 20. drum phase control device, 21. reference signal generator, 22. period measuring device, 23. target period calculation circuit, 25. gain calculation device, 26. frequency-voltage converter, 27. code identification circuit, 28. integral circuit, 29. control center voltage generator, 36. Speed command offset device, 37. variable gain device, 38. acceleration/deceleration determination device, 41. phase difference detection device, 42. Phase difference value setting circuit, 43. and circuit, 44. Unlock detection circuit.

Claims (4)

[Claims] 1. Speed control signal generating means for controlling the rotation speed of a capstan that drives a recording medium to be constant; means for reproducing a control signal from the recording medium; and a means for generating a control signal from the reproduction control signal. A phase control signal generating means for controlling the obtained phase information to match the phase of a reference signal provided in advance, a phase control signal integrating means for integrating the control signal output from the phase control signal generating means, and the integrating means. In the capstan servo control device, the capstan servo control device has means for adding the phase control signal obtained by adding the phase control signal and the speed control signal to obtain a capstan control signal. A capstan servo control device comprising means for adding an offset to a target speed. 2. Speed control signal generating means for controlling the rotational speed of a capstan for driving a recording medium to be constant; means for reproducing a control signal from the recording medium; A phase control signal generating means for controlling the obtained phase information to match the phase of a reference signal provided in advance, a phase control signal integrating means for integrating the control signal output from the phase control signal generating means, and the integrating means. a capstan servo control device comprising: means for adding the phase control signal obtained by adding the phase control signal and the speed control signal to obtain a capstan control signal; , when the second acceleration/deceleration determining means detecting the acceleration/deceleration state of the phase control and the acceleration/deceleration states of the first acceleration/deceleration determining means and the second acceleration/deceleration determining means do not match, the speed control A capstan servo control device comprising: means for reducing the output gain of the capstan servo controller. 3. Speed control signal generating means for controlling the rotation speed of a capstan for driving a recording medium to be constant; means for reproducing a control signal from the recording medium; and a means for generating a control signal from the reproduction control signal. A phase control signal generating means for controlling the obtained phase information to match the phase of a reference signal provided in advance, a phase control signal integrating means for integrating the control signal output from the phase control signal generating means, and the integrating means. In the capstan servo control device, the capstan servo control device has means for adding the phase control signal and the speed control signal to obtain a capstan control signal, and the target speed at capstan startup is set to a speed slightly shifted from the final target speed. means for setting and starting the capstan; a first detection means for detecting that the capstan speed has reached the vicinity of the target speed; and a second detection means for detecting that the capstan phase has reached the vicinity of the target phase. means for starting a capstan phase calculation operation with the capstan phase control output in an OFF state by the first detection means; means for turning on the capstan phase control output by the second detection means; A capstanser characterized by having means for switching the target speed of the capstan to the final target speed by means of the detection means.
Bo control device. 4. Speed control signal generating means for controlling the rotational speed of a capstan for driving a recording medium to be constant; means for reproducing a control signal from the recording medium; A phase control signal generating means for controlling the obtained phase information to match the phase of a reference signal provided in advance, a phase control signal integrating means for integrating the control signal output from the phase control signal generating means, and the integrating means. A capstan servo control device comprising: means for adding the phase control signal obtained by adding the phase control signal and the speed control signal to obtain a capstan control signal; , comprising an integrating means for adding when the first acceleration/deceleration determining means is determining acceleration and subtracting when determining decelerating, and using the integral output as capstan phase control means during recording. Capstan servo control device.