JPH04269863A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area occupied by a memory cell, to enhance the integration density of a semiconductor integrated circuit device, to prevent the discontinuity defect or the short circuit of word lines for shunt use and to enhance the electric reliability of the device at the semiconductor integrated circuit device provided with a DRAM in which a series circuit by a MISFET for cell selection use and by a capacitor element for information storage use of stacked structure is used as the memory cell. CONSTITUTION:At a semiconductor integrated circuit device provided with said DRAM, the film thickness of a lower-layer electrode 8 at a capacitor element C for information storage use of stacked structure is made thick, and a difference-in-level relaxation layer 8 formed of the same conductive layer as the lower-layer electrode 8 at the capacity element C for information storage use of stacked structure is constituted around the connecting part of a word line 6 to a word line 17 for shunt use. In addition, a difference-in-level relaxation layer 10 is constituted.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, and particularly to DRAM (Dynamic Random
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device equipped with an access memory.

0002

[Prior Art] DRAMs with a large capacity of 1 [Mbit], 4 [Mbit] or more have a cell selection MOSFET.
A memory cell that stores 1 bit of information is configured by a series circuit of an ET and a stacked information storage capacitive element. This memory cell is connected to word lines extending in the column direction (X direction) and the row direction (Y direction) in the memory cell array (memory cell mat).
are arranged at each intersection with a data line extending in the direction).

MOSFET for cell selection of the memory cell
is formed on the main surface of the semiconductor substrate, and includes a channel forming region,
It mainly consists of a gate insulating film, a gate electrode, a source region, and a drain region. The gate electrode is integrally formed and electrically connected to the word line in the gate width direction. In other words, each of the gate electrode and word line is basically formed of the same gate material (wiring material), for example, a single layer of polycrystalline silicon film, or a polycrystalline silicon film and a refractory metal silicide layered on top of it. It is formed of a laminated film formed of films.

On the other hand, an information storage capacitor element of a stacked structure of a memory cell is constructed by sequentially stacking a lower layer electrode, a dielectric film, and an upper layer electrode. The lower electrode is formed of the gate material of the upper layer of the gate electrode of the cell selection MOSFET, and is formed of, for example, a polycrystalline silicon film. The lower electrode is
It is connected to one semiconductor region of the MOSFET for cell selection, and a potential serving as information is supplied from the data line. The upper layer electrode is formed of a gate material above the lower layer electrode, and is similarly formed of a polycrystalline silicon film. The upper layer electrode is configured as a common electrode for adjacent memory cells and is supplied with a fixed potential.

[0005] In this stacked structure information storage capacitor, the lower layer electrode is formed by overlapping the gate electrode of the cell selection MOSFET and the upper surface of each of the word lines extending adjacent thereto. A step corresponding to the film thickness of each line can be formed, and the area of the lower electrode can be increased in the height direction within the area occupied by the lower electrode. Also,
The upper layer electrode is configured along the upper surface and side surface of the lower layer electrode with a dielectric film interposed therebetween, and the information storage capacitive element configured in this way corresponds to the side surface of the lower layer electrode within the area occupied by the lower layer electrode. The area can be increased in the height direction. In other words, the stacked structure information storage capacitor element can increase the charge storage area and reduce the area occupied by the memory cell, so it has the feature that it can improve the degree of integration of the DRAM.

MOSFET for cell selection of the memory cell
A data line is connected to the other semiconductor region. The data line extends on the surface of an interlayer insulating film formed on the upper layer of the information storage capacitor element of the stacked structure of the memory cell, and is formed of a low resistance wiring material such as an aluminum alloy film.

A shunt word line extends over the data line with an interlayer insulating film interposed therebetween. The shunt word line extends in the same column direction as the word line, one end is connected to the X decoder circuit via a word driver circuit, and the other end is connected to the word line. The shunt word line has a lower resistance value than the word line, and is formed of, for example, an aluminum alloy film.

[0008] DRAM, which has a tendency to increase in capacity as described above,
The memory cell array is divided into a plurality of pieces, and the word line for each of the divided memory cell arrays is divided into a plurality of lines in the extending direction, and the divided word lines are used for one shunt. Connect to word line. In other words, in this type of DRAM, the resistance value of the word line can be substantially reduced by using the shunt word line, so that the memory cell selection speed can be increased, and the information read operation speed can be increased.

The shunt word line is provided with a connection region between each of the plurality of divided memory cell arrays, and is connected to each of the plurality of divided word lines in this connection region.

0010

SUMMARY OF THE INVENTION The present inventors have found that the following problems frequently occur in a DRAM constructed of memory cells having the above-mentioned stacked-structure information storage capacitor elements.

In the DRAM, one layer of gate material is used for the gate electrode or word line of the MOSFET for cell selection in the memory cell array, and two layers of gate material are used for the lower and upper electrodes of the stacked information storage capacitive element. A total of three layers of gate material are used. On the other hand, only one layer of gate material is used as the word line in the connection region of the shunt word line and the word line. For this reason, a step corresponding to the two layers of gate material described above is generated between the memory cell array and the connection region, and the step coverage of the wiring material at this step is reduced, so the shunt word line passing through the step is Frequent disconnection failures occur.

[0012] Furthermore, in the step of patterning shunt word lines in the DRAM manufacturing process, the photoresist film (etching mask) remains thicker on the steps than on other flat areas. Since the wiring material remains, short circuits between adjacent shunt word lines occur frequently.

[0013] In particular, in a stacked structure information storage capacitor, there is a limit to the amount of charge storage that can be obtained in a planar manner. This tends to increase the amount of charge storage that can be obtained three-dimensionally. In other words, the lower layer electrode of the stacked structure information storage capacitor element is the upper layer electrode, and the cell selection MOSFET.
The film thickness is set to be considerably thicker than the respective film thicknesses of the gate electrodes of the ET. For this reason, the step difference between the memory cell array and the connection region described above becomes even larger, and disconnections of shunt word lines or short circuits between adjacent shunt word lines occur frequently.

[0014] An object of the present invention is to provide a MISFET for cell selection.
In a semiconductor integrated circuit device equipped with a DRAM whose memory cell is a series circuit of a stacked information storage capacitor and a stacked information storage capacitor, it is possible to reduce the area occupied by the memory cell, improve the degree of integration, and reduce the disconnection of the shunt word line. The object of the present invention is to provide a technology that can prevent defects or short circuits and improve electrical reliability.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0016]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

(1) A stacked structure information storage capacitive element and cell selection MISFE having a lower layer electrode and an upper layer electrode laminated with a dielectric film interposed on each of its top and side surfaces.
The memory cell array is integrated with and electrically connected to the gate electrode of the cell selection MISFET of the memory cell on the side of the memory cell array in which a plurality of memory cells are arranged in a series circuit with T. A word line extending in a specific direction, a word line extending in the same direction as the word line, formed in a conductive layer above the word line, and having a smaller resistance value than the word line. In a semiconductor integrated circuit device including a DRAM, in which a connection region to which each of the shunt word lines is connected is arranged,
The lower layer electrode of the information storage capacitive element of the stacked structure of the memory cell of the DRAM is configured to have a thicker film thickness than the upper layer electrode, and around the connection portion between the shunt word line and the word line in the connection region, A step relief layer is formed of the same conductive layer as the lower electrode of the information storage capacitive element of the stacked structure of the memory cell.

(2) The step relief layer of the means (1) is formed by laminating a conductive layer that is the same as the lower electrode of the information storage capacitor element of the stacked structure of the memory cell of the DRAM, and a conductive layer that is the same as the upper electrode. configured.

[0019]

[Operation] According to the above-mentioned means (1), the area of the side surface of the lower electrode of the information storage capacitor of the stacked structure of the memory cell of the DRAM is increased, and the amount of charge storage of this information storage capacitor is increased. Therefore, the cell area of the memory cell can be reduced and the degree of integration of the DRAM can be improved. The level difference on the surface of the underlying insulating film of the shunt word line between the shunt and It is possible to prevent disconnection of word lines or short circuit between adjacent shunt word lines, thereby improving the electrical reliability of the DRAM.

According to the above-mentioned means (2), the thickness of the step relief layer is increased to increase the height of the surface of the base insulating film of the shunt word line of the memory cell array, and the surface of the base insulating film of the connection region. Since the heights of the memory cell array and the connection region can be made substantially equal to each other, the level difference in the surface of the underlying insulating film between the memory cell array and the connection region can be made even, thereby further improving the electrical reliability of the DRAM.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a DRAM composed of memory cells having stacked information storage capacitive elements.

In all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 (block circuit diagram of essential parts) shows the configuration of a DRAM which is an embodiment of the present invention.

As shown in FIG. 2, 1[b
The memory cell M that stores information of [it] is a cell selection MI.
SFETQn and stacked structure information storage capacitive element C
It consists of a series circuit with. A plurality of memory cells M are arranged at each intersection of a word line (WL) 6 and a complementary data line (DL) 14.

MISFE for cell selection of the memory cell M
The gate electrode of TQn is connected to the word line WL, one semiconductor region is connected to the complementary data line DL, and the other semiconductor region is connected to one electrode (lower layer electrode) of the stacked structure information storage capacitive element C. be done. The other electrode (upper layer electrode) of the stacked structure information storage capacitive element C has a fixed potential, for example, 1/2 Vcc fixed potential (for example, operating potential Vc
When c is 5 [V], it is connected to approximately 2.5 [V]).

A plurality of the memory cells M are arranged in a column direction (X direction) in which the word line WL extends and in a row direction (Y direction) in which the complementary data line DL extends, forming a memory cell array 20. do. The memory cell array 20 is divided into a plurality of parts at least in the column direction in which the word line WL extends, and for each divided memory cell array 20, the word line WL is divided into a plurality of lines in the column direction in which the word line WL extends.

Each word line WL divided into a plurality of lines in the column direction is connected to one shunt word line (WL
) 17, and is connected to the word driver circuit and the X decoder circuit 22 via this shunt word line WL, and is selected thereby. The shunt word line WL basically has a smaller resistance value than the word line WL, and can increase the selection speed of the memory cell M when reading information from the memory cell M.

The shunt word line WL and the divided word lines WL are electrically connected to each other in the connection region 21 between the memory cell arrays 20 divided in the column direction.

The complementary data line DL is connected to and selected by the Y decoder circuit 23.

Next, the specific cross-sectional structures of the memory cell M and the connection region 21 of the DRAM will be briefly explained using FIG. 1 (a cross-sectional view of a main part).

As shown in FIG. 1, a DRAM is mainly composed of a p-type semiconductor substrate 1 basically made of single crystal silicon. Memory cell array 20 of this p-type semiconductor substrate 1
A p-type well region 2 is formed in the main surface portion, such as the region where the n-channel MISFET of the peripheral circuit is formed. The peripheral circuit includes a word driver circuit, an X decoder circuit 22, a Y decoder circuit 23, a clock control system circuit (not shown), a buffer circuit, etc. Further, an n-type well region (not shown) is formed on the main surface of the p--type semiconductor substrate 1, such as a region where a p-channel MISFET is formed.

As shown on the left side of FIG. 1, the cell selection MISFET Qn of the memory cell M of the DRAM is located in a p-type well region in a region defined by an element isolation insulating film 3 and a p-type channel stopper region 4. 2 (actually, the main surface of p-type channel stopper region 4). In other words, the cell selection MISFET Qn includes a channel forming region (a region diffused toward the active region side of the p-type channel stopper region 4), a gate insulating film 5, a gate electrode 6, and a pair of n-type semiconductor regions 7 that are a source region and a drain region. It is mainly composed of.

The gate insulating film 5 is composed of, for example, a silicon oxide film formed by subjecting the main surface of the p-type well region 2 to an oxidation treatment.

The gate electrode 6 is formed in the step of forming the first layer of gate material in the DRAM manufacturing process, and is made of, for example, a polycrystalline silicon film. This polycrystalline silicon film is deposited by, for example, a CVD method, and an n-type impurity is introduced during or after the deposition to reduce the resistance value. The thickness of the gate electrode 6 should be made thick in order to increase the speed of information read operation, but in order to suppress the growth of steps on the surface of the underlying insulating film of the upper layer wiring, the thickness of the gate electrode 6 should be 200 to 400 [nm].
It is formed with a relatively thin film thickness of about 100 ml. The gate electrode 6 is
It is formed integrally with the word line (WL) 6 in the gate width direction and is electrically connected. That is, the word line 6 and the gate electrode 6 are formed of the same gate material and in the same manufacturing process. In addition, each of the gate electrode 6 and the word line 6 is formed of a multilayer film (gate material).

A pair of n-type semiconductor regions 7, which are a source region and a drain region, are formed by an ion implantation method in which n-type impurities are introduced using the gate electrode 6 as an impurity introduction mask. The n-type semiconductor region 7 is made of, for example, 1014 [at
oms/cm2] or less.

The information storage capacitive element C of the stacked structure of the memory cell M is constructed by sequentially stacking a lower layer electrode 8 as one electrode, a dielectric film 9, and an upper layer electrode 10 as the other electrode.

A part of the lower electrode 8 is connected to the MIS for cell selection.
The cell selection MISFETQ is connected between the gate electrode 6 of the FETQn and the word line 6 extending adjacent thereto.
n type semiconductor region 7 . Part of this lower electrode 8 and the n-type semiconductor region 7 of the cell selection MISFETQn
The connection is made through the n+ type semiconductor region 11 for connection. Further, the other portion (periphery) of the lower electrode 8 is superimposed on the upper surfaces of the gate electrode 6 and the word line 6, respectively. The lower electrode 8 is formed in the second layer gate material forming step in the manufacturing process, and is made of, for example, a polycrystalline silicon film. N-type impurities are similarly introduced into this polycrystalline silicon film, and this polycrystalline silicon film is also used as a solid-phase diffusion source for n-type impurities forming the n+ type semiconductor region 11 for connection. In addition, the polycrystalline silicon film has a thickness of, for example, 500 to 800[
It is formed with a thick film thickness of about 100 nm.

The dielectric film 9 covers the upper and side surfaces of the lower electrode 8. This dielectric film 9 is formed, for example, of a single layer of silicon oxide film or silicon nitride film, or a laminated film of these.

The upper layer electrode 10 is configured to cover the upper and side surfaces of the lower layer electrode 8 with the dielectric film 9 interposed therebetween. The upper layer electrode 10 is configured integrally with the upper layer electrode 10 of the information storage capacitive element C having a stacked structure of a plurality of memory cells M arranged in the memory cell array 20. The upper layer electrode 10 is formed in the third layer gate material forming step in the manufacturing process, and is made of, for example, a polycrystalline silicon film. Similarly, n-type impurities are introduced into this polycrystalline silicon film,
For the purpose of suppressing the growth of steps on the surface of the base insulating film of the upper wiring, it is formed with a relatively thin film thickness of, for example, about 200 to 300 [nm].

A complementary data line (DL) 14 is connected to one n-type semiconductor region 7 of the cell selection MISFET Qn of the memory cell M configured as described above. Complementary data line 14 extends on the surface of interlayer insulating film 12 and is connected to n-type semiconductor region 7 through connection hole 13 formed in interlayer insulating film 12 . The complementary data line 14 is formed in the first layer wiring formation step in the manufacturing process, and is made of, for example, an aluminum alloy film. The aluminum alloy film is an aluminum film to which at least one of Cu, which improves electromigration resistance, and Si, which improves alloy spike resistance, is added, for example.

Further, the complementary data line 14 may be formed of a laminated film in which a MoSi2 film, an aluminum alloy film, and a MoSi2 film are laminated in sequence. In this case, the underlying MoS
The i2 film is used as a barrier metal film to prevent mutual diffusion between Si particles and AL particles. Upper layer MoSi2
The film is used as an antihalation film (reducing the reflectance of the surface of the AL) when exposing the photoresist film to form an etching mask in the complementary data line 14 patterning step of the manufacturing process.

A shunt word line (WL) 17 extends above the complementary data line 14 . The shunt word line 17 extends on the interlayer insulating film 15 . This shunt word line 17 is formed in the second layer interconnection forming step in the manufacturing process, and is, for example, the complementary data line 14.
It is formed using the same wiring material.

A final protective film (final passivation film) 18 is formed on this shunt word line 17.

The shunt word line 17 is electrically connected to the word line 6 in the connection region 21, as shown on the right side of FIG. The word line 6 in the connection region 21 basically extends on the element isolation insulating film 3 for the purpose of preventing the generation of parasitic MOS. Each of the shunt word line 17 and the word line 6 is connected with an intermediate conductive layer 14 interposed therebetween in order to prevent the shunt word line 17 from being disconnected. The intermediate conductive layer 14 has one end connected to the shunt word line 17 through a connection hole 16 formed in the interlayer insulating film 15, and the other end connected to the word line 6 through the connection hole 13 formed in the interlayer insulating film 12. Ru. This intermediate conductive layer 14 is formed of the same conductive layer as the complementary data line 14 and is formed in the same manufacturing process. Also,
The connection holes 16 arranged at one end of the intermediate conductive layer 14 and the connection holes 13 arranged at the other end are not arranged at the same position in order to reduce disconnection of the shunt word line 17. , are arranged at mutually shifted positions.

In this connection region 21, around the connection portion between the shunt word line 17 and the word line 6, there is provided a dummy having a cross-sectional structure substantially the same as that of the memory cells M arranged in the memory cell array 20. A memory cell Md is arranged. This dummy memory cell Md is a dummy cell selection MISFETQ having at least a gate electrode 6.
d, and a dummy stacked information storage capacitive element Cd having at least a lower electrode 8. Basically, none of the elements of the dummy memory cell Md has the function of the memory cell M.

The gate electrode 6 of the dummy cell selection MISFET Qd, the lower layer electrode 8 and the upper layer electrode 10 of the dummy stacked structure information storage capacitor C are each used as the step relief layers 6, 8, and 10, respectively. Ru. Each of the step relief layers 6, 8, and 10 is connected to the memory cell array 20.
The surface heights of the interlayer insulating film 15, which is the base insulating film, of the shunt word line 17 extending inside the connection region 21 and the shunt word line 17 extending inside the connection region 21 can be made equal to or approximated. In other words, each of the step reduction layers 6, 8, and 10 can reduce the step difference that occurs on the surface of the interlayer insulating film 15 (or interlayer insulating film 12) between the memory cell array 20 and the connection region 21.

In particular, in the stacked structure information storage capacitive element C of the memory cell M, the lower layer electrode 8 is formed thicker in order to increase the amount of charge storage, and the lower layer electrode 8 is thicker than the above-mentioned step. Therefore, by arranging in the connection region 21 the step relief layer 8 formed of the same conductive layer as the lower electrode 8 which causes the step, the step can be significantly reduced.

In this way, the lower layer electrode 8 and the upper layer electrode 10 are laminated with the dielectric film 9 interposed on each of the upper and side surfaces thereof.
A cell selection MISFET Qn of the memory cell M is provided on the side of the memory cell array 20 in which a plurality of memory cells M constituted by a series circuit of a stacked information storage capacitive element C having a stacked structure and a cell selection MISFET Qn are arranged. a word line (WL) 6 that is integrated with and electrically connected to the gate electrode 6 and extends the memory cell array 20 in a specific direction; In a DRAM, a connection region 21 is formed in a conductive layer above the word line 6 and is connected to each shunt word line (WL) 17 having a smaller resistance value than the word line 6. , the above D
The lower layer electrode 8 of the information storage capacitive element C of the stacked structure of the memory cell M of the RAM is configured to have a thicker film thickness than the upper layer electrode 10, and the connection between the shunt word line 17 and the word line 6 in the connection region 21 is made A step relief layer 8 formed of the same conductive layer as the lower electrode 8 of the information storage capacitive element C of the stacked structure of the memory cell M is formed around the connection portion. With this configuration, it is possible to increase the area of the side surface of the lower layer electrode 8 of the information storage capacitive element C of the stacked structure of the memory cell M of the DRAM, and increase the amount of charge storage of the information storage capacitive element C. It is possible to reduce the cell area of M and improve the degree of integration of the DRAM, and also to reduce the problem caused by the increase in the film thickness of the lower layer electrode 8 of the information storage capacitor C of the stacked structure of the memory cell M.
A step relief layer whose film thickness is increased based on an increase in the film thickness of the lower electrode 8 is used to reduce the step difference on the surface of the base insulating film (interlayer insulating film 15) of the shunt word line 17 between the connection region 21 and the connection region 21. 8 and can be flattened, it is possible to prevent disconnection of the shunt word line 17 or short circuit between adjacent shunt word lines, thereby improving the electrical reliability of the DRAM.

[0049] Furthermore, the step relief layer is a stacked structure information storage capacitor C of the memory cell M of the DRAM.
The step relaxation layer 8 is the same conductive layer as the lower electrode 8, and the upper electrode 1
It is constructed by laminating step difference reducing layers 10 each of which is the same conductive layer as that of layer 0. With this configuration, the thickness of the step relief layer is increased, and the height of the surface of the base insulating film (15) of the shunt word line 17 of the memory cell array 20 and the height of the surface of the base insulating film of the connection region 21 are increased. DR.
The electrical reliability of AM can be further improved.

[0050] Furthermore, the step relief layer (8, 10, or 6) is formed in the same step as the step of forming the conductive layer (lower layer electrode 8, upper layer electrode 10, or gate electrode 6) forming the memory cell M in the manufacturing process. Since it can be formed by D
The number of steps in the RAM manufacturing process can be reduced.

[0051] As described above, the invention made by the present inventor is as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, it goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof.

For example, the present invention is applicable to SRAM (Statistical RAM).
c RAM).

The present invention also provides a microprocessor, etc.
It can be applied to semiconductor integrated circuit devices equipped with DRAM.

[0054]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device equipped with a DRAM whose memory cell is a series circuit of a cell selection MISFET and a stacked information storage capacitor element, the area occupied by the memory cell can be reduced and the degree of integration can be improved. , it is possible to prevent disconnection or short-circuiting of the shunt word line and improve electrical reliability.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part showing a specific cross-sectional structure of a memory cell and a connection region of a DRAM according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram of main parts showing the configuration of the DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 3... Element isolation insulating film, 5... Gate insulating film, 6... Gate electrode or word line or step relief layer, 7...
Semiconductor region, 8... Lower electrode or step relief layer, 9... Dielectric film, 10... Upper electrode or step relief layer, 12, 15... Interlayer insulating film, 14... Complementary data line or intermediate conductive layer, 17...
Shunt word line, DL...complementary data line, WL...word line or shunt word line, M...memory cell, Md
...dummy memory cell, Qn...MISFET for cell selection,
C...Stacked structure information storage capacitive element.

Claims (2)

[Claims] 1. A stacked structure information storage capacitive element and cell selection MISFET having a lower layer electrode and an upper layer electrode laminated with a dielectric film interposed on each of its top and side surfaces.
The memory cell array is integrated with and electrically connected to the gate electrode of the cell selection MISFET of the memory cell on the side of the memory cell array in which a plurality of memory cells are arranged in series circuits. A word line that extends in a specific direction, a shunt that extends in the same direction as the word line, is formed in a conductive layer above the word line, and has a resistance value smaller than that of the word line. In a semiconductor integrated circuit device including a DRAM, in which connection regions are arranged to which word lines for use are connected, the lower electrode of the information storage capacitive element of the stacked structure of the memory cell of the DRAM has a thicker film thickness than the upper electrode. A step relaxation layer formed of the same conductive layer as the lower electrode of the information storage capacitive element of the stacked structure of the memory cell is formed around the connection portion between the shunt word line and the word line in the connection region. A semiconductor integrated circuit device comprising: 2. The step relief layer is formed by laminating a conductive layer that is the same as the lower electrode of the information storage capacitor element of the stacked structure of the memory cell of the DRAM, and a conductive layer that is the same as the upper electrode. The semiconductor integrated circuit device according to claim 1.