JPH04269859A - Capacitor - Google Patents
CapacitorInfo
- Publication number
- JPH04269859A JPH04269859A JP3050691A JP3050691A JPH04269859A JP H04269859 A JPH04269859 A JP H04269859A JP 3050691 A JP3050691 A JP 3050691A JP 3050691 A JP3050691 A JP 3050691A JP H04269859 A JPH04269859 A JP H04269859A
- Authority
- JP
- Japan
- Prior art keywords
- film
- high dielectric
- laminated
- capacitor
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000002131 composite material Substances 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910007277 Si3 N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、高誘電体複合酸化物（
以下「高誘電体物」と略す）を利用したキャパシタに関
するものである。[Industrial Application Field] The present invention relates to a high dielectric composite oxide (
The present invention relates to a capacitor using a high dielectric material (hereinafter abbreviated as a "high dielectric material").
【０００２】0002
【従来の技術】高誘電体物を利用したキャパシタは、従
来の誘電体膜，例えばＳｉＯ２，Ｓｉ３Ｎ４，Ｔａ２Ｏ
５ に比べ非常に誘電率が高いため、小面積化が実現で
きる。2. Description of the Related Art Capacitors using high dielectric materials are manufactured using conventional dielectric films such as SiO2, Si3N4, Ta2O.
Since the dielectric constant is much higher than that of 5, it is possible to reduce the area.
【０００３】従来は、一のキャパシタ電極上に高誘電体
を堆積させ、７００℃以上で加熱し、高誘電体を結晶化
し、その上面にもう一方のキャパシタ電極を設けること
により、高い誘電率のキャパシタを得ていた。Conventionally, a high dielectric constant has been achieved by depositing a high dielectric material on one capacitor electrode, heating it at 700° C. or higher to crystallize the high dielectric material, and providing the other capacitor electrode on the top surface. I was getting a capacitor.
【０００４】0004
【発明が解決しようとする課題】高誘電体膜は、ＳｉＯ
２ 膜，Ｓｉ３Ｎ４ 膜に比べピンホールが多く、また
グレインサイズが大きいために粒界を通じてリーク電流
等が発生しやすい。また、高誘電体膜をアモルファス状
態にすることにより、リーク電流は減少するが、誘電率
は、前記高誘電体膜が結晶状態の場合に比べて、かなり
低下する。[Problem to be solved by the invention] The high dielectric constant film is made of SiO
2 film and Si3N4 film, there are more pinholes and the grain size is larger, so leakage current etc. are likely to occur through grain boundaries. Further, by making the high dielectric constant film in an amorphous state, leakage current is reduced, but the dielectric constant is considerably lower than when the high dielectric constant film is in a crystalline state.
【０００５】本発明は、以上の問題点に鑑みてなされた
もので、リーク電流を抑制し、高誘電率が得られる手段
を提供することを目的とする。The present invention was made in view of the above problems, and an object of the present invention is to provide a means for suppressing leakage current and obtaining a high dielectric constant.
【０００６】[0006]
【課題を解決するための手段】請求項１記載の本発明の
キャパシタは、キャパシタ電極間に、１層の高誘電体膜
と１層のシリコン窒化膜との積層構造を有することを特
徴とする。Means for Solving the Problems The capacitor of the present invention as set forth in claim 1 is characterized in that it has a laminated structure of one layer of high dielectric constant film and one layer of silicon nitride film between capacitor electrodes. .
【０００７】また、請求項２記載の本発明のキャパシタ
は、キャパシタ電極間に、２層のシリコン窒化膜と、該
シリコン窒化膜の間に設けられた１層の高誘電体膜との
積層構造を有することを特徴とする。Further, the capacitor of the present invention according to claim 2 has a laminated structure of two layers of silicon nitride films between the capacitor electrodes and one layer of high dielectric constant film provided between the silicon nitride films. It is characterized by having the following.
【０００８】[0008]
【作用】上記請求項１記載の本発明及び請求項２記載の
本発明を用いることにより、高誘電体のグレイン粒界及
び表面に窒化シリコン膜（以下「Ｓｉ３Ｎ４ 膜 」と
略す）が形成される。[Operation] By using the present invention as set forth in claim 1 and the present invention as set forth in claim 2, a silicon nitride film (hereinafter abbreviated as "Si3N4 film") is formed on the grain boundaries and surfaces of the high dielectric constant. .
【０００９】[0009]
【実施例】以下、実施例に基づいてＤＲＡＭメモリセル
に用いる本発明のキャパシタについて詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a capacitor of the present invention used in a DRAM memory cell will be explained in detail based on examples.
【００１０】図１は、請求項１記載の本発明の一実施例
の作成工程図を示す。図１に於いて、１はＬＯＣＯＳ酸
化膜，２はｎ＋ 拡散層，３はポリシリコン，４は基板
，５はゲート酸化膜を示す。FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention as defined in claim 1. In FIG. 1, 1 is a LOCOS oxide film, 2 is an n+ diffusion layer, 3 is polysilicon, 4 is a substrate, and 5 is a gate oxide film.
【００１１】以下、請求項１記載の本発明の製造工程を
説明する。The manufacturing process of the present invention according to claim 1 will be explained below.
【００１２】従来方法により、トランジスタを形成した
後（図１（ａ））、絶縁膜６をトランジスタ部に積層す
る（図１（ｂ））。After forming a transistor by a conventional method (FIG. 1(a)), an insulating film 6 is laminated on the transistor portion (FIG. 1(b)).
【００１３】次に、スパッタリングにより誘電体下部電
極７（Ｐｔ）を厚さ１０００〜２０００Å積層し（図１
（ｃ））、その後基板４を３００℃に加熱し、スパッタ
法により高誘電体膜８を厚さ１０００〜５０００Å積層
し、その上部に、基板４を７００℃に加熱し、ＬＰＣＶ
Ｄ法によりＳｉ３Ｎ４膜９を厚さ３０〜５０Å積層する
（図１（Ｄ））。高誘電体膜８として、ＢａＴｉＯ３
膜，ＳｒＴｉＯ２ 膜， ＰｂＴｉＯ３ 膜，ＰＺＴ膜
等を用いることができる。Next, a dielectric lower electrode 7 (Pt) is deposited to a thickness of 1000 to 2000 Å by sputtering (see FIG.
(c)) Then, the substrate 4 is heated to 300°C, a high dielectric constant film 8 is laminated to a thickness of 1000 to 5000 Å by sputtering, and on top of that, the substrate 4 is heated to 700°C, and the LPCV
A Si3N4 film 9 is deposited to a thickness of 30 to 50 Å by method D (FIG. 1(D)). As the high dielectric film 8, BaTiO3
A film, SrTiO2 film, PbTiO3 film, PZT film, etc. can be used.
【００１４】Ｓｉ３ Ｎ４ 膜９形成と同時に高誘電体
膜８が結晶化され、結晶化により誘電率が向上する。そ
の後、上部電極１０（Ｐｔ）をスパッタリングにより厚
さ１０００〜２０００Å積層後（図１（ｅ））、フォト
リソグラフィ工程によりキャパシタを形成し、絶縁膜１
２を堆積しコンタクト孔を形成した後、配線１１を形成
する（図１（ｆ））。電極７，１０として白金（Ｐｔ）
を用いるのは、非常に酸化されにくい金属のためである
。[0014] Simultaneously with the formation of the Si3N4 film 9, the high dielectric constant film 8 is crystallized, and the dielectric constant is improved by crystallization. Thereafter, after laminating the upper electrode 10 (Pt) to a thickness of 1000 to 2000 Å by sputtering (FIG. 1(e)), a capacitor is formed by a photolithography process, and the insulating film 1
After depositing 2 and forming a contact hole, a wiring 11 is formed (FIG. 1(f)). Platinum (Pt) as electrodes 7 and 10
is used because it is a metal that is very difficult to oxidize.
【００１５】図２は、請求項２記載の本発明の構成断面
図を示す。FIG. 2 shows a cross-sectional view of the structure of the present invention according to claim 2.
【００１６】次に請求項２記載の本発明の製造工程を説
明する。請求項１記載の本発明の製造工程における、下
部電極７を厚さ１０００〜２０００Å積層し（図１（ｃ
））、ＬＰＣＶＤ法によりＳｉ３ Ｎ４ 膜９を厚さ３
０〜５０Å積層した後、基板４を３００℃に加熱し、ス
パッタ法により高誘電体膜８を厚さ１０００〜５０００
Å積層し、基板４を７００℃に加熱した後ＬＰＣＶＤ法
によりＳｉ３ Ｎ４ 膜９を厚さ３０〜５０Å積層する
。その後、上部電極１０（Ｐｔ）をスパッタリングによ
り厚さ１０００〜２０００Å積層後、フォトリソグラフ
ィ工程によりキャパシタを形成し、絶縁膜１２を積層し
、コンタクト孔を形成した後、配線１１を形成する。Next, the manufacturing process of the present invention according to claim 2 will be explained. In the manufacturing process of the present invention according to claim 1, the lower electrode 7 is laminated to a thickness of 1000 to 2000 Å (FIG. 1(c)
)), the Si3 N4 film 9 is grown to a thickness of 3 by the LPCVD method.
After laminating layers of 0 to 50 Å, the substrate 4 is heated to 300° C., and a high dielectric constant film 8 is formed to a thickness of 1000 to 5000 Å by sputtering.
After heating the substrate 4 to 700 DEG C., a Si3 N4 film 9 is deposited to a thickness of 30 to 50 .ANG. by LPCVD. After that, an upper electrode 10 (Pt) is deposited to a thickness of 1000 to 2000 Å by sputtering, a capacitor is formed by a photolithography process, an insulating film 12 is deposited, a contact hole is formed, and then a wiring 11 is formed.
【００１７】以上、実施例では高誘電体膜８の形成にス
パッタ法を用いたが、ＣＶＤ法を用いても実施可能であ
る。Although the sputtering method was used to form the high dielectric constant film 8 in the embodiments described above, it is also possible to use the CVD method.
【００１８】[0018]
【発明の効果】以上、詳細に説明した様に、請求項１記
載の本発明及び請求項２記載の本発明を用いることによ
り、それぞれ高誘電率を得ることができ、且つリーク電
流を迎えることができる。[Effects of the Invention] As explained in detail above, by using the present invention according to claim 1 and the present invention according to claim 2, a high dielectric constant can be obtained, and leakage current will not occur. Can be done.
【００１９】また、請求項１記載の本発明は、高誘電率
を得ることができる点で請求項２記載の本発明より優れ
ているが、リーク電流を迎えることができる点では、請
求項２記載の本発明の方が優れている。[0019]Also, the present invention according to claim 1 is superior to the present invention according to claim 2 in that a high dielectric constant can be obtained, but the present invention according to claim 2 is superior in that a leakage current can be generated. The described invention is superior.
【図１】請求項１記載の本発明の一実施例の作成工程図
である。FIG. 1 is a production process diagram of an embodiment of the present invention as set forth in claim 1.
【図２】請求項２記載の本発明の一実施例の構成断面図
である。FIG. 2 is a cross-sectional view of the configuration of an embodiment of the present invention according to claim 2.
１ ＬＯＣＯＳ酸化膜 ２ ｎ＋ 拡散層 ３ ポリシリコン ４ 基板 ５ ゲート酸化膜 ６ 絶縁膜 ７ 下部電極（Ｐｔ） ８ 高誘電体複合酸化物膜 ９ Ｓｉ３ Ｎ４ 膜 １０ 上部電極（Ｐｔ） １１ 配線 １２ 絶縁膜 1 LOCOS oxide film 2 n+ diffusion layer 3 Polysilicon 4 Board 5 Gate oxide film 6 Insulating film 7 Lower electrode (Pt) 8 High dielectric composite oxide film 9 Si3 N4 film 10 Upper electrode (Pt) 11 Wiring 12 Insulating film
Claims (2)
複合酸化物膜と１層のシリコン窒化膜との積層構造を有
することを特徴とするキャパシタ。1. A capacitor having a laminated structure of one layer of high dielectric composite oxide film and one layer of silicon nitride film between capacitor electrodes.
窒化膜と該シリコン窒化膜の間に設けられた１層の高誘
電体複合酸化物膜との積層構造を有することを特徴とす
るキャパシタ。2. A capacitor characterized by having a laminated structure of two layers of silicon nitride films and one layer of high dielectric composite oxide film provided between the silicon nitride films between capacitor electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3050691A JPH04269859A (en) | 1991-02-26 | 1991-02-26 | Capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3050691A JPH04269859A (en) | 1991-02-26 | 1991-02-26 | Capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04269859A true JPH04269859A (en) | 1992-09-25 |
Family
ID=12305706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3050691A Pending JPH04269859A (en) | 1991-02-26 | 1991-02-26 | Capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04269859A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6284580B1 (en) | 2000-02-23 | 2001-09-04 | Oki Electric Industry Co., Ltd. | Method for manufacturing a MOS transistor having multi-layered gate oxide |
-
1991
- 1991-02-26 JP JP3050691A patent/JPH04269859A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6284580B1 (en) | 2000-02-23 | 2001-09-04 | Oki Electric Industry Co., Ltd. | Method for manufacturing a MOS transistor having multi-layered gate oxide |
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