JP2972238B2 - Semiconductor storage element - Google Patents
Semiconductor storage elementInfo
- Publication number
- JP2972238B2 JP2972238B2 JP1249857A JP24985789A JP2972238B2 JP 2972238 B2 JP2972238 B2 JP 2972238B2 JP 1249857 A JP1249857 A JP 1249857A JP 24985789 A JP24985789 A JP 24985789A JP 2972238 B2 JP2972238 B2 JP 2972238B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- electrode
- platinum
- film
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は容量素子の構造に関するものである。Description: TECHNICAL FIELD The present invention relates to a structure of a capacitor.
半導体メモリセルの溝積層容量素子として、第２図に
示すようにシリコン基板１の溝1aに熱酸化膜12等の非晶
質絶縁膜を形成しその上に不純物を含んだ低抵抗ポリシ
リコン13を下部電極として形成し、該ポリシリコン表面
上に絶縁膜４を形成しさらに上部電極５を形成した素子
が、広い範囲で使用されている。下部電極ポリシリコン
13の低抵抗化にはリンの熱拡散技術が広く用いられる。
しかし、厚いポリシリコンを低抵抗化するための熱処理
温度や時間はデバイス全体のプロセス適合性において問
題となる。As shown in FIG. 2, an amorphous insulating film such as a thermal oxide film 12 is formed in a groove 1a of a silicon substrate 1 and a low-resistance polysilicon 13 containing impurities is formed thereon as a groove stacked capacitive element of a semiconductor memory cell. Are used as a lower electrode, an insulating film 4 is formed on the surface of the polysilicon, and an upper electrode 5 is further formed. Lower electrode polysilicon
The thermal diffusion technology of phosphorus is widely used to reduce the resistance of 13.
However, the heat treatment temperature and time for lowering the resistance of thick polysilicon poses a problem in the process suitability of the entire device.
そこで、シンポジウム オン ブイエルエスアイ テ
クノロジー：ダイジェスト オブ テクニカル ペーパ
ー（SYMPOSIUM ON VLSI TECHNOLOGY:DIGEST OF TECHNIC
AL PAPERS）1989年23〜25頁にリライアビリティ オブ
SiO2/Si3N4 ダイエレクトリックフィルム オン Mo
Si2 アンドWSi2（Reliability of SiO2/Si3N4 Films o
n MoSi2 and WSi2）と題して発表された論文において示
されているように、下部電極にタングステンシリサイド
（WSi2），モリブデンシリサイド（MoSi2）を用い、熱
処理を緩和した容量部構造が報告された。Therefore, Symposium on VLSI Technology: Digest of Technical Paper (SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNIC
AL PAPERS) Reliability of 1989 on pages 23-25
SiO 2 / Si 3 N 4 die electric film on Mo
Si 2 and WSi 2 (Reliability of SiO 2 / Si 3 N 4 Films o
n MoSi 2 and WSi 2 ), as shown in the paper published, reported that the lower electrode was made of tungsten silicide (WSi 2 ) and molybdenum silicide (MoSi 2 ), and the capacitor structure was relaxed by heat treatment. Was done.
しかしながら、セミコンダクターワールド1989年８月
号60〜64頁で報告されたようにシリサイド上には自然酸
化膜が形成され、このような自然酸化膜が形成される
と、誘電率の低い層ができてしまうことになり問題とな
る。However, as reported in Semiconductor World, August 1989, pp. 60-64, a native oxide film is formed on silicide, and when such a native oxide film is formed, a layer having a low dielectric constant is formed. It becomes a problem.
50Å（酸化膜の誘電率換算）以下の薄い容量絶縁膜形
成時にこの自然酸化膜が10Å存在すると、膜厚全体の20
％の部分が膜質の悪い自然酸化膜が占めることになる。If a natural oxide film is present at a thickness of less than 50 mm (equivalent to the dielectric constant of an oxide film), the total thickness of the film will be 20 mm.
% Is occupied by a natural oxide film having poor film quality.
本発明の目的は従来の問題点を除去し、信頼性の高い
薄い絶縁膜を有する容量素子を形成する構造を提供する
ことにある。An object of the present invention is to eliminate the conventional problems and to provide a structure for forming a capacitive element having a highly reliable thin insulating film.
前記目的を達成するため、本発明に係る半導体記憶素
子は、シリコン基板上に形成した下部電極及び容量絶縁
膜並びに上部電極からなる半導体素子のキャパシタ部に
おいて、前記下部電極は、プラチナ電極であり、該プラ
チナ電極は、トランジスタ電極との接続部のシリコンと
反応してシリサイド化する部分と絶縁膜上に堆積される
ことでプラチナとして安定に存在する部分とからなるも
のである。In order to achieve the above object, a semiconductor memory device according to the present invention has a lower electrode and a capacitor insulating film formed on a silicon substrate and a capacitor portion of a semiconductor device including an upper electrode, wherein the lower electrode is a platinum electrode, The platinum electrode is composed of a portion that reacts with silicon at a connection portion with the transistor electrode to be silicided and a portion that is stably deposited as platinum by being deposited on the insulating film.
積層容量絶縁膜において下部電極にシリサイドを用い
ると、この電極上に自然酸化膜が形成されてしまい、誘
電率の低い部分が形成されることになる。50Å（酸化膜
の誘電率換算）以下の薄い容量絶縁膜形成時にこの自然
酸化膜が10Å存在すると膜厚全体の20％の部分が膜質の
悪い自然酸化膜が占めることになる。このため容量絶縁
膜の信頼性に対して悪影響を及ぼす。If silicide is used for the lower electrode in the laminated capacitor insulating film, a natural oxide film will be formed on this electrode, and a portion having a low dielectric constant will be formed. If a natural oxide film is present at a thickness of 10 ° at the time of forming a thin capacitive insulating film having a thickness of 50 ° (converted to the dielectric constant of an oxide film) or less, 20% of the entire film thickness is occupied by a poor quality natural oxide film. This has an adverse effect on the reliability of the capacitance insulating film.
本発明では、酸化されにくいプラチナを下部電極とし
て形成しているため、自然酸化膜はほとんど成長しな
い。このため、従来のシリサイド電極上に形成した絶縁
膜に比べ、より信頼性の高い均一な絶縁膜が形成でき
る。このとき下部電極として形成したプラチナ電極とト
ランジスタの接続部（以下容量コンタクト部と呼ぶ）は
プラチナシリサイドになるのでオーミックなコンタクト
が形成できる。In the present invention, since platinum, which is hardly oxidized, is formed as the lower electrode, a natural oxide film hardly grows. Therefore, a more reliable and uniform insulating film can be formed as compared with the conventional insulating film formed on the silicide electrode. At this time, the connection between the platinum electrode formed as the lower electrode and the transistor (hereinafter referred to as a capacitance contact) becomes platinum silicide, so that an ohmic contact can be formed.
以下、本発明の実施例について図面を用いて説明す
る。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す断面図であ
る。図において、本発明はシリコン基板１の溝1aの内壁
に沿って形成した絶縁膜２と絶縁膜２上に形成した下部
電極としてのプラチナ膜３と、プラチナ膜３上に形成し
た容量絶縁膜４と上部電極５とを有するものである。FIG. 1A is a sectional view showing an embodiment of the present invention. Referring to FIG. 1, the present invention relates to an insulating film 2 formed along an inner wall of a groove 1a of a silicon substrate 1, a platinum film 3 as a lower electrode formed on the insulating film 2, and a capacitive insulating film 4 formed on the platinum film 3. And an upper electrode 5.
次に本発明に係る半導体記憶素子の製造方法を第１図
（ｂ），（ｃ），（ｄ）を用いて説明する。Next, a method for manufacturing a semiconductor memory element according to the present invention will be described with reference to FIGS. 1 (b), 1 (c) and 1 (d).
まず第１図（ｂ）に示すように、シリコン基板１に溝
1aを形成し、溝1aの内壁に沿って熱酸化膜等の絶縁膜２
を形成する。First, as shown in FIG.
1a is formed, and an insulating film 2 such as a thermal oxide film is formed along the inner wall of the groove 1a.
To form
次に第１図（ｃ）に示すように絶縁膜２上に、下部電
極としてのプラチナ膜３を成長形成させる。このとき下
部電極として形成したプラチナ電極とトランジスタソー
ス電極の接続部（以下、容量コンタクト部という）はプ
ラチナシリサイドとなりオーミックなコンタクトが得ら
れる。Next, as shown in FIG. 1C, a platinum film 3 as a lower electrode is grown on the insulating film 2. At this time, the connection between the platinum electrode formed as the lower electrode and the transistor source electrode (hereinafter referred to as a capacitance contact) becomes platinum silicide, and an ohmic contact is obtained.
次に第１図（ｄ）に示すように、前記プラチナ膜３上
に容量絶縁膜４としてチタン酸ストロンチウム（SrTi
O3）またはチタン酸バリウム（BaTiO3）などの絶縁膜を
形成する。本実施例ではSrTiO3またはBaTiO3を用いた
が、本特許においては容量絶縁膜としての材料は特に限
定されることはない。また、該容量絶縁膜４は一層でも
多層でもよい。Next, as shown in FIG. 1 (d), strontium titanate (SrTi) is formed on the platinum film 3 as a capacitive insulating film 4.
An insulating film such as O 3 ) or barium titanate (BaTiO 3 ) is formed. In this example, SrTiO 3 or BaTiO 3 was used, but the material of the capacitive insulating film is not particularly limited in the present patent. Further, the capacitance insulating film 4 may be a single layer or a multilayer.
最終に第１図（ａ）に示すように、前記容量絶縁膜４
上にCVD法によりポリシリコン膜を成長して不純物を拡
散し上部電極５を形成し、本発明に係る半導体記憶素子
を完成させる。上部電極５の材料として金属材料を用い
ることもできる。Finally, as shown in FIG.
A polysilicon film is grown thereon by the CVD method to diffuse impurities, thereby forming the upper electrode 5, thereby completing the semiconductor memory device according to the present invention. A metal material can be used as the material of the upper electrode 5.
本発明では、酸化されにくいプラチナを下部電極とし
て形成しているため、自然酸化膜は殆ど成長しない。こ
のため、従来のシリサイド電極上に形成した絶縁膜に比
べより信頼性の高い均一な絶縁膜が形成できる。また、
容量コンタクト部はプラチナシリサイドになるので、オ
ーミックなコンタクトが形成できる。In the present invention, since platinum, which is hardly oxidized, is formed as the lower electrode, a natural oxide film hardly grows. For this reason, a more reliable uniform insulating film can be formed as compared with the conventional insulating film formed on the silicide electrode. Also,
Since the capacitor contact portion is made of platinum silicide, an ohmic contact can be formed.
以上述べたように本発明によれば、信頼性の高い均一
な薄い絶縁膜を有する容量素子を容易に形成することが
できる。As described above, according to the present invention, a capacitive element having a highly reliable uniform thin insulating film can be easily formed.
第１図（ａ）は本発明の一実施例を示す断面図、第１図
（ｂ），（ｃ），（ｄ）は本発明の一実施例の製造方法
を工程順に示す断面図、第２図は従来例を示す断面図で
ある。 １……シリコン基板、２……絶縁膜 ３……プラチナ膜、４……容量絶縁膜 ５……上層電極、12……酸化シリコン膜 13……ポリシリコン膜1A is a sectional view showing an embodiment of the present invention, and FIGS. 1B, 1C, and 1D are sectional views showing a manufacturing method of the embodiment of the present invention in the order of steps. FIG. 2 is a sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Insulating film 3 ... Platinum film, 4 ... Capacitive insulating film 5 ... Upper electrode, 12 ... Silicon oxide film 13 ... Polysilicon film
Claims (1)
量絶縁膜並びに上部電極からなる半導体素子のキャパシ
タ部において、 前記下部電極は、プラチナ電極であり、 該プラチナ電極は、トランジスタ電極との接続部のシリ
コンと反応してシリサイド化する部分と絶縁膜上に堆積
されることでプラチナとして安定に存在する部分とから
なることを特徴とする半導体記憶素子。1. A capacitor portion of a semiconductor device comprising a lower electrode, a capacitor insulating film, and an upper electrode formed on a silicon substrate, wherein the lower electrode is a platinum electrode, and the platinum electrode is a connection portion with a transistor electrode. A semiconductor storage element comprising: a portion which reacts with silicon to form silicide and a portion which is deposited on an insulating film and stably exists as platinum.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249857A JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249857A JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03110862A JPH03110862A (en) | 1991-05-10 |
| JP2972238B2 true JP2972238B2 (en) | 1999-11-08 |
Family
ID=17199221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1249857A Expired - Lifetime JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2972238B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3118785B2 (en) * | 1991-05-23 | 2000-12-18 | ソニー株式会社 | Method of forming barrier metal structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4423087A (en) * | 1981-12-28 | 1983-12-27 | International Business Machines Corporation | Thin film capacitor with a dual bottom electrode structure |
| JPH0354828A (en) * | 1989-07-24 | 1991-03-08 | Oki Electric Ind Co Ltd | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
-
1989
- 1989-09-26 JP JP1249857A patent/JP2972238B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03110862A (en) | 1991-05-10 |
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