JPH03110862A - Semiconductor storage element - Google Patents
Semiconductor storage elementInfo
- Publication number
- JPH03110862A JPH03110862A JP1249857A JP24985789A JPH03110862A JP H03110862 A JPH03110862 A JP H03110862A JP 1249857 A JP1249857 A JP 1249857A JP 24985789 A JP24985789 A JP 24985789A JP H03110862 A JPH03110862 A JP H03110862A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- platinum
- film
- electrode
- capacitive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021339 platinum silicide Inorganic materials 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000002269 spontaneous effect Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 description 2
- 101001052394 Homo sapiens [F-actin]-monooxygenase MICAL1 Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 102100024306 [F-actin]-monooxygenase MICAL1 Human genes 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野］ 本発明は容量素子の構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a capacitive element.
［従来の技術］
半導体メモリセルの溝積層容量素子として、第２図に示
すようにシリコン基板ｌの溝１ａに熱酸化膜１２等の非
晶質絶縁膜を形成しその上に不純物を含んだ低抵抗ポリ
シリコン１３を下地電極として形成し、該ポリシリコン
表面上に絶縁膜４を形成しさらに上部電極５を形成した
素子が、広い範囲で使用されている。下部電極ポリシリ
コン１３の低抵抗化にはリンの熱拡散技術が広く用いら
れる。しかし、厚いポリシリコンを低抵抗化するための
熱処理温度や時間はデバイス全体のプロセス適合性にお
いて問題となる。[Prior Art] As shown in FIG. 2, an amorphous insulating film such as a thermal oxide film 12 is formed in a trench 1a of a silicon substrate 1, and an impurity is contained thereon, as a groove laminated capacitor element of a semiconductor memory cell. Elements in which a low-resistance polysilicon 13 is formed as a base electrode, an insulating film 4 is formed on the surface of the polysilicon, and an upper electrode 5 is further formed are widely used. Phosphorus thermal diffusion technology is widely used to reduce the resistance of the lower electrode polysilicon 13. However, the heat treatment temperature and time required to lower the resistance of thick polysilicon pose problems in the process compatibility of the entire device.
そこで、シンポジウム オン ブイエルニスアイ テク
ノロジー：ダイジェスト オブ テクニカル ペーパー
（ＳＹＭＰＯ３ＩＵＭ ＯＮ ＶＬＳＩ ＴＥＣＨＮＯ
ＬＯＧＹ：ＤＩＧＥＳＴ ＯＦ ＴＥＣＩ（ＮＩＣＡＬ
ＰＡＰＥＲ３）１９８９年２３〜２５頁にポリシリコ
ン／Ｓｉ帆インターフェイス マイクロテキスチャー
アンド ダイエレクトリック ブレークダウン（Ｐｏｌ
ｙｓｉｌｉｃｏｎ／ＳｉＯ，Ｉｎｔｅｒｆａｃｅ Ｍｉ
ｃｒｏｔｅｘｔｕｒｅ ａｎｄ Ｄｉｅｌｅｃｔｒｉｃ
Ｂｒｅａｋｄｏｗｎ）と題して発表された論文におい
て示されているように、下地電極にタングステンシリサ
イド（ＷＳｉ、）、モリブデンシリサイド（ＭＯＳ ｌ
ｍ ）を用い、熱処理を緩和した容量部構造が報告さ
れた。Therefore, the Symposium on VLSI TECHNO: Digest of Technical Papers (SYMPO3IUM ON VLSI TECHNO)
LOGY:DIGEST OF TECI(NICAL
PAPER 3) 1989, pp. 23-25 Polysilicon/Si sail interface microtexture
and dielectric breakdown (Pol
ysilicon/SiO, Interface Mi
crotexture and dielectric
As shown in a paper titled ``Breakdown'', tungsten silicide (WSi) and molybdenum silicide (MOS l) are used as the base electrode.
A capacitor structure with relaxed heat treatment was reported.
〔発明が解決しようとする課題）
しかしながら、セミコンダクターワールド１９８９年８
月号６０〜６４頁で報告されたようにシリサイド上には
自然酸化膜が形成され、このような自然酸化膜が形成さ
れると、誘電率の低い層ができてしまうことになり問題
となる。[Problem to be solved by the invention] However, Semiconductor World 1989 8
As reported on pages 60-64 of the issue, a natural oxide film is formed on silicide, and when such a natural oxide film is formed, a layer with a low dielectric constant is formed, which poses a problem. .
５０人（酸化膜の誘電率換算）以下の薄い容量絶縁膜形
成時にこの自然酸化膜が１０人存在すると、膜厚全体の
２０％の部分が膜質の悪い自然酸化膜が占めることにな
る。If 10 of these natural oxide films exist when forming a thin capacitive insulating film of 50 or less (converted to the dielectric constant of the oxide film), 20% of the entire film thickness will be occupied by the poor quality natural oxide film.
本発明の目的は従来の問題点を除去し、信頼性の高い薄
い絶縁膜を有する容量素子を形成する構造を提供するこ
とにある。An object of the present invention is to eliminate the conventional problems and provide a structure for forming a capacitive element having a highly reliable thin insulating film.
［課題を解決するための手段］
に１記目的を達成するため、本発明に係る半導体記憶素
子は、シリコン基板上に形成した下部電極゛及び容量絶
縁膜並びに北部電極からなる半導体記憶素子において、
前記下部電極にプラチナ電極を用いたものである。[Means for Solving the Problems] In order to achieve the object set forth in item 1, a semiconductor memory element according to the present invention includes a lower electrode formed on a silicon substrate, a capacitive insulating film, and a north electrode.
A platinum electrode is used for the lower electrode.
［作用］
積層容量絶縁膜において下地電極にシリサイドを用いる
と、この電極上に自然酸化膜が形成されてしまい、誘電
率の低い部分が形成されることになる。５０人（酸化膜
の誘電率換算）以下の薄い容量絶縁膜形成時にこの自然
酸化膜が１０人存在すると膜厚全体の２０％の部分が膜
質の悪い自然酸化膜が占めることになる。このため容量
絶縁膜の信頼性に対して悪影響を及ぼす。[Operation] If silicide is used for the base electrode in a laminated capacitive insulating film, a natural oxide film will be formed on this electrode, resulting in the formation of a portion with a low dielectric constant. If 10 of these natural oxide films are present when forming a thin capacitive insulating film of 50 or less (converted to the dielectric constant of the oxide film), 20% of the entire film thickness will be occupied by the poor quality natural oxide film. This adversely affects the reliability of the capacitor insulating film.
本発明では、酸化されにくいプラチナを下地電極として
形成しているため、自然酸化膜はほとんど成長しない。In the present invention, since platinum, which is difficult to oxidize, is formed as the base electrode, almost no natural oxide film grows.
このため、従来のシリサイド電極上に形成した絶縁膜に
比べ、より信頼性の高い均一な絶縁膜が形成できる。こ
のとき容量ポリシリコンとトランジスタの接続部（以下
容量コンタクト部と呼ぶ）はプラチナシリサイドになる
のでオーミッタなコンタクトが形成できる。Therefore, a more reliable and uniform insulating film can be formed compared to a conventional insulating film formed on a silicide electrode. At this time, since the connecting portion between the capacitive polysilicon and the transistor (hereinafter referred to as a capacitive contact portion) is made of platinum silicide, an ohmitter contact can be formed.
〔実施例］ 以下、本発明の実施例について図面を用いて説明する。〔Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す断面図である。FIG. 1(a) is a sectional view showing one embodiment of the present invention.
図において、本発明はシリコン基板ｌの溝１ａの内壁に
沿って形成した絶縁膜２と絶縁膜２上に形成した下部電
極としてのプラチナ膜３と、プラチナ膜３上に形成した
容量絶縁膜４と上部電極５とを有するものである。In the figure, the present invention includes an insulating film 2 formed along the inner wall of a groove 1a of a silicon substrate 1, a platinum film 3 as a lower electrode formed on the insulating film 2, and a capacitive insulating film 4 formed on the platinum film 3. and an upper electrode 5.
次に本発明に係る半導体記憶素子の製造方法を第１図（
ロ）、 （ｃ）、 （ｄ）を用いて説明する。Next, a method for manufacturing a semiconductor memory element according to the present invention is shown in FIG.
This will be explained using (b), (c), and (d).
まず第１図（ハ）に示すように、シリコン基板ｌに溝＋
ａを形成し、溝１ａの内壁に沿って熱酸化膜等の絶縁膜
２を形成する。First, as shown in FIG. 1 (c), a groove +
Then, an insulating film 2 such as a thermal oxide film is formed along the inner wall of the trench 1a.
次に第１図（ｃ）に示すように絶縁膜２上に、下部電極
としてのプラチナ膜３を成長形成させる。このとき下部
電極ポリシリコンとトランジスタソース電極の接続部（
以下、容量コンタクト部という）はプラチナシリサイド
となリオーミックなコンタクトが得られる。Next, as shown in FIG. 1(c), a platinum film 3 as a lower electrode is grown on the insulating film 2. At this time, the connection part between the lower electrode polysilicon and the transistor source electrode (
The capacitive contact portion (hereinafter referred to as the capacitive contact portion) is made of platinum silicide, and a rhiomic contact can be obtained.
次に第１図（ｄ）に示すように、前記プラチナ膜３上に
容量絶縁膜４としてチタン酸ストロンチウム（ＳｒＴｉ
Ｏ，）またはチタン酸バリウム（ＢａＴｉＯ，）などの
絶縁膜を形成する。本実施例では５ｒＴｉＯ，またはＢ
ａＴｉｅ、を用いたが、本特許においては容量絶縁膜と
しての材料は特に限定されることはない。また、該容量
絶縁膜４は一層でも多層でもよい。Next, as shown in FIG. 1(d), a capacitor insulating film 4 made of strontium titanate (SrTi) is formed on the platinum film 3.
An insulating film such as O, ) or barium titanate (BaTiO, ) is formed. In this example, 5rTiO or B
aTie was used, but the material for the capacitive insulating film is not particularly limited in this patent. Further, the capacitive insulating film 4 may be one layer or multiple layers.
最終に第１図（ａ）に示すように、前記容量絶縁膜４上
にＣＶＤ法によりポリシリコン膜を成長して不純物を拡
散し上部電極５を形成し、本発明に係る半導体記憶素子
を完成させる。上部電極５の材料として金属材料を用い
ることもできる。Finally, as shown in FIG. 1(a), a polysilicon film is grown on the capacitor insulating film 4 by the CVD method and impurities are diffused to form the upper electrode 5, thereby completing the semiconductor memory element according to the present invention. let A metal material can also be used as the material for the upper electrode 5.
本発明では、酸化されにくいプラチナを下部電極として
形成しているため、自然酸化膜は殆ど成長しない。この
ため、従来のシリサイド電極上に形成した絶縁膜に比べ
より信頼性の高い均一な絶縁膜が形成できる。また、容
量コンタクト部はプラチナシリサイドになるので、オー
ミックなコンタクトが形成できる。In the present invention, since platinum, which is difficult to oxidize, is formed as the lower electrode, almost no natural oxide film grows. Therefore, a more reliable and uniform insulating film can be formed compared to the conventional insulating film formed on a silicide electrode. Furthermore, since the capacitive contact portion is made of platinum silicide, an ohmic contact can be formed.
以上述べたように本発明によれば、信頼性の高い均一な
薄い絶縁膜を有する容量素子を容易に形成することがで
きる。As described above, according to the present invention, it is possible to easily form a capacitive element having a highly reliable and uniform thin insulating film.
第１図（ａ）は本発明の一実施例を示す断面図、第１図
（ロ）、 （ｃ）、（ｄ）は本発明の一実施例の製造方
法を工程順に示す断面図、第２図は従来例を示す断面図
である。
■・・・シリコン基板 ２・・・絶縁膜３・・
・プラチナ膜
５・・・上層電極
１３・・・ポリシリコン膜
４・・・容量絶縁膜
１２・・・酸化シリコン膜FIG. 1(a) is a sectional view showing an embodiment of the present invention, FIGS. FIG. 2 is a sectional view showing a conventional example. ■...Silicon substrate 2...Insulating film 3...
・Platinum film 5...Upper layer electrode 13...Polysilicon film 4...Capacitive insulating film 12...Silicon oxide film
Claims (1)
膜並びに上部電極からなる半導体記憶素子において、前
記下部電極にプラチナ電極を用いたことを特徴とする半
導体記憶素子。(1) A semiconductor memory element comprising a lower electrode, a capacitive insulating film, and an upper electrode formed on a silicon substrate, characterized in that a platinum electrode is used for the lower electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249857A JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1249857A JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03110862A true JPH03110862A (en) | 1991-05-10 |
| JP2972238B2 JP2972238B2 (en) | 1999-11-08 |
Family
ID=17199221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1249857A Expired - Lifetime JP2972238B2 (en) | 1989-09-26 | 1989-09-26 | Semiconductor storage element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2972238B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5254498A (en) * | 1991-05-23 | 1993-10-19 | Sony Corporation | Method for forming barrier metal structure |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115843A (en) * | 1981-12-28 | 1983-07-09 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Thin film capacitor |
| JPH0354828A (en) * | 1989-07-24 | 1991-03-08 | Oki Electric Ind Co Ltd | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
-
1989
- 1989-09-26 JP JP1249857A patent/JP2972238B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58115843A (en) * | 1981-12-28 | 1983-07-09 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Thin film capacitor |
| JPH0354828A (en) * | 1989-07-24 | 1991-03-08 | Oki Electric Ind Co Ltd | Compound conductor layer of semiconductor device, hole-making process of capacitor using compound conductor layer and compound conductor layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5254498A (en) * | 1991-05-23 | 1993-10-19 | Sony Corporation | Method for forming barrier metal structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2972238B2 (en) | 1999-11-08 |
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