JPH04267517A - Formation method of semiconductor thin film - Google Patents
Formation method of semiconductor thin filmInfo
- Publication number
- JPH04267517A JPH04267517A JP2874091A JP2874091A JPH04267517A JP H04267517 A JPH04267517 A JP H04267517A JP 2874091 A JP2874091 A JP 2874091A JP 2874091 A JP2874091 A JP 2874091A JP H04267517 A JPH04267517 A JP H04267517A
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous silicon
- silicon
- forming
- semiconductor thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 239000010409 thin film Substances 0.000 title claims description 23
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 238000002425 crystallisation Methods 0.000 claims abstract description 16
- 230000008025 crystallization Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010408 film Substances 0.000 claims description 150
- 239000007790 solid phase Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000010438 heat treatment Methods 0.000 abstract description 10
- 230000006835 compression Effects 0.000 abstract 1
- 238000007906 compression Methods 0.000 abstract 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000008602 contraction Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- -1 which then grow Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052909 inorganic silicate Inorganic materials 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
Abstract
Description
[発明の目的] [Purpose of the invention]
【0001】0001
【産業上の利用分野】本発明は半導体装置の製造方法に
係わり、特に半導体薄膜の形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a semiconductor thin film.
【0002】0002
【従来の技術】最近、半導体装置の製造技術は著しく進
歩し、集積回路の微細化がサブミクロンオーダーで実現
されている。しかしながら、このような微細化も一つ一
つの半導体素子の大きさを小さくするだけではもはや集
積化の限界に達しつつある。そこで一部の素子などを垂
直方向に重ね合わせることにより集積度を上げる方法が
要求されてきている。2. Description of the Related Art Recently, semiconductor device manufacturing technology has made remarkable progress, and integrated circuits have been miniaturized to the submicron order. However, even with such miniaturization, the limit of integration is being reached by simply reducing the size of each semiconductor element. Therefore, there is a need for a method of increasing the degree of integration by vertically overlapping some elements.
【0003】そこで、素子を重ねるために、下地に素子
形成した後この上に絶縁膜を形成し、さらにその後、こ
の絶縁膜上にシリコン膜を形成し、このシリコン膜に素
子形成する技術が開発されてきている。Therefore, in order to stack elements, a technology was developed in which an element is formed on a base, an insulating film is formed on this, a silicon film is then formed on this insulating film, and an element is formed on this silicon film. It has been done.
【0004】このような技術において、上記シリコン膜
を形成する方法として固相成長法がある。この方法は、
絶縁膜上に非晶質(アモルファス)シリコン膜を堆積し
、このアモルファスシリコン膜を熱処理により単結晶膜
或いは結晶粒の大きな多結晶膜に固相成長させる方法で
ある。この固相成長法は、上記熱処理の温度が一般に5
00〜800℃と低いため、下層の下地に既に形成され
た素子にダメージ等の悪影響を及ぼすことがない。[0004] In such technology, there is a solid phase growth method as a method for forming the silicon film. This method is
This is a method in which an amorphous silicon film is deposited on an insulating film, and this amorphous silicon film is grown in a solid phase into a single crystal film or a polycrystalline film with large crystal grains by heat treatment. In this solid phase growth method, the temperature of the heat treatment is generally 5.
Since the temperature is as low as 00 to 800°C, there is no adverse effect such as damage to elements already formed on the underlying base.
【0005】しかしながら、上記固相成長法には次に述
べる問題がある。即ち、固相成長により結晶化が進行す
る際、まず非晶質シリコン膜中で結晶核が発生し、次に
これが成長し、結晶成長が進行する。しかし、この時別
の結晶核が新たに発生し、この核から結晶成長が別に進
行するため、一つ一つの結晶はその成長過程で新しくで
きた別の結晶とぶつかって十分に大きくなることができ
ない。However, the solid phase growth method described above has the following problems. That is, when crystallization progresses by solid phase growth, crystal nuclei are first generated in the amorphous silicon film, which then grow, and crystal growth progresses. However, at this time, another crystal nucleus is newly generated, and crystal growth proceeds separately from this nucleus, so each crystal collides with another newly formed crystal during the growth process, making it impossible for each crystal to grow sufficiently large. Can not.
【0006】以上の問題点は、非晶質シリコン膜の結晶
化の際に、該シリコン膜と下地の絶縁膜、例えば酸化シ
リコン膜との界面で生ずる応力の影響により増々顕著に
なる。図10は、この問題点を説明する説明図である。
この図に示すように、シリコン基板101 上には酸化
シリコン膜102 及び非晶質シリコン膜103 がこ
の順に形成されているが、非晶質シリコン膜103 と
酸化シリコン膜102 との界面では、非晶質シリコン
膜103 の結晶化の際、非晶質シリコン膜103 に
は引張り応力104 が、下地の酸化シリコン膜102
には圧縮応力105 が加わる。この場合、非晶質シ
リコン膜103 中のシリコン原子は上記引張り応力1
04 により結晶格子中の所定の位置に配列することを
妨げられる。従って、非晶質シリコン膜103 の結晶
化部分103aの成長速度は極度に低下せしめられ、こ
のため、この結晶の成長過程で新たな結晶核が多数発生
し、この核からも結晶化が進んでしまう。この結果、結
晶粒の大きさは極度に小さくなってしまう問題があった
。The above-mentioned problems become more and more noticeable due to the effects of stress generated at the interface between the silicon film and the underlying insulating film, such as a silicon oxide film, when the amorphous silicon film is crystallized. FIG. 10 is an explanatory diagram illustrating this problem. As shown in this figure, a silicon oxide film 102 and an amorphous silicon film 103 are formed in this order on a silicon substrate 101, but at the interface between the amorphous silicon film 103 and the silicon oxide film 102, When the crystalline silicon film 103 is crystallized, a tensile stress 104 is applied to the amorphous silicon film 103 and the underlying silicon oxide film 102 is
A compressive stress 105 is applied to . In this case, the silicon atoms in the amorphous silicon film 103 are exposed to the tensile stress 1
04 prevents them from being arranged at predetermined positions in the crystal lattice. Therefore, the growth rate of the crystallized portion 103a of the amorphous silicon film 103 is extremely reduced, and as a result, many new crystal nuclei are generated during the crystal growth process, and crystallization from these nuclei also progresses. Put it away. As a result, there was a problem in that the size of the crystal grains became extremely small.
【0007】[0007]
【発明が解決しようとする課題】以上述べたように、従
来の半導体薄膜の形成方法は、絶縁膜上に形成した非晶
質シリコン膜中で、結晶核からの結晶成長が長く伸びず
、結晶粒が大きくならないという問題を抱えていた。
本発明は上記実情に鑑みてなされたものであり、結晶粒
の大きさを大幅に増加せしめることのできる半導体薄膜
の形成方法を提供することを目的とする。
[発明の構成][Problems to be Solved by the Invention] As described above, in the conventional method for forming semiconductor thin films, crystal growth from crystal nuclei does not extend long in an amorphous silicon film formed on an insulating film, resulting in crystal growth. The problem was that the grains did not grow large. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for forming a semiconductor thin film that can significantly increase the size of crystal grains. [Structure of the invention]
【0008】[0008]
【課題を解決するための手段】前述した問題を解決する
ため本発明は、基体上に非晶質半導体からなる第1の膜
を形成する工程と、この第1の膜上に第1の膜の結晶化
温度より低い温度で第2の膜を形成する工程と、前記第
1の膜を固相成長により結晶化させる工程とを含むこと
を特徴とする半導体薄膜の形成方法を提供する。[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a step of forming a first film made of an amorphous semiconductor on a substrate, and a step of forming a first film on the first film. Provided is a method for forming a semiconductor thin film, comprising the steps of: forming a second film at a temperature lower than the crystallization temperature of the first film; and crystallizing the first film by solid phase growth.
【0009】[0009]
【作用】本発明による半導体薄膜の形成方法であれば、
基体上に形成された非晶質半導体からなる第1の膜上に
、第1の膜の結晶化温度より低い温度で第2の膜を形成
するので、前記第1の膜は結晶化を起こさず、さらにこ
の後、この第1の膜を前記第2の膜を収縮させながら結
晶化するので、この第1の膜は前記第2の膜により圧縮
応力を受ける。前記第1の膜中の原子はこの圧縮応力に
より所定の結晶格子位置に迅速に配列するようになり、
このため第1の膜の結晶化速度は著しく向上する。
従って、膜中で新たな核が形成される前に結晶化が大幅
に進行するので、結晶粒の大きな多結晶半導体膜を形成
でき、この膜に形成する素子の特性を大幅に向上させる
ことができる。[Function] The method for forming a semiconductor thin film according to the present invention,
Since the second film is formed on the first film made of an amorphous semiconductor formed on the substrate at a temperature lower than the crystallization temperature of the first film, the first film does not undergo crystallization. First, after this, the first film is crystallized while shrinking the second film, so that the first film is subjected to compressive stress by the second film. The atoms in the first film are quickly arranged at predetermined crystal lattice positions due to this compressive stress,
Therefore, the crystallization speed of the first film is significantly improved. Therefore, crystallization progresses significantly before new nuclei are formed in the film, making it possible to form a polycrystalline semiconductor film with large crystal grains and greatly improving the characteristics of elements formed in this film. can.
【0010】0010
【実施例】図1〜図6は本発明による半導体薄膜の形成
方法の一実施例を示す工程断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 6 are process cross-sectional views showing an embodiment of a method for forming a semiconductor thin film according to the present invention.
【0011】まず、図1に示すようにシリコン基板1上
に絶縁膜、例えば酸化シリコン膜2を膜厚5000オン
グストロームで形成した後、さらにこの酸化膜2上に多
結晶シリコン膜3を膜厚1000オングストロームで形
成した。この多結晶シリコン膜3は、SiH4 ,He
の混合ガスを用いた通常のLPCVD法により、基板温
度610℃,圧力0.5Torrの条件で堆積せしめた
。First, as shown in FIG. 1, an insulating film, for example a silicon oxide film 2, is formed to a thickness of 5000 angstroms on a silicon substrate 1, and then a polycrystalline silicon film 3 is further formed on this oxide film 2 to a thickness of 1000 angstroms. Formed in angstroms. This polycrystalline silicon film 3 is made of SiH4, He
The deposition was carried out by a conventional LPCVD method using a mixed gas of 1 to 100 mL at a substrate temperature of 610° C. and a pressure of 0.5 Torr.
【0012】次に、図2に示すようにシリコンイオン4
を前記多結晶シリコン膜3にイオン注入することにより
、この膜を非晶質化し、非晶質シリコン膜(第1の膜)
3とした。この時の条件は加速電圧50KeV ,ドー
ズ量1×1015cm−2とした。なお、多結晶シリコ
ン膜3の膜厚が2000オングストロームの場合は、膜
厚が大きいので、膜全体を非晶質化するためには、膜の
深い部分と浅い部分に対して2度にわたってイオン注入
する必要がある。この場合、イオン注入条件は50Ke
V,2.5×1015cm−2及び120KeV,5.
4×1015cm−2とした。Next, as shown in FIG.
By implanting ions into the polycrystalline silicon film 3, this film is made amorphous and an amorphous silicon film (first film) is formed.
It was set as 3. The conditions at this time were an acceleration voltage of 50 KeV and a dose of 1 x 1015 cm-2. Note that when the thickness of the polycrystalline silicon film 3 is 2000 angstroms, the film thickness is large, so in order to make the entire film amorphous, ions are implanted twice into the deep and shallow parts of the film. There is a need to. In this case, the ion implantation conditions are 50Ke
V, 2.5 x 1015 cm-2 and 120 KeV,5.
It was set to 4 x 1015 cm-2.
【0013】次に、図3に示すようにSiH4 及びO
2 の混合ガスを用いたLPCVD法により、基板温度
400℃,SiH4 流量200SCCM,O2 流量
200SCCM,圧力1Torrにて、第2の膜として
酸化シリコン膜5を膜厚3000オングストロームで非
晶質シリコン膜3上に堆積した。この堆積した非晶質シ
リコン膜3は非常にポーラスで電気的耐性が劣っていた
。またこの時、非晶質シリコン膜3はアモルファス状態
のままで結晶化を起こさなかった。Next, as shown in FIG. 3, SiH4 and O
2, a silicon oxide film 5 was formed as the second film with a thickness of 3000 angstroms using an amorphous silicon film 3 at a substrate temperature of 400°C, a SiH4 flow rate of 200SCCM, an O2 flow rate of 200SCCM, and a pressure of 1 Torr. deposited on top. This deposited amorphous silicon film 3 was extremely porous and had poor electrical resistance. Further, at this time, the amorphous silicon film 3 remained in an amorphous state and did not undergo crystallization.
【0014】さらに、図4に示すように基板温度600
℃、処理時間20時間で非酸化性雰囲気、例えばN2
又はAr等の雰囲気下で熱処理を行った。この際、前記
非晶質シリコン膜3は結晶化により体積収縮が起こり、
また酸化シリコン膜5も、SiO4 の正四面体同志の
結合状態が変化し、原子間距離が小さくなることにより
、体積収縮を起こす。非晶質シリコン膜3の体積収縮は
、結晶核形成に所定の時間が必要である一方、酸化シリ
コン膜5はSiO4 正四面体同志の結合状態が容易に
変化するため、酸化シリコン膜5の方が早めに堆積収縮
を起こす。また体積収縮率も、非晶質シリコンが2〜3
%であるのに対し、本実施例で形成した酸化シリコンは
10%弱と著しく大きい。このため、非晶質シリコン膜
3は酸化シリコン膜5により圧縮応力を受け、この応力
により結晶化の速度が大幅に向上する。即ち、非晶質シ
リコン膜3中のシリコン原子が、この応力により所定の
結晶格子位置に迅速に配列するようになり、このため非
晶質シリコン膜3の結晶化速度は著しく向上する。本実
施例ではこの圧縮応力の値は108 〜109 dym
/cm2 であり、結晶化速度は酸化膜5を用いない
場合と比べてほぼ2倍となった。このように結晶化速度
が向上すれば、アモルファス膜中で新たな核が形成され
る前に、結晶は大きく成長することができる。実際、本
実施例で、酸化膜5のない場合と比べてほぼ2倍の大き
さの結晶粒が形成されていることを確認した。なお、こ
の場合、結晶核の形成速度(活性化エネルギー)は変わ
らない。Furthermore, as shown in FIG.
℃, treatment time 20 hours in a non-oxidizing atmosphere, e.g. N2
Alternatively, heat treatment was performed in an atmosphere such as Ar. At this time, the amorphous silicon film 3 undergoes volumetric contraction due to crystallization.
In addition, the silicon oxide film 5 also undergoes volumetric contraction due to a change in the bonding state between SiO4 regular tetrahedrons and a decrease in interatomic distance. The volume contraction of the amorphous silicon film 3 is caused by the fact that a certain amount of time is required for the formation of crystal nuclei, while the bonding state of SiO4 regular tetrahedrons in the silicon oxide film 5 changes easily. causes early deposition and shrinkage. Also, the volume shrinkage rate of amorphous silicon is 2 to 3.
%, whereas the silicon oxide formed in this example is significantly larger at just under 10%. Therefore, the amorphous silicon film 3 is subjected to compressive stress by the silicon oxide film 5, and this stress significantly increases the speed of crystallization. That is, the silicon atoms in the amorphous silicon film 3 are quickly aligned at predetermined crystal lattice positions due to this stress, so that the crystallization rate of the amorphous silicon film 3 is significantly improved. In this example, the value of this compressive stress is 108 to 109 dym.
/cm2, and the crystallization rate was almost twice that of the case where the oxide film 5 was not used. If the crystallization rate is improved in this way, the crystal can grow to a large size before new nuclei are formed in the amorphous film. In fact, in this example, it was confirmed that crystal grains approximately twice the size were formed compared to the case without the oxide film 5. In this case, the formation rate (activation energy) of crystal nuclei remains unchanged.
【0015】次に、図5に示すように弗酸又は弗化アン
モニウム溶液等を用いて、上記酸化シリコン膜5の除去
を行った。なおここで、この酸化膜の除去は所望により
行わなくてもよい。但し、薄膜トランジスタのように薄
い素子の場合は、後工程を容易にするため除去した方が
好ましい。Next, as shown in FIG. 5, the silicon oxide film 5 was removed using hydrofluoric acid or ammonium fluoride solution. Note that here, the removal of this oxide film may not be performed if desired. However, in the case of a thin element such as a thin film transistor, it is preferable to remove it in order to facilitate post-processing.
【0016】最後に、図6に示すように、イオン注入に
よるソース6a,ドレイン6bの形成、LOCOS法に
よる素子分離絶縁膜7の形成を行った後、通常の方法に
よりゲート絶縁膜(厚み350〜450オングストロー
ム)8,ゲート電極(厚み4000オングストローム)
9,層間絶縁膜10,コンタクト配線11a,11b,
パッシベーション膜12を形成し、薄膜MOSトランジ
スタを完成した。Finally, as shown in FIG. 6, after forming a source 6a and a drain 6b by ion implantation and forming an element isolation insulating film 7 by LOCOS method, a gate insulating film (thickness 350 to 450 angstroms) 8, Gate electrode (thickness 4000 angstroms)
9, interlayer insulating film 10, contact wiring 11a, 11b,
A passivation film 12 was formed to complete a thin film MOS transistor.
【0017】次に、酸化膜を用いた本発明による方法で
形成した多結晶シリコン膜を用いてMOS素子を作製し
た場合の移動度を、酸化膜を用いない従来の方法で形成
した多結晶シリコン膜の場合と比較した。Next, we will compare the mobility when a MOS device is manufactured using a polycrystalline silicon film formed by the method according to the present invention using an oxide film compared to that of polycrystalline silicon film formed by a conventional method that does not use an oxide film. A comparison was made with the case of membrane.
【0018】図7は、本発明による方法で形成した膜の
場合の移動度を示した特性図,図8は、従来の方法で形
成した膜の場合の移動度を示した特性図である。これら
の図を見てわかるように、本発明を用いた場合のMOS
素子は、従来のMOS素子と比べて、移動度が大きくな
るとともに、そのばらつきが小さくなっている。即ち、
素子特性が改善されたことがわかる。FIG. 7 is a characteristic diagram showing the mobility of a film formed by the method according to the present invention, and FIG. 8 is a characteristic diagram showing the mobility of a film formed by the conventional method. As can be seen from these figures, the MOS when using the present invention
The device has higher mobility and smaller variations than conventional MOS devices. That is,
It can be seen that the device characteristics were improved.
【0019】なおここで、本発明の方法により形成する
MOS素子は次のようにして作製した。即ち、上記実施
例方法により形成した非晶質シリコン膜にチャネルを形
成するため燐を加速電圧15KeV ,ドーズ量1×1
013cm−2でイオン注入し、さらに酸化シリコン膜
を2000オングストロームで上記実施例と同じ方法に
より堆積した。さらに700℃、5時間の熱処理を行う
ことにより前記非晶質シリコン膜を結晶化させ、この膜
に幅1μm,長さ0.5μmのMOS素子を作製した。
ここでは700℃、5時間という高温、短時間の熱処理
を行うことにより、結晶粒の大きさを小さくし、素子間
の移動度のばらつきを極力抑えた。Note that the MOS device formed by the method of the present invention was manufactured in the following manner. That is, in order to form a channel in the amorphous silicon film formed by the method of the above embodiment, phosphorus was applied at an acceleration voltage of 15 KeV and a dose of 1×1.
Ions were implanted to a thickness of 0.13 cm@-2, and a silicon oxide film was deposited to a thickness of 2000 .ANG. by the same method as in the above embodiment. The amorphous silicon film was further crystallized by heat treatment at 700° C. for 5 hours, and a MOS element having a width of 1 μm and a length of 0.5 μm was fabricated on this film. Here, by performing heat treatment at a high temperature of 700° C. for 5 hours for a short time, the size of crystal grains was reduced and variation in mobility between elements was suppressed as much as possible.
【0020】一方、従来の方法により形成するMOS素
子は、従来通り酸化シリコン膜無しで結晶化を行い、こ
の膜に本発明によるものと同じ大きさのMOS素子を作
製した。On the other hand, a MOS element formed by the conventional method was crystallized without a silicon oxide film as before, and a MOS element of the same size as the one according to the present invention was fabricated using this film.
【0021】また、上記したMOS素子の結晶粒の大き
さを、透過電子顕微鏡を用いた観察により測定した。そ
の結果、本発明を用いた場合のMOS素子の方が、従来
の場合よりも最大の結晶粒の大きさが約0.5μmと2
倍以上大きく、また粒の大きさのばらつきも少なかった
。この理由は、本発明の方法を用いれば、酸化シリコン
膜から受ける圧縮応力により結晶粒の大きさを十分大き
くすることができるとともに、チャネル領域より適度に
小さい状態でその大きさを揃えることができるからであ
る。従って、どの素子のチャネル領域でも安定してほぼ
同じ数の少数の粒界を含ませることができ、素子特性を
向上させることができる。次に、非晶質シリコン膜をシ
リコン基板の一部表面を種部として結晶化する方法に本
発明を適用した他の実施例について説明する。Furthermore, the size of the crystal grains of the above-mentioned MOS device was measured by observation using a transmission electron microscope. As a result, the MOS device using the present invention has a maximum crystal grain size of approximately 0.5 μm, which is 2.
It was more than twice as large, and the variation in grain size was also small. The reason for this is that by using the method of the present invention, the size of the crystal grains can be made sufficiently large due to the compressive stress received from the silicon oxide film, and the sizes can be made uniform while being appropriately smaller than the channel region. It is from. Therefore, the channel region of any device can stably contain approximately the same number of small grain boundaries, and device characteristics can be improved. Next, another embodiment in which the present invention is applied to a method of crystallizing an amorphous silicon film using a part of the surface of a silicon substrate as a seed will be described.
【0022】図9はこの実施例を示す断面図である。こ
の図に示すように、シリコン基板21上にはLOCOS
法により酸化シリコン膜22が選択的に形成されており
、その全面に非晶質シリコン膜(第1の膜)23が形成
されている。この非晶質シリコン膜23は多結晶シリコ
ン膜を2000オングストローム堆積し、シリコンイオ
ン注入(加速電圧/ドーズ量:50KeV /2.5×
1015cm−2,120Kev /5.4×1015
cm−2)でアモルファス化して形成したものである。
ここで、酸化シリコン膜22が形成されないシリコン基
板21表面は種部21aとして非晶質シリコン膜23と
接続しており、この種部21aから非晶質シリコンが結
晶化する。23aはその結晶化部分である。さらに非晶
質シリコン膜23上には第2の膜として酸化シリコン膜
24が形成されている。この膜24はCVD法によりS
iO2 を前述した図5の工程と同じ条件で堆積したも
のである。FIG. 9 is a sectional view showing this embodiment. As shown in this figure, there is a LOCOS on the silicon substrate 21.
A silicon oxide film 22 is selectively formed by a method, and an amorphous silicon film (first film) 23 is formed on the entire surface thereof. This amorphous silicon film 23 is made by depositing a polycrystalline silicon film with a thickness of 2000 angstroms and implanting silicon ions (acceleration voltage/dose amount: 50 KeV/2.5×
1015cm-2,120Kev /5.4×1015
cm-2) to become amorphous. Here, the surface of the silicon substrate 21 on which the silicon oxide film 22 is not formed is connected to the amorphous silicon film 23 as a seed portion 21a, and amorphous silicon is crystallized from this seed portion 21a. 23a is its crystallized portion. Furthermore, a silicon oxide film 24 is formed as a second film on the amorphous silicon film 23. This film 24 is made of S by the CVD method.
iO2 was deposited under the same conditions as in the process of FIG. 5 described above.
【0023】以上の試料に対して前述した図4の工程と
同じ条件で熱処理を行うことにより、非晶質シリコン膜
23の結晶化を行った。その結果、熱処理により種部2
1aから単結晶化できる距離は15μmとなり、従来方
法による距離5μmと比較して飛躍的に向上させること
ができた。The amorphous silicon film 23 was crystallized by subjecting the above sample to heat treatment under the same conditions as in the process shown in FIG. 4 described above. As a result, the seed part 2 is
The distance from 1a that could be made into a single crystal was 15 μm, which was a dramatic improvement compared to the distance of 5 μm according to the conventional method.
【0024】この理由は、非晶質シリコン膜23を結晶
化させるための熱処理の際、酸化シリコン膜24は矢印
Aの方向に収縮し、この収縮のため非晶質シリコン膜2
3には矢印Bの方向に圧縮応力が働くので、前述した実
施例と同様の作用により結晶成長が促進されるからであ
る。The reason for this is that during the heat treatment for crystallizing the amorphous silicon film 23, the silicon oxide film 24 contracts in the direction of arrow A, and due to this contraction, the amorphous silicon film 2
This is because compressive stress acts in the direction of the arrow B in 3, so crystal growth is promoted by the same effect as in the above-mentioned embodiment.
【0025】なお、本発明は上記実施例に限定されるこ
とはない。例えば、非晶質シリコン膜上に形成する酸化
シリコン膜の形成条件としては、基板温度は350〜5
00℃の範囲内、SiH4 及びO2 の流量はともに
50〜500SCCMの範囲内、圧力は1Torr以下
が好ましく、この範囲を基準として適宜変更できる。Note that the present invention is not limited to the above embodiments. For example, the conditions for forming a silicon oxide film on an amorphous silicon film include a substrate temperature of 350 to 50°C.
It is preferable that the temperature is within the range of 00°C, the flow rates of both SiH4 and O2 are within the range of 50 to 500 SCCM, and the pressure is 1 Torr or less, and can be changed as appropriate based on this range.
【0026】また、第2の膜として上記した酸化シリコ
ン膜の代わりに窒化シリコン膜を用いてもよく、例えば
SiH4 やNH3 等のガスを用いて形成できる。こ
の場合の形成条件としては、基板温度は350〜500
℃の範囲内、SiH4 及びNH3の流量はともに50
〜500SCCMの範囲内が好ましい。Furthermore, a silicon nitride film may be used as the second film instead of the silicon oxide film described above, and can be formed using a gas such as SiH4 or NH3. In this case, the forming conditions include a substrate temperature of 350 to 500.
℃, the flow rates of SiH4 and NH3 are both 50℃.
It is preferably within the range of ~500 SCCM.
【0027】さらにまた、非晶質シリコン膜としては、
既に述べたイオン注入により作ったものでなくても、S
iH4 やSi2 H6等を用いたCVD法により直接
形成した膜でも同様の挙動を示し、いずれも本発明によ
る方法を用いての熱処理により、同様の結果を得ること
ができた。ここで言うCVDの条件としては、非晶質シ
リコンを堆積させる温度は450〜600℃の範囲、原
料ガスとしてシランガスを用いる場合その分圧は0.1
〜5.0Torr、ジシランガスを用いる場合その分圧
は0.1〜5.0Torrの範囲である。Furthermore, as an amorphous silicon film,
Even if it is not made by ion implantation as mentioned above, S
Films directly formed by the CVD method using iH4, Si2 H6, etc. showed similar behavior, and similar results could be obtained in both cases by heat treatment using the method according to the present invention. The CVD conditions mentioned here are that the temperature for depositing amorphous silicon is in the range of 450 to 600°C, and when silane gas is used as the raw material gas, the partial pressure is 0.1
~5.0 Torr, and when disilane gas is used, its partial pressure is in the range of 0.1 to 5.0 Torr.
【0028】さらにまた、固相成長のための熱処理温度
は550〜700℃が好ましく、この固相成長せしめる
非晶質半導体膜は非晶質シリコン以外の材料の膜であっ
てもよい。Furthermore, the heat treatment temperature for solid phase growth is preferably 550 to 700° C., and the amorphous semiconductor film to be grown in solid phase may be made of a material other than amorphous silicon.
【0029】その他、一般に不純物の添加により結晶成
長速度は増加するが、本発明による半導体薄膜の形成方
法では、固相成長法において、非常に少ない不純物量、
例えばチャネルイオン注入程度の量でも十分結晶粒を大
きくする効果が現れた。実験によると、燐以外にもボロ
ン、砒素等 III族或いはV族の不純物についても同
様の効果があった。In addition, the crystal growth rate is generally increased by adding impurities, but in the method for forming a semiconductor thin film according to the present invention, in the solid phase growth method, the amount of impurities is extremely small.
For example, even an amount equivalent to channel ion implantation has the effect of sufficiently enlarging crystal grains. According to experiments, similar effects were found with group III or group V impurities such as boron and arsenic in addition to phosphorus.
【0030】また、非晶質シリコン膜上に形成する酸化
シリコン膜の厚さを変えると結晶成長速度を変えること
ができ、結晶粒の大きさを素子のチャネルの大きさに合
わせて制御することができた。即ち、この場合、酸化シ
リコン膜の厚さを厚くすると、非晶質シリコン膜に加わ
る圧縮応力が大きくなり、このため結晶粒の大きさは大
きくなる。また逆に膜厚を薄くすると、結晶粒の大きさ
は小さくなる。Furthermore, by changing the thickness of the silicon oxide film formed on the amorphous silicon film, the crystal growth rate can be changed, and the size of the crystal grains can be controlled to match the size of the channel of the device. was completed. That is, in this case, when the thickness of the silicon oxide film is increased, the compressive stress applied to the amorphous silicon film increases, and therefore the size of the crystal grains increases. Conversely, when the film thickness is reduced, the size of the crystal grains becomes smaller.
【0031】さらにまた、本発明による方法によれば、
結晶成長速度を早くすることで結晶化に必要な全工程の
時間を短くすることができ、プロセス時間の短縮化を図
ることができた。Furthermore, according to the method according to the invention,
By increasing the crystal growth rate, the total time required for crystallization could be shortened, and the process time could be shortened.
【0032】[0032]
【発明の効果】本発明による半導体薄膜の形成方法によ
れば、結晶粒の大きな多結晶半導体膜を形成することが
でき、この膜に形成する素子の特性を大幅に向上させる
ことが可能となる。[Effects of the Invention] According to the method for forming a semiconductor thin film according to the present invention, a polycrystalline semiconductor film with large crystal grains can be formed, and the characteristics of elements formed in this film can be significantly improved. .
【図1】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 1 is a process sectional view showing an embodiment of a method for forming a semiconductor thin film according to the present invention.
【図2】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 2 is a process cross-sectional view showing an embodiment of the method for forming a semiconductor thin film according to the present invention.
【図3】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 3 is a process cross-sectional view showing an embodiment of the method for forming a semiconductor thin film according to the present invention.
【図4】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 4 is a process cross-sectional view showing an embodiment of the method for forming a semiconductor thin film according to the present invention.
【図5】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 5 is a process cross-sectional view showing an embodiment of the method for forming a semiconductor thin film according to the present invention.
【図6】 本発明による半導体薄膜の形成方法の一実
施例を示す工程断面図。FIG. 6 is a process sectional view showing an embodiment of the method for forming a semiconductor thin film according to the present invention.
【図7】 本発明による方法で形成した半導体薄膜を
用いてMOS素子を作製した場合の移動度を示した特性
図。FIG. 7 is a characteristic diagram showing the mobility when a MOS device is manufactured using a semiconductor thin film formed by the method according to the present invention.
【図8】 従来の方法で形成した半導体薄膜を用いて
MOS素子を作製した場合の移動度を示した特性図。FIG. 8 is a characteristic diagram showing the mobility when a MOS device is manufactured using a semiconductor thin film formed by a conventional method.
【図9】 本発明を用いた他の実施例を示す断面図。FIG. 9 is a sectional view showing another embodiment using the present invention.
【図10】 従来の方法の問題点を説明する説明図。FIG. 10 is an explanatory diagram illustrating problems with the conventional method.
1,21,101…シリコン基板、
2,22,102…酸化シリコン膜、
3,23,103…非晶質シリコン膜、4…シリコンイ
オン、
5,24…酸化シリコン膜(第2の膜)、6a…ソース
、
6b…ドレイン、
7…素子分離絶縁膜、
8…ゲート絶縁膜、
9…ゲート電極、
10…層間絶縁膜、
11a,11b…コンタクト配線、
12…パッシベーション膜、
21a…種部、
23a,103a…非結晶シリコン膜の結晶化部分、A
…酸化シリコン膜24の収縮の方向、B…非晶質シリコ
ン膜23に働く圧縮応力の方向、103…非晶質シリコ
ン膜、
104…引張り応力、
105…圧縮応力。1,21,101...Silicon substrate, 2,22,102...Silicon oxide film, 3,23,103...Amorphous silicon film, 4...Silicon ion, 5,24...Silicon oxide film (second film), 6a... Source, 6b... Drain, 7... Element isolation insulating film, 8... Gate insulating film, 9... Gate electrode, 10... Interlayer insulating film, 11a, 11b... Contact wiring, 12... Passivation film, 21a... Seed part, 23a , 103a...Crystallized portion of the amorphous silicon film, A
... direction of contraction of silicon oxide film 24, B... direction of compressive stress acting on amorphous silicon film 23, 103... amorphous silicon film, 104... tensile stress, 105... compressive stress.
Claims (4)
膜を形成する工程と、この第1の膜上に第1の膜の結晶
化温度より低い温度で第2の膜を形成する工程と、前記
第1の膜を固相成長により結晶化させる工程とを含むこ
とを特徴とする半導体薄膜の形成方法。1. A step of forming a first film made of an amorphous semiconductor on a substrate, and forming a second film on the first film at a temperature lower than the crystallization temperature of the first film. A method for forming a semiconductor thin film, comprising the steps of: and crystallizing the first film by solid phase growth.
に、前記第2の膜を除去する工程を行うことを特徴とす
る請求項1記載の半導体薄膜の形成方法。2. The method of forming a semiconductor thin film according to claim 1, wherein a step of removing the second film is performed after the step of crystallizing the first film.
り、前記第2の膜は酸化シリコン膜又は窒化シリコン膜
であることを特徴とする請求項1記載の半導体薄膜の形
成方法。3. The method of forming a semiconductor thin film according to claim 1, wherein the first film is an amorphous silicon film, and the second film is a silicon oxide film or a silicon nitride film.
膜をCVD法により形成することを特徴とする請求項3
記載の半導体薄膜の形成方法。4. Claim 3, wherein the silicon oxide film or the silicon nitride film is formed by a CVD method.
The method for forming the semiconductor thin film described above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2874091A JPH04267517A (en) | 1991-02-22 | 1991-02-22 | Formation method of semiconductor thin film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2874091A JPH04267517A (en) | 1991-02-22 | 1991-02-22 | Formation method of semiconductor thin film |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04267517A true JPH04267517A (en) | 1992-09-24 |
Family
ID=12256821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2874091A Pending JPH04267517A (en) | 1991-02-22 | 1991-02-22 | Formation method of semiconductor thin film |
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Country | Link |
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JP (1) | JPH04267517A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243576A (en) * | 1992-02-28 | 1993-09-21 | Casio Comput Co Ltd | Semiconductor device |
-
1991
- 1991-02-22 JP JP2874091A patent/JPH04267517A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243576A (en) * | 1992-02-28 | 1993-09-21 | Casio Comput Co Ltd | Semiconductor device |
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