JPH0426546U - - Google Patents
Info
- Publication number
- JPH0426546U JPH0426546U JP6754190U JP6754190U JPH0426546U JP H0426546 U JPH0426546 U JP H0426546U JP 6754190 U JP6754190 U JP 6754190U JP 6754190 U JP6754190 U JP 6754190U JP H0426546 U JPH0426546 U JP H0426546U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- semiconductor element
- accommodating
- wiring layer
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の半導体素子収納用パツケージ
の一実施例を示す断面図、第2図a,b,cは第
1図に示すパツケージの絶縁基体の製造方法を説
明するための各工程毎の断面図、第3図は従来の
半導体素子収納用パツケージの断面図、第4図は
第3図に示すパツケージの製造方法を説明するた
めの断面図である。
1……絶縁基体、1a……凹部、1b……貫通
孔、2……蓋体、5……メタライズ配線層、7…
…外部リード端子。
FIG. 1 is a cross-sectional view showing an embodiment of the package for housing semiconductor elements of the present invention, and FIGS. 3 is a sectional view of a conventional package for housing semiconductor elements, and FIG. 4 is a sectional view for explaining a method of manufacturing the package shown in FIG. 3. DESCRIPTION OF SYMBOLS 1...Insulating base, 1a...Recess, 1b...Through hole, 2...Lid, 5...Metalized wiring layer, 7...
...External lead terminal.
Claims (1)
子の各電極を外部電気回路に電気的に接続するた
めのメタライズ配線層を有する絶縁基体と蓋体と
から成る半導体素子収納用パツケージにおいて、
前記メタライズ配線層が絶縁基体の凹部周辺より
凹部内壁面を経て凹部底面に導出され、且つ該凹
部底面に穿設した貫通孔を介して絶縁基体底面に
延出されていることを特徴とする半導体素子収納
用パツケージ。 A package for accommodating a semiconductor element comprising an insulating base body and a lid body having a recess for accommodating the semiconductor element and a metallized wiring layer for electrically connecting each electrode of the semiconductor element to an external electric circuit,
A semiconductor characterized in that the metallized wiring layer is led out from the periphery of the recess of the insulating substrate through the inner wall surface of the recess to the bottom surface of the recess, and extends to the bottom surface of the insulating substrate through a through hole formed in the bottom surface of the recess. Package cage for storing elements.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990067541U JP2514094Y2 (en) | 1990-06-26 | 1990-06-26 | Package for storing semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990067541U JP2514094Y2 (en) | 1990-06-26 | 1990-06-26 | Package for storing semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0426546U true JPH0426546U (en) | 1992-03-03 |
JP2514094Y2 JP2514094Y2 (en) | 1996-10-16 |
Family
ID=31601200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990067541U Expired - Lifetime JP2514094Y2 (en) | 1990-06-26 | 1990-06-26 | Package for storing semiconductor devices |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2514094Y2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11251488A (en) * | 1998-03-05 | 1999-09-17 | Sumitomo Metal Electronics Devices Inc | Ceramic package |
JP2001110941A (en) * | 1999-10-06 | 2001-04-20 | Meito Chin | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63261862A (en) * | 1987-04-20 | 1988-10-28 | Sumitomo Electric Ind Ltd | Semiconductor device |
-
1990
- 1990-06-26 JP JP1990067541U patent/JP2514094Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63261862A (en) * | 1987-04-20 | 1988-10-28 | Sumitomo Electric Ind Ltd | Semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11251488A (en) * | 1998-03-05 | 1999-09-17 | Sumitomo Metal Electronics Devices Inc | Ceramic package |
JP2001110941A (en) * | 1999-10-06 | 2001-04-20 | Meito Chin | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2514094Y2 (en) | 1996-10-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |