JPH04264736A - Gallium arsenide field effect transistor - Google Patents

Abstract

PURPOSE:To suppress kink phenomenon and current control and improve the performance of a field effect transistor(FET) by forming a high-concentration layer between an operating layer other than the part directly under a gate electrode and a buffer layer. CONSTITUTION:On a semi-insulating semiconductor substrate 1, a buffer layer 2, an operating layer 6 and a cap layer 7 are laminated, a Shottky gate electrode 8 is formed on the operating layer 6 and a source electrode 9 and a drain electrode 10 are formed on the cap layer 7. A high-concentration N-type GaAs layer 4 is formed between the operating layer 6 other than the part directly under a gate electrode and the buffer layer 2. A hole in the operating layer 6 is induced on the buffer layer 2 side, however, for the high-concentration N-type GaAs layer 4, since the recombination velocity is high, accumulation is not easily permitted and kink phenomenon is suppressed. The expansion of an area which controls the current of a depleted layer, etc., from the buffer layer 2 side between the gate electrode 8 and the drain electrode 10 while the FET is operating is suppressed by the high-concentration N-type GaAs layer and the deterioration of performance is reduced.

Description

[Detailed description of the invention]

0001

FIELD OF THE INVENTION This invention relates to gallium arsenide field effect transistors.

0002

[Prior Art] Gallium arsenide (GaAs)
) A field effect transistor (FET) will be explained with reference to FIG.

[0003] Non-doped A is deposited on a semi-insulating GaAs substrate 1.
A lGaAs buffer layer 2, an N-type GaAs operating layer 6, and a highly doped N-type GaAs cap layer 7 are stacked. A gate electrode 8 that makes Schottky contact is formed where the surfaces of the heavily doped N-type GaAs cap layer 7 and the N-type GaAs active layer 6 are mesa-etched. High concentration N-type GaAs
A source electrode 9 and a drain electrode 10 are formed on the cap layer 7 and are in ohmic contact with each other.

[0004] In order to improve the gain at high frequencies, the gate length is shortened, but if the insulation of the buffer layer 2 is poor, the performance of the FET will deteriorate, such as a decrease in gain. Therefore, by forming a heterojunction with the active layer 6 using the buffer layer 2 made of non-doped AlGaAs, the current from the N-type GaAs active layer 6 to the non-doped AlGaAs buffer layer 2 is blocked and the gm in minute currents is improved. Ta.

[0005]

[Problem to be solved by the invention] GaA according to prior art
In the s-field effect transistor, holes are induced and accumulated on the active layer side of the heterojunction. As a result, holes are generated due to partial avalanche breakdown, and these holes flow to the interface (kink phenomenon).

[0006] Also, a depletion layer extends from the buffer layer,
There is a problem in that the active layer between the gate and drain, which is the path for carriers, is narrowed, limiting current and degrading performance.

[0007]

[Means for Solving the Problems] A gallium arsenide field effect transistor of the present invention has a buffer layer, an active layer, and a cap layer stacked in this order on one main surface of a semi-insulating semiconductor substrate, and the cap layer is removed. A Schottky gate electrode is formed on the exposed active layer, a source-drain electrode in ohmic contact is formed on the cap layer, and a high concentration layer is formed between the active layer and the buffer layer except directly below the Schottky gate electrode. It is made up of layers.

[0008]

[Example] Regarding the first example of the present invention, FIG. 1(a)
Explain with reference to.

Non-doped A is deposited on the semi-insulating GaAs substrate 1.
A lGaAs buffer layer 2, an N-type GaAs operating layer 6, and a high concentration N-type GaAs cap layer 7 are laminated, and the N-type GaAs
As in the prior art, a Schottky gate electrode 8 is formed on the active layer 6, and a source electrode 9 and a drain electrode 10 are formed on the highly doped N-type GaAs cap layer 7.

In this embodiment, an electron carrier concentration of 5.0 x 1023 to
A highly concentrated N-type GaAs layer 4 having a size of 1.0×10 24 cm −3 and a thickness of 5 to 30 nm is formed.

Holes in the N-type GaAs active layer 6 are guided toward the non-doped AlGaAs buffer layer 2, but the high concentration N-type GaAs layer 4 has a high recombination rate, so accumulation is difficult to occur and "kink" is suppressed. can do.

Also, during the operation of the FET, the non-doped AlGaAs buffer layer 2 between the gate electrode 8 and the drain electrode 10 is
The highly doped N-type GaAs layer 4 suppresses the expansion of a region that limits current, such as a depletion layer, from the side, which has the effect of reducing performance deterioration.

Furthermore, the non-doped AlGaAs buffer layer 2 has the effect of preventing impurity diffusion from the N-type GaAs active layer 6 directly below the gate electrode 8.

Next, a second embodiment of the present invention will be described with reference to FIG. 1(b).

In this embodiment, a non-doped GaAs buffer layer 3 and an N-type GaAs layer are formed on a semi-insulating GaAs substrate 1.
An s-active layer 6 and a high concentration N-type GaAs cap layer 7 are laminated, and a Schottky gate electrode 8 is formed on the N-type GaAs active layer 6.
is formed, and a source electrode 9 and a drain electrode 10 are formed on the heavily doped N-type GaAs cap layer 7.

Since the GaAs layer is used instead of the AlGaAs layer as the buffer layer, holes are not accumulated, but there is an effect of relaxing the current restriction.

[0017] Also, between the high concentration N type GaAs layers 4 is a P type G layer.
By forming the aAs layer 5, leakage current to the substrate 1 can be blocked.

[0018]

[Effect of the invention] By forming a high concentration layer between the active layer and the buffer layer other than directly under the gate electrode, "kink" can be prevented.
It was also possible to suppress current limitation and improve FET performance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the structure of a GaAs field effect transistor according to the prior art.

[Explanation of symbols]

1 Semi-insulating GaAs substrate 2 Non-doped AlGaAs buffer layer 3
Non-doped GaAs buffer layer 4 High concentration N-type GaAs layer 5 P-type GaAs layer 6 N-type GaAs operating layer 7 High concentration N-type GaAs cap layer 8 Gate electrode 9 Source electrode 10 Drain electrode

Claims (2)

[Claims] 1. A buffer layer, an active layer, and a cap layer are sequentially stacked on one main surface of a semi-insulating semiconductor substrate, and a Schottky gate electrode is formed on the active layer exposed by removing the cap layer, In the gallium arsenide field effect transistor in which a source-drain electrode is formed in ohmic contact on the cap layer, a high concentration layer is formed between the active layer other than directly under the Schottky gate electrode and the buffer layer. A gallium arsenide field effect transistor featuring: 2. The gallium arsenide field effect transistor according to claim 1, wherein a P-type layer is formed directly under the Schottky gate electrode sandwiched between the high concentration layers.