JPH0425945A - Incircuit emulator - Google Patents

Abstract

PURPOSE:To normally operate an incircuit emulator by switching an F/W memory to the memory of a user program area to execute DMA transfer when DMA transfer is executed in the middle of a supervisor interruption processing, and switching the memory to the F/W memory when DMA transfer terminates to continue the processing. CONSTITUTION:When DMA is generated in the middle of supervisor interruption, the output DMAAK signal of an evachip 201 becomes active 'L' and a system comes to a state showing DMA transfer. Thus, one of inputs from NAND 202 becomes 'L' and therefore an FACS signal becomes 'H'. Thus, the F/W memory 204 comes to a disable state, a buffer (2) 210 comes to an enable state and the system comes to a state where DMA transfer is possible. When DMA transfer terminates, the F/W memory 204 comes to the enable state and the buffer (2) 210 comes to the disable state, whereby the system returns to a supervisor interruption processing state. Thus, DMA transfer in the middle of the supervisor interuption processing can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an in-circuit emulator, and in particular to a DM
This invention relates to an in-circuit emulator that is compatible with microcomputers that have built-in A functions.

[Conventional technology]

Conventionally, this type of in-circuit emulator (hereinafter referred to as IE
) sets a breakpoint at any address in the program or under any condition, and when this AI pulse section is executed or the condition is met, execution of the user program is stopped (hereinafter this operation is referred to as a "break"), and a supervisor interrupt is generated. Start processing. During this supervisor interrupt processing, the emulation CPU (referred to as the IFF Eva chip) inside the IE was structured so that the registers and memory could be read and changed by the program on the F/W memory.

Further, when a DMA transfer occurs during supervisor interrupt processing, the memory accessed by the evaluation chip is not switched from the F/W memory to the memory in the user block area.

[Problem to be solved by the invention]

The above-mentioned conventional IE does not have a structure in which when a DMA transfer occurs during supervisor interrupt processing, the memory to be accessed by the evaluation switch is switched from the F/W memory to the memory in the knee program area.

For this reason, in conventional IE, D
When MA occurs, for example, when DMA transfer should be performed between the user program area memory and Ilo, the DMA transfer is performed between the F/W memory and Ilo, and the F/W memory is destroyed. This had the disadvantage that the Inserkit emulator would not work properly.

Further, if DMA can be prohibited during supervisor interrupt processing, the above problem can be avoided, but even in that case, there are the following drawbacks.

First, when depacking a user system that refreshes DRAM using DMA transfer using conventional IE, there is a problem that the contents of DRAM will be destroyed because DRAM will not be refreshed during supervisor interrupt processing. was there.

Also, when depacking a user system that displays on a CRT monitor using DMA transfer,
There was a problem in that the display on the CRT monitor stopped during supervisor interrupt processing.

[Means to solve the problem]

The IE of the present invention includes a microcomputer with a built-in DMA function, a signal indicating that a supervisor interrupt is being processed, a circuit that detects that a DMA transfer has occurred during the supervisor interrupt processing, and a supervisor interrupt that is generated by the detection signal. It has means for interrupting processing, a circuit for detecting the end of DMA transfer, and means for performing supervisor interrupt processing again.

That is, in contrast to the conventional IE described above, when a DMA transfer occurs during supervisor interrupt processing, the IE of the present invention switches the memory accessed by the evaluation chip from the F/W memory to the memory in the user program area and performs the DMA transfer. When the DMA transfer is completed, the controller switches to the F/W memory again and continues the supervisor interrupt processing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an IE according to an embodiment of the present invention.

In Fig. 1, 101 is an evaluation chip mounted inside the IE, 102 is a decoder that decodes the bus status, detects the occurrence of DMA transfer, and generates a DMACY signal, and 103 controls the direction of the data bus buffer. D
A decoder ■ that generates a B R/W signal, 104 is a DM
NAND, 10 that generates the FAC8 signal for determining whether to enable or disable the F/W memory and buffer ■ from the DEGPRC8 signal of the ACY signal.
5 is an F/W memory accessed by the evaluation chip during supervisor interrupt processing; 106 is a mapping memory that records the mapping state of the user program area and switches between emulation memory and user memory; 107 is an I/W memory;
E internal emulation memory, 108 address bus buffer, 109 user memory of the Nisa system,
110 is a user I10 of the user system. 111 is a data bus buffer (hereinafter referred to as buffer 2).

Here, the operation of the IE of this patent will be explained as follows. First, when no supervisor interrupt occurs, the DECPRC8 signal is inactive "L" and the FAC8 signal is "H", so the F/W memory 105 is in a disabled state.

If a supervisor interrupt occurs here, DEGPR
Since the C8 signal becomes active HIGH and the FACS signal becomes ``L''', the F/W memo! J105 becomes enabled. At this time, the buffer 111 becomes disabled.

...(Status shown in timing chart Figure 3 ■) When DMA occurs here, the output B5 of the Eva chip 101 is first output.
2-0, R/W, M/D0 signals are in a state indicating DMA transfer. As a result, the output DMA of decoder ■102, C
Y becomes active "L"'. This allows NANDl
Since one of the inputs of 04 becomes “L++”, FAC
8AC8 signal''.

As a result, the F/W memory 105 becomes disabled, and the buffer 111 becomes enabled.

This enables DMA transfer.

・・・・・・(Status shown in Timing Chart Figure 3 ■) At this time, the direction of the buffer ■11 is DM
It is determined by the type of A transfer (memory→I10, ■10→memory, etc.) and the mapping state.

Conversely, when DMA transfer is completed, BS 2-0, R/W
Since the M/IO signal is in an output state other than DMA transfer, the output signal DMACY of the decoder 102 becomes inactive "H", thereby causing the FAC8AC8 signal +
It becomes +. Therefore, the F/W memory 105 becomes enabled again, and the buffer 111 becomes disabled, returning to the supervisor interrupt processing state.

(Status shown in timing chart 3) Next, a $2 embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an IE according to a second embodiment of the present invention.

In Figure 2, 201 is an evaluation chip installed inside IE, and 202 is a DMA indicating that DMA transfer is occurring.
NAND, 20, which generates the F'ACS signal for determining whether to enable or disable the F/W memory and buffer ■ from the AK signal and the DBGPRC3 signal.
3 is DBR/ which controls the direction of the data bus buffer.
A decoder that generates the W signal; 204 is a F/W memory that the Eva chip accesses during supervisor interrupt processing;
205 indicates the mapping state of the user program area; -c mapping memory for switching between emulation memory and user memory; 206 emulation memory inside IE; 207 address bus buffer;
8 is the user memory of the user system, 209 is the user I of the user system, and 210 is the data bus buffer (
(hereinafter referred to as buffer ■).

Here, the operation of the IE of this patent will be explained as follows.

First, when no supervisor interrupt occurs, D
The BGPRC8 signal is inactive "'L'M:" and the F'AC8 signal is H', so the F/W memory 2
04 is in a disabled state.

If a supervisor interrupt occurs here, the DBGPR
Since the C8 signal becomes active H° and the FAC8 signal becomes L, the F/W memory 204 is enabled.Furthermore, the buffer 2)0 is disabled.

... (Status shown in timing chart Figure 4 ■) When DMA occurs here, first the output D of the Eva chip 201 is
The MAAK signal becomes active "'L" and enters a state indicating DMA transfer. As a result, one of the inputs of the NAND 202 becomes "L", so the FAC3 signal becomes "H". As a result, the F/W memory 204 becomes disabled and the buffer 210 becomes enabled. This enables DMA transfer.

・・・・・・(Timing Chart 1 - Condition shown in Figure 4 ■)
At this time, the direction of the buffer ■210 is D.
Type of MA transfer (memory → I10, ■/○ → memory, etc.)
and mapping status.

Conversely, once the DMA transfer is completed, the DMAAK signal becomes inactive ``H'', which causes the TAC8AC8L
Therefore, the F/W memory 204 becomes enabled again, and the buffer 210 becomes disabled, returning to the supervisor interrupt processing state.

... (Status shown in Figure 4 ■ of the timing chart) [
[Effects of the Invention] As described above, the IE of the present invention includes a microcomputer with a built-in DMA function, a signal indicating that a supervisor interrupt is being processed, and a circuit that detects that a DMA transfer has occurred during the supervisor interrupt processing. And, by having a means for interrupting supervisor interrupt processing by the detection signal, a circuit for detecting the end of DMA transfer, and a means for performing supervisor interrupt processing again, it is possible to realize DMA transfer during supervisor interrupt processing. has.

[Brief explanation of drawings]

FIG. 1 shows a first embodiment of the IE of the present invention. 101... Eva chip, 102... Decoder ■, 103... Lever-3f ■, 104...
...NAND. 105...F/W memory, 106...
Mapping memory, 107...Emulation memory, 108...Address buffer, 10
9...User memory, 110...User I10.111...Data bus buffer. Further, FIG. 2 shows a second embodiment of the IE of the present invention. 201...Ebachit7', 202...N
AND, 203... Decoder, 204...
... F/W memory, 205 ... Mapping memory, 206 ... Emulation memory, 207
... Address buffer, 208 ... User memory, 209 ... User I10.210
...Data bus buffer. Note that FIGS. 3 and 4 are timing charts of the first and second embodiments, respectively. Agent Patent Attorney Susumu Hara 1 No. 3 Glue 4 T, h Shibu Chart JL Fu Otsu Isu 1 A 7 1/ , Mu 4

Claims (1)

[Claims] A microcomputer with a built-in DMA function, a signal indicating that a supervisor interrupt is being processed, a circuit for detecting that a DMA transfer has occurred during the supervisor interrupt processing, and means for interrupting the supervisor interrupt processing based on the detection signal. An in-circuit emulator characterized in that it has a circuit for detecting the end of DMA transfer and means 2 for performing supervisor interrupt processing again.