KR20010064594A - Method for contorlling duplication of processor - Google Patents

Abstract

PURPOSE: The method for controlling the duplex of the processor is provided to process the memory control and the alarm generation efficiently and stably when the memory is controlled and the alarm is generated in the duplex system. CONSTITUTION: The signal requesting the refresh of a memory is created in the idle state. The writing operation is performed on the memory of an active board and the signal for updating the memory of a stand-by mode is created. A CPU creates the request signal for accessing an own memory of the CPU. The request signal for reading the memory of the stand-by board from the active board is created. When the signals are created, the related control operation is performed.

Description

How to Control Redundancy of Processors {METHOD FOR CONTORLLING DUPLICATION OF PROCESSOR}

The present invention relates to a redundancy control method of a processor board, and more particularly, to a memory control and an efficient method of processing an alarm in a redundancy system.

In general, in a synchronous write (Concurrent Write) scheme, as shown in FIG. 1, when the memory 112 of the active side 110 is updated, the same data is also updated in the memory 122 of the standby side 120. to be. As such, the main memory between active / standby maintains concurrency, and thus, when an active failure occurs, the standby can continue to perform the operation performed by the active.

As such, since redundancy is a structure for increasing the reliability and stability of the system, how efficiently and stably the controller for controlling redundancy is very important in the synchronous write redundancy structure.

Accordingly, an object of the present invention is to provide a method for efficiently and stably processing a memory control and an alarm in a redundant system.

According to an aspect of the present invention, there is provided a first process of generating a signal for requesting refresh of a memory in an idle state, a write operation is performed in a memory of the active board, and a signal for updating the memory of the standby board. A second process of generating a signal; a third process of generating a signal for the CPU to access its memory; a fourth process of generating a request signal for reading a memory of the standby board from the active board; When the signals are generated, a fifth process of performing a corresponding control operation is performed.

1 is a redundant configuration diagram of a conventional simultaneous write method.

2 is a block diagram of a redundant controller according to the present invention.

3 is a state diagram for controlling a DRAM according to the present invention;

4 is a refresh timing diagram of a DRAM according to the present invention;

Fig. 5 is a write timing diagram of a DRAM in the standby state according to the present invention.

6 is a DRAM access timing diagram in accordance with the present invention.

7 is a read timing diagram of a standby DRAM in an operating state according to the present invention.

8 shows a redundant connection according to the invention.

9 illustrates a redundancy start / end signal according to the present invention.

10 is a busy cycle in a duplex operation according to the present invention;

11 illustrates a delay reset in accordance with the present invention.

12 is a block diagram of an alarm processing unit according to the present invention.

13 is a circuit diagram of a cleat remover according to the present invention.

14 is a circuit diagram of a level detector according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a redundant controller for implementing a synchronous write method according to the present invention, and includes a DRAM controller 210 and an alarm processor 220.

Referring to FIG. 2, the DRAM controller 210 allocates bus usage rights for DRAM access as a controller for refresh and DRAM access, and generates DRAM control signals by controlling a redundant bus and a local bus. The DRAM controller 210 generates a DRAM request signal as described below to access the DRAM.

First, a local request signal (local_req) is a request signal for a local CPU to access its DRAM. The dual_req signal is a request signal for updating the standby DRAM when the active DRAM is updated, the conrd_req signal is a request signal for reading the standby DRAM in the active state, and the ref_req signal is a request signal for refreshing the DRAM. to be.

The DRAM controller 210 sets priority among the request signals so that the four request signals can access the DRAM without colliding with each other, and performs the state processing as shown in FIG. 3.

First, the refresh cycle is as follows.

Referring to FIGS. 3 and 4, when the REF_REQ signal is asserted in the IDLE state as shown in the signal 410 of FIG. 4, the state is changed to REF_STATE0 at the falling edge of the next system clock. Once the state has reached REF_STATE0 (310), it continues to change from REF_STATE1 (311) to REF_STATE2 (312) to REF_STATE3 (313) for each falling edge of the system clock, such as signal (400), and back to the IDLE state. . At this time, a CAS signal such as the (440) signal becomes an active low state while the states are REF_STATE1 311 and REF_STATE2 312, and a RAS signal such as the (430) signal is an active low state while the state is REF_STATE2 312. So, DRAM can be refreshed by CAS-before-RAS method. Here, the REF_REQ signal is asserted every 15.6us, and the state is maintained until it is changed to 'REF_STATE0' in the IDLE state.

Next, the dual cycle is as follows.

First, the write operation of the active side is performed. In standby, the dual_req signal is asserted, and the same contents as the active are written to the standby DRAM. Also, when the active reads the standby DRAM, the dual_req signal is asserted in standby.

3 and 5, when the ref_req signal is high in the IDLE state and the dual_req signal is asserted, the state is changed to DUAL_STATE0 320 at the falling edge of the next system clock. Once the status changes to DUAL_STATE0 (320) and again, the status continues on every falling edge of the system clock, such as signal (400). DUAL_STATE1 (321)-> DUAL_STATE2 (322)-> DUAL_STATE3 (323)-> DUAL_STATE4 (324) It changes to and returns to the IDLE state again. At this time, while the state is DUAL_STATE1 (321), DUAL_STATE2 (322), DUAL_STATE3 (323), and DUAL_STATE4 (324), the RAS signal such as the (530) signal becomes an active low state. The AMUX signal for controlling the address mux is in an active low state while the states are DUAL_STATE2 322, DUAL_STATE3 323, and DUAL_STATE4 324 as shown in the signal 540. The CAS, XLDACK, and XTERM signals become active low while the DUAL_STATE3 (323) and DUAL_STATE4 (324) states are the same as the (550), (560), and (570) signals, respectively.

Next, the local cycle is as follows.

3 and 6, when the local CPU wishes to access the DRAM, the LCOAL_REQ signal is asserted like the 610 signal. If ref_req and dual_req are high in the IDLE state and the LOCAL_REQ signal is asserted, the state changes to LOCAL_STATE0 on the falling edge of the next system clock. Once the status is LOCAL_STATE0, the status continues on each polling edge of the system clock, changing to LOCAL_STATE1-> LOCAL_STATE2-> LOCAL_STATE3-> LOCAL_STATE4 as shown by the signal (620) and back to IDLE. At this time, while the state is LOCAL_STATE1, LOCAL_STATE2, LOCAL_STATE3, and LOCAL_STATE4, the RAS signal such as the 630 signal becomes an active low state. The AMUX signal becomes an active low state while the states are LOCAL_STATE2, LOCAL_STATE3, and LOCAL_STATE4, as with the signal (640). The CAS signal and the DSACKx signal are in the active low state while the states are LOCAL_STATE3 and LOCAL_STATE4, as with the signals 650 and 660, respectively.

Next, CONRD CYCLE is as follows.

3 and 7, the CONRD_REQ signal is asserted like the 710 signal to read the DRAM contents of the standby in the active state. At this time, in standby, the DUAL_REQ signal is asserted to perform a dual cycle, and in the active state, the state is changed from IDLE to WAIT_STATE 340. In WAIT_STATE, the state is maintained until the acknowledgment signal XTERM comes from standby. When the XTREM signal such as signal 730 comes from standby, the state changes to CONRD_END0 341 at the falling edge of the next system clock. Once the state changes to CONRD_END0 341, the state changes to CONRD_END1 342 for each falling edge of the next system clock, as shown at 720, and back to the IDLE state. At this time, while the states are CONRD_END0 341 and CONRD_END1 342, the DSACKx signal is asserted to be an active low state like the signal 740 and the bus cycle is terminated.

8 shows a redundant connection according to the present invention.

Referring to FIG. 8, in order to perform simultaneous write and standby read operations from the active board 110 to the standby board 120, a redundant connection must first be made between the two boards 110 and 120. Whether or not the redundant connection is made is checked by checking the con and ot_con signals, and if both signals are low, it is determined that the redundant connection is made and the duplication operation is performed.

9 shows a redundancy start / end signal according to the present invention.

9 and 10, when the active board 110 writes its own DRAM 111 under a redundant connection state, the LOCAL_REQ signal is asserted like the (1020) signal, and the state is changed from IDLE to LOCAL_STATE0. When changed, the busy_tx signal is asserted low as signal (1010). In the standby board 120, when the busy_rx signal is asserted low, the dual_req signal is asserted and the dual_cycle starts. On the other hand, at the end of the dual_cycle, the standby board 120 asserts the xldack signal to the low state as shown by the signal 103, and the active board 110 clears the in_xldack signal to the high state. Here, in the active board 110 under the redundant connection state, the next bus cycle cannot proceed until the busy_tx signal is cleared to the high state. That is, the active board 110 may proceed to the next bus cycle only when receiving the recognition signal from the standby board 120 that the update of the DRAM is completed.

On the other hand, the alarm processing unit 220 generates an interrupt signal of IRQ7 such as the signal 1110 shown in FIG. 11 to the CPU when an abnormality has occurred in the board due to a push button reset or a power failure, etc. After 500ms), SYSFAIL is asserted and reset to CPU. Here, when an interrupt of IRQ7 occurs, the CPU must die after writing the data (PC value and SP value) that needs to be redundantly transferred to the simultaneous write area before being reset. The SYSFAIL signal enters REM_SYSFAIL on the opposing board and generates an IRQ7 interrupt to the opposing CPU. When the IRQ7 interrupt generated by REM_SYSFAIL occurs, the standby board 120 takes the PC value and the SP value from the active board 110 and continues the operation performed until the active board 110 dies.

At this time, a source capable of generating an IRQ 7 interrupt to the CPU includes a mounting signal of the counterpart board, an XINTO signal that generates an interrupt by software of the counterpart board, and an ABORT signal by the ABORT switch.

These alarm signals are transmitted to the click canceller 1210, the level detector 1220 and the interrupt controller 1230 as shown in FIG. 12.

The clinch remover 1210 includes D flip-flops 1310, 1320, and 1330 and an OR gate 1340 as shown in FIG. 13.

The level detector 1220 includes a D flip-flop 1410 and an exclusive noar gate 1420 as shown in FIG. 14.

When the level of the signal from the level detector 1220 is detected, the interrupt controller 1230 generates an IRQ7 interrupt to the CPU, and stores the state of each source in a register so that the CPU knows which source the interrupt was caused by. Can be.

As described above, the present invention can efficiently handle memory control and alarm occurrence in a redundant system.

Claims (5)

In the redundancy control method through memory sharing in a redundancy system having at least an active board and a standby board, A first process of generating a signal requiring a refresh of the memory in an idle state; Performing a write operation on a memory of the active board, and generating a signal for updating a memory of the standby board; A third process of generating a signal required by the CPU to access its memory, Generating a request signal for reading a memory of the standby board from the active board; And when the signals are generated, a fifth process of performing a corresponding control operation. The method of claim 1, wherein the fifth process, And refreshing the memory according to the refresh request signal of the memory generated in the first process. The method of claim 1, wherein the fifth process, And updating the memory of the standby board when the memory of the active board is updated according to the memory update request signal generated in the second process. The method of claim 1, wherein the fifth process, And accessing its own memory according to the memory access request signal generated in the third step. The method of claim 1, wherein the fifth process, And reading the memory of the standby board from the active board according to the memory read request signal generated in the fourth process.