KR100817316B1 - Portable device and Method for controlling refresh of shared memory - Google Patents

Abstract

Disclosed are a refresh control method of a portable device and a shared memory. A memory device according to an embodiment of the present invention determines a refresh mode of each partition by a combination of n ports and n signal signals input from a processor through corresponding ports to couple to n processors, respectively. It may include a refresh controller to perform the refresh. According to the present invention, a refresh operation can be performed even when a plurality of processors share one memory, thereby enabling data preservation.

Low power mode, self refresh, refresh, memory, share

Description

Portable device and method for controlling refresh of shared memory

1 is a block diagram of an SDRAM according to the prior art for refreshing.

FIG. 2 is a detailed circuit diagram of the control unit shown in FIG. 1. FIG.

3 is a detailed circuit diagram of the cell fresh mode decoder shown in FIG. 2;

4 is a view showing an operation timing diagram in FIG. 1;

5 illustrates a command table transmitted and received between a memory and a processor.

6 is a diagram illustrating a combination structure of a memory and a processor according to an exemplary embodiment of the present invention.

7 is a block diagram of a refresh mode controller according to an embodiment of the present invention.

The present invention relates to shared memory, and more particularly, to a portable device and a low power mode control method of the shared memory.

In general, portable devices each have a plurality of processors for performing a predetermined function. Each processor is coupled with a memory for storing data for operations, data for processing, processed data, and the like.

As is well known, in the case of a memory cell storing data in a volatile memory device, there is a disadvantage in that data stored in the volatile memory device cannot be stored for a predetermined time or more.

To compensate for this limitation, the system performs a refresh operation that allows the memory device to restore data again at certain times.

Such a refresh operation includes an auto refresh that performs a refresh operation during a normal operation of the system and a self refresh that performs a refresh operation when the system does not operate for a long time.

In this case, when the system is not operated for a long time, the memory device maintains a minimum operation to reduce power consumption. In this state, a refresh operation must be performed in order for the memory to accurately maintain data. do. The refresh operation performed at this time is called self refresh.

That is, self refresh means that a volatile memory device such as a DRAM performs internal refresh at a predetermined period (ie, a basic period) in order to maintain data stored in a memory cell in a standby state.

The refresh operation is basically the same as the row active and precharge operations that are normal operations. That is, a series of processes are performed to amplify the data stored in the memory cell with a sense amplifier and store the data in the memory cell again.

Meanwhile, in the case of the self refresh operation, since the refresh operation must be performed at a predetermined time without a command from the outside of the memory device, the self refresh operation is performed independently in the chip.

That is, even if the low active command is not applied from the outside, the low active operation should be performed and the precharge operation should be performed successively.

However, the conventional refresh control method for a memory device is a method proposed to be suitable for a single port memory, which is not suitable for a shared memory system in which a plurality of processors share one memory.

Accordingly, the present invention has been made to solve the above-described problem, and provides a refresh control method for a portable device and a shared memory that enable data preservation by allowing a refresh operation to be performed even when a plurality of processors share a single memory. It is.

Another object of the present invention is to provide a portable device capable of performing a refresh operation for preserving data stored in a common area shared by a plurality of processors among a plurality of storage areas divided in a memory, and a refresh control method of a shared memory.

It is still another object of the present invention to provide a portable device and a refresh control method of a shared memory capable of maximizing the utilization efficiency of the shared memory by dividing a plurality of storage areas of the memory and allocating a specific partition area for each processor. .

It is still another object of the present invention to provide a portable device and a method of controlling refresh of shared memory, which can minimize power consumption by allowing the memory to operate in the self refresh mode as a whole.

Other objects of the present invention will become more apparent through the preferred embodiments described below.

According to an aspect of the present invention to achieve the above object, there is provided a memory device and / or a portable terminal including the memory device for determining and performing a refresh mode for each partition of the storage area.

A memory device according to an exemplary embodiment of the present invention may include n ports for coupling to n (two or more natural numbers) processors, respectively; And a refresh controller for performing a refresh by determining a refresh mode of each partition region by a combination of command signals input from the processor through a corresponding port, wherein the refresh mode is a self refresh mode. Or in auto refresh mode. Here, the storage area of the memory device is divided into k (natural numbers) partitions, and m (natural numbers less than k) partitions are allocated to dedicated areas of each of the n processors, and j (natural numbers of kms) The partition area may be allocated to a common area accessible by the n processors.

Each refresh area may be determined by a combination of command signals input from a corresponding processor, and the refresh mode may be determined by a combination of command signals input from one processor.

Each refresh area may be determined by a combination of command signals input from a corresponding processor, and the refresh mode may be determined by a combination of command signals input from a most recently accessed processor.

The refresh controller may include n command interpreters corresponding to each of the combined processors; And determining a refresh mode for the m dedicated areas in correspondence with the n refresh control signals input from the n command analyzing units, and using the refresh control signal by a command signal input from an arbitrary processor. And a region manager for determining a refresh mode of the refresh control signal, wherein the refresh control signal is a refresh enter signal or a refresh exit signal. The command analyzer may interpret the chip select signal CS, the write enable signal WE, the row address strobe signal RAS, and the column address strobe signal CAS input from a corresponding processor. A command decoder which determines whether the command is a refresh command and outputs a corresponding result value; A CKE level detector generating and outputting information on whether the clock enable signal CKE is inverted from a corresponding processor; And a command determiner configured to generate and output the refresh ingress signal when the result value indicates that the refresh command is generated and the inversion information indicates that the clock enable signal is inverted from a first value to a second value. have.

The command determiner may generate and output the refresh exit signal when the inversion information indicates that the clock enable signal is inverted from a second value to a first value.

According to another preferred embodiment of the present invention, a portable terminal includes: n (two or more natural numbers) processors; And a memory device coupled to each of the n processors. The memory device may include: n ports for coupling to the n processors, respectively; And a refresh controller for performing a refresh by determining a refresh mode of each partition region by a combination of command signals input from the processor through a corresponding port, wherein the refresh mode is a self refresh mode or a refresh mode. And an auto refresh mode, wherein the storage area of the memory device is divided into k (natural numbers) partitions, and m (natural numbers less than k) partitions are dedicated areas of each of the n processors. J partitions may be allocated to a common area accessible by the n processors.

Each refresh area may be determined by a combination of command signals input from a corresponding processor, and the refresh mode may be determined by a combination of command signals input from one processor.

Each refresh area may be determined by a combination of command signals input from a corresponding processor, and the refresh mode may be determined by a combination of command signals input from a most recently accessed processor.

The refresh controller may include n command interpreters corresponding to each of the combined processors; And determining a refresh mode for the m dedicated areas in correspondence with the n refresh control signals input from the n command analyzing units, and using the refresh control signal by a command signal input from an arbitrary processor. And a region manager for determining a refresh mode of the refresh control signal, wherein the refresh control signal is a refresh enter signal or a refresh exit signal. The command analyzer may interpret the chip select signal CS, the write enable signal WE, the row address strobe signal RAS, and the column address strobe signal CAS input from a corresponding processor. A command decoder which determines whether the command is a refresh command and outputs a corresponding result value; A CKE level detector generating and outputting information on whether the clock enable signal CKE is inverted from a corresponding processor; And a command determiner configured to generate and output the refresh ingress signal when the result value indicates that the refresh command is generated and the inversion information indicates that the clock enable signal is inverted from a first value to a second value. have.

The command determiner may generate and output a refresh exit signal when the clock enable signal is inverted from a second value to a first value.

According to another aspect of the present invention to achieve the above object, a refresh control method for performing a refresh operation by determining the refresh mode of each partition of the shared memory and / or a recording medium on which a program for performing the method is recorded Is provided.

In a refresh control method according to an exemplary embodiment, a refresh mode for each partition is determined by a combination of command signals input from an arbitrary processor, and a common region is determined by a combination of command signals input from a processor having access authority. The refresh mode is determined.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and in describing the present invention with reference to the accompanying drawings, the same or corresponding elements are denoted by the same reference numerals, and duplicated thereto. The description will be omitted. In addition, the ordinal numbers (for example, first, second, etc.) used for the description of the present invention herein are only to distinguish the same or similar individuals, it is obvious that the present invention is not limited thereto.

1 is a block diagram of a conventional SDRAM for refreshing, FIG. 2 is a detailed circuit diagram of the control unit shown in FIG. 1, FIG. 3 is a detailed circuit diagram of the cell refresh mode decoder shown in FIG. 2, and FIG. 4. 1 is a diagram illustrating an operation timing diagram in FIG. 1, and FIG. 5 is a diagram illustrating a command table transmitted and received between a memory and a processor.

As shown in FIG. 1, the auto refresh circuit according to the related art includes a low-address input buffer (BF1), a controller for interpreting commands input from the outside to perform self refresh and auto refresh operations, and all words in a memory array. Auto refresh counter 2 that can access lines sequentially, self refresh counter 3 that generates addresses of all word lines to be refreshed with its own timer in self-refresh mode, the auto refresh counter 2 and self It consists of the row decoder 4 which decodes the address which generate | occur | produces in the refresh counter 3, and an external address.

The control section analyzes the auto refresh command to generate the sequential address increment flag signal REF of the auto refresh counter 2 (see FIG. 2), and interprets the self refresh command to interpret the self refresh counter 3. And a self-refresh mode decoder (see Fig. 3) which produces a flag signal SREF of sequential address increments.

Here, as shown in FIG. 2, the auto refresh mode decoder may include inverters INV21 and INV22 that sequentially invert the external clock signal ICLK and an inverter that inverts the inverted signal of the external clock signal ICLK. The NOA gate NOR21 combining the INV23, the external command signals ISCB, IRASB, ICASB, and IWE, and the sequential inverted signal of the external clock signal ICLK and its inverted signal to control the The N flip-flop DFF21 whose output of NOR21 is connected to the input terminal, the NAND gate ND21 which sums the output of the D flip-flop DFF21 and the inverted signal of the external clock signal ICLK, and the NAND gate ( Inverter INV24 for inverting the output of ND21.

In addition, the self refresh mode decoder inputs an output signal FSB of the self refresh exit circuit EX and an output signal FRB of the self refresh entry circuit EN, as shown in FIG. 3. And an RS flip-flop RSFF31 which outputs the address increment flag signal SREF to the self refresh counter 3.

Here, the self refresh exit circuit EX includes a delay unit DE31 for delaying the control clock signal ICKE and a signal SET having a low value at all times when the output of the delay unit DE31 and power are applied. Is composed of a NOR gate NOR31 for outputting the output signal FSB by combining the inverted signals.

In addition, the self-refresh entry circuit EN is controlled by inverters INV31 and INV32 that sequentially invert the external clock signal ICLK and the outputs of the inverters INV31 and INV32 so that the control clock signal ICKE is controlled. The first D flip-flop DFF31 applied to the input terminal and the second D flip-flop DFF32 to which the output of the flip-flop DFF31 is applied to the input terminal, and the internal clock signal ICKI of the second flip-flop DFF32. Delay delay DE32 for delaying?), Inverters INV33 and INV34 for sequentially inverting the output of the delayer DE32, and outputs and inverters INV33 and INV34 of the second D flip-flop DFF32; The NOA gate NO32 outputs the output clock signal CKD3 by combining the outputs of the output signals, the inverters INV35 and INV36 that sequentially invert the external clock signal ICLK, and the external clock signal ICLK. Inverter INV37 for inverting the signal, Noah gate NOR33 for combining external command signals ISCB, IRASB, ICASB, and IWE, and others. Controlled by the sequentially inverted signal of the clock signal ICLK and its inverted signal, a D flip-flop DFF33 having an output of a Noah gate NOR33 connected to an input terminal, an output of the D flip-flop DFF33, and an external clock. A NAND gate ND31 that sums sequentially inverted signals of the signal ICLK, an inverter INV38 that inverts the output of the NAND gate ND31, and a delay unit DE33 that delays the output of the inverter INV38. And a NAND gate ND32 that combines the output CKD3 of the NOR gate NOR32 and the output SAR of the delay device DE33.

4 and 5 illustrate a timing diagram for entry into the self refresh mode, and a command table transmitted and received between the memory and the processor.

As shown in Figures 4 and 5, when a combination of external command signals from the combined processor indicates entry or exit into the self refresh mode, the memory is operated in the corresponding mode of operation.

That is, the row and column address strobe signals RAS and CAS and the chip select signal CS of the external command signals are low, and the write enable signal WE is high ( High), the memory device performs an operation in the refresh mode.

In this case, whether to operate in the self refresh mode or the auto refresh mode is determined by the clock enable signal CKE. That is, the memory is operated in the auto refresh mode when the clock enable signal CKE is kept high and enters the self refresh mode when the clock enable signal CKE is inverted from the high state to the low state. entry). In addition, when the clock enable signal CKE is inverted from a low state to a high state, the clock enable signal CKE is exited from the self refresh mode.

As described above, the memory performs operations in different refresh modes according to a combination of external command signals input from an external system (e.g., a combined processor) to preserve the recorded data.

However, the above-described prior art is merely a refresh mode control method suitable for a single port memory that is independently coupled to only one processor.

Therefore, there is a need for a refresh control method for a memory shared by a plurality of processors.

6 is a diagram illustrating a combination structure of a memory and a processor according to an exemplary embodiment of the present invention.

As illustrated in FIG. 6, the memory device 630 may include two ports, and may be coupled to the main processor 610 and the application processor 620 through respective ports. Of course, one or more application processors may be further coupled to the memory device 630, and the memory device 630 may include more ports. This is to solve the problem that the size of the portable device increases, the manufacturing cost increases, and the like, when each processor independently includes one or more memories as in the related art.

Here, the main processor 610 may perform a control function for the basic functions of the portable terminal (eg, a phone call function in the case of a mobile communication terminal) and the application processors 620 provided therein. In addition, the application processor 620 may perform a function preset by the control of the main processor 610.

Although not shown, a host interface may be further provided between the main processor 610 and the application processor 620 for transmitting and receiving control commands, processing responses, and the like. Of course, the host interface may be omitted if the control command, the processing response, etc. are configured to be written by one processor and read by the other processor in the preset area of the memory device 630.

The storage area of the memory device 630 may be divided into, for example, four banks BANK 0 to 3, and an accessible processor for each bank may be preset.

As illustrated in FIG. 6, when the storage area of the memory is divided into four banks BANK 0 to 3, one bank may be accessed through the first port as a dedicated area for the main processor, and two banks may be accessed. The bank may be accessed through the second port as a dedicated area for the application processor, and the other bank may be set as a common area accessible by the main processor and the application processor through the first port and the second port, respectively. .

A plurality of processors may not be connected to a common area at the same time, and one processor may be connected only when another processor is not connected to the common area. To this end, the first processor (that is, either one of the main processor 610 and the application processor 620) transmits the information to the second processor (that is, the main processor when the connection is terminated and / or when the connection is terminated). The other of the processor 610 and the application processor 620).

The connection state information of the common area is transmitted and received through the host interface, records a value corresponding to a predetermined register inside the processor, or uses a semaphore function using the preset area inside the memory device 630. It can be provided by a variety of ways. Of course, it is obvious that all methods for transferring information on whether to access the common area to other processors may be used without limitation.

As described above, when the storage area of the memory device 620 is divided into a plurality of regions, and if any partition is designated as a dedicated area allocated to each processor, the memory device 620 is not connected by a corresponding processor. ) May enter a self-refresh mode for the dedicated area and perform a data preservation operation. However, in the common area, it is not preferable to enter the self refresh mode and perform a data preservation operation only because one processor is not connected. This is because other processors can connect and are not desirable in terms of power consumption suppression.

Hereinafter, a refresh control method for each partition of the shared memory will be described in detail with reference to FIG. 7.

7 is a block diagram of a refresh mode controller according to an embodiment of the present invention.

Referring to FIG. 7, the illustrated refresh mode controller 710 is included in a memory device 630 shared by a plurality of processors (eg, 610, 620, etc.), and configured to be coupled to a plurality of processors, respectively. Enter / exit self-refresh mode using external command signals connected to respective ports (eg, first port, second port) of the device 630 and input from the corresponding processor, respectively. Determine whether or not.

Referring to FIG. 7, the refresh mode controller 710 may include a first command decoder 720a, a second command decoder 720b, a first CKE level detector 725a, a second CKE level detector 725b, and a first command decoder 720a. The first command determining unit 730a, the second command determining unit 730b, the first area managing unit 733, the common area managing unit determining unit 735, and the second area managing unit 737 are included.

As shown, the command decoders 720a and b, the CKE level detectors 725a and b, and the command determiners 730a and b receive and interpret each signal from each processor to output a result value. Each port is provided. FIG. 7 illustrates a case in which two processors are coupled to the memory device 630, but there may be n (natural number of two or more) processors combined, and in this case, the corresponding components may be formed as n pairs. .

The first command decoder 720a may be a clock signal from a correspondingly coupled processor (for example, the main processor 610 or the application processor 620 of FIG. 6, hereinafter referred to as a 'first processor'). And a write enable signal WE, a row and column address strobe signals RAS and CAS are inputted, and a combination of these commands for a refresh mode (hereinafter referred to as a 'refresh command'). Or not).

The first command decoder 720a has the write enable signal WE high and the chip select signal CS, the row and column address strobe signals RAS and CAS are low. In this case, it may be determined that the refresh command is performed.

If it is determined that the first command decoder 720a is a refresh command by signals input from the first processor, the first command decoder 720a outputs a corresponding refresh determination signal to the first command determination unit 730a.

The first CKE level detector 725a records the clock enable signal CKE input from the first processor, and immediately before the CKE value CKE-1 (see FIG. 5) and the current CKE value CKE (FIG. 5). When the CKE value is inverted from high to low, a state signal (ie, a low state signal) is output to the first command determination unit 730a. In addition, the first CKE level detecting unit 725a records the clock enable signal CKE input from the first processor, and immediately before the CKE value CKE-1 (see FIG. 5) and the current CKE value CKE, 5, when the CKE value is inverted from low to high, a state signal (that is, a high state signal) is output to the first command determination unit 730a.

As another embodiment, the first CKE level detector 725a may be implemented to store only information on the CKE (ie, state information of whether it is high or low). In this case, the first CKE level detection unit 725a may store the previous CKE value and the current CKE value. If the first CKE level detection unit 725a only stores state information on the CKE and does not output a status signal to the first command determination unit 730a, the first command determination unit 730a detects the first CKE level. The information stored in the unit 725a may be used to determine whether the CKE value is changed.

The first command determiner 730a receives the refresh determination signal input from the first command decoder 720a and the first provision information from the first CKE level detector 725a (that is, the first CKE level detector 725a). It is determined whether to enter the self-refresh mode corresponding to the first processor using the state signal inputted from the state signal or the state information stored in the first CKE level detection unit 725a.

If the CKE value is maintained high by the first provision information from the first CKE level detector 725a, the first command determination unit 730a may enter the self refresh mode corresponding to the first processor. Do not decide. This is because it is an auto refresh command.

However, if the CKE value is inverted from the high state to the low state by the first provision information from the first CKE level detection unit 725a, the first command determination unit 730a enters the self refresh mode corresponding to the first processor. The first SR (self refresh) entry signal is determined and output to the first area manager 733 and the common area manager 735. The first command determination unit 730a may be implemented by, for example, a latch circuit. The first area manager 733 performs a self refresh operation on the bank BANK 0 according to the first SR entry signal input from the first command determiner 730a.

After the first command determination unit 730a determines to enter the self-refresh mode corresponding to the first processor, a new state change of the CKE value from the first CKE level detection unit 725a (that is, inversion from low to high). When the information about is provided, it is determined to exit from the self-refresh mode, and the first SR exit signal is output to the first area manager 733 and the common area manager 735. In this case, the command information interpreted by the first command decoder 720a may be ignored. The first area manager 733 terminates the self refresh operation on the bank BANK 0 according to the first SR exit signal input from the first command determiner 730a.

The functions of the second command decoder 720b, the second CKE level detector 725b, and the second command determiner 730b shown in the drawing are the first command decoder 720a and the first CKE level detector 725a. And only the difference between interpreting the external command signals input from the processor different from the first command determination unit 730a, and other matters are the same, so description thereof will be omitted. However, the signal output for the convenience of understanding is referred to as the second provision information, the second SR entry signal, and the second SR exit signal. The second command determination unit 730b may output the second SR entry signal or the second SR exit signal to the common area manager 735 and the second area manager 737. The second area manager 737 performs the self refresh operation or the self refresh operation on the banks BANK 2 and 3 according to the second SR entry signal or the second SR exit signal input from the second command determination unit 730b. To exit.

In performing the refresh operation on the common area, the common area manager 735 performs a refresh mode by an external command signal input through a fixed port which is fixed in advance, or an external command input through a port that is fluidly changed. There may be a method of performing a refresh mode by a signal.

In the former case, only external command signals input from either processor will determine the refresh mode for the common area (e.g. BANK 1). In this case, the output of only the first command determination unit 730a or the second command determination unit 730b may be set in advance so as to be input to the common area manager 735.

In the latter case, the refresh mode may be performed by an external command signal input from a processor having access to the common area. Each processor may provide connection status information about the common area to the memory device 630 or record a preset value in a preset area inside the memory device 630 so as to identify who has a processor. Various methods are available.

For example, if there is a processor currently accessed in the common area, the auto refresh mode by the external command signal input through the corresponding port will be performed. However, if no processor is currently accessed in the common area, a refresh mode (ie, auto refresh mode or self refresh mode) by an external command signal input from the most recently accessed processor will be performed. By this process, the common area may enter the refresh mode together with the bank 0 or the refresh mode together with the banks 2 and 3, depending on which processor is currently accessed or most recently accessed.

By the above-described process, the preservation operation of the data recorded in all the partitions included in the storage area 713 can be performed with minimum power consumption by suppressing unnecessary repetition of refreshing the common area.

So far, in describing the refresh mode control method of the memory according to the present invention, the CKE value is inverted from high to low by the signal analysis inputted from each of the combined processors, and the write enable signal WE ) Is high, and the chip select signal CS, the row and column address strobe signals RAS and CAS are low, and the self refresh mode is applied to the corresponding bank. Explained. In addition, the case where the CKE value is changed from low to high will be described based on the case of exiting from the self refresh mode.

However, this is merely an example of a protocol that may be used or applied for the purpose of signaling entry and exit into the self-refresh mode, which may be modified. For example, the signals such as the write enable signal WE and the column address strobe signal CAS may be made to have an inverted signal level as shown.

As described above, the method for controlling the refresh of the portable device and the shared memory according to the present invention has an effect of enabling data preservation by allowing the refresh operation to be performed even when a plurality of processors share a single memory.

In addition, the present invention has the effect that it is possible to perform a refresh operation for preserving data stored in a common area shared by a plurality of processors among a plurality of storage areas divided in a memory.

In addition, the present invention also has the effect of maximizing the utilization efficiency of the shared memory by dividing the storage area of the memory into a plurality and assigning a specific partition area to each processor.

In addition, the present invention has the effect of minimizing power consumption by allowing the memory to operate in the self-refresh mode as a whole.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (10)

In a memory device, n ports for respectively coupling to n (two or more natural numbers) processors; And A refresh controller which performs a refresh by determining a refresh mode of each partition by a combination of command signals input from the processor through a corresponding port, wherein the refresh mode is a self refresh mode or an auto refresh mode. Include in auto refresh mode, The storage area of the memory device is divided into k (natural numbers) partitions, m (natural numbers less than k) partitions are divided into dedicated areas of each of the n processors, and j (natural numbers of km) partitions. Is the n processors are allocated to an accessible common area. The method of claim 1, Each refresh area is determined by a combination of command signals input from a corresponding processor, and the refresh area is determined by a combination of command signals input from one processor. Memory device. The method of claim 1, Each refresh area is determined by a combination of command signals input from a corresponding processor, and the refresh area is determined by a combination of command signals input from a most recently accessed processor. Memory device. The method according to any one of claims 1 to 3, The refresh controller, N command interpreters corresponding to each of the combined processors; And The refresh mode for the m dedicated areas is determined according to the n refresh control signals input from the n command interpreting units, and the refresh control signal by the command signal input from an arbitrary processor is used to determine the refresh mode of the common area. An area manager for determining a refresh mode, wherein the refresh control signal is a refresh enter signal or a refresh exit signal, The command analysis unit, The chip select signal CS, the write enable signal WE, the row address strobe signal RAS, and the column address strobe signal CAS inputted from the corresponding processor are interpreted to determine whether they are refresh commands, and the corresponding results. A command decoder for outputting a value; A CKE level detector configured to generate and output information on whether the clock enable signal CKE is inverted from a corresponding processor; And And a command determiner configured to generate and output the refresh ingress signal when the result value indicates that the refresh command and the inversion information indicates that the clock enable signal is inverted from a first value to a second value. Memory device. The method of claim 4, wherein The command determining unit generates and outputs the refresh exit signal when the inversion information indicates that the clock enable signal is inverted from a second value to a first value. In a portable terminal, n (two or more natural numbers) processors; And memory devices coupled to the n processors, respectively. The memory device, N ports for coupling to the n processors, respectively; And A refresh controller which performs a refresh by determining a refresh mode of each partition by a combination of command signals input from the processor through a corresponding port, wherein the refresh mode is a self refresh mode or an auto refresh mode. In auto refresh mode, The storage area of the memory device is divided into k (natural numbers) partitions, m (natural numbers less than k) partitions are divided into dedicated areas of each of the n processors, and j (natural numbers of km) partitions. Wherein the n processors are allocated to an accessible common area. The method of claim 6, Each refresh area is determined by a combination of command signals input from a corresponding processor, and the refresh area is determined by a combination of command signals input from one processor. Handheld terminal. The method of claim 6, Each refresh area is determined by a combination of command signals input from a corresponding processor, and the refresh area is determined by a combination of command signals input from a most recently accessed processor. Portable terminal to be. The method according to any one of claims 6 to 8, The refresh controller, N command interpreters corresponding to each of the combined processors; And The refresh mode for the m dedicated areas is determined according to the n refresh control signals input from the n command interpreting units, and the refresh control signal by the command signal input from an arbitrary processor is used to determine the refresh mode of the common area. An area manager for determining a refresh mode, wherein the refresh control signal is a refresh enter signal or a refresh exit signal, The command analysis unit, The chip select signal CS, the write enable signal WE, the row address strobe signal RAS, and the column address strobe signal CAS inputted from the corresponding processor are interpreted to determine whether they are refresh commands, and the corresponding results. A command decoder for outputting a value; A CKE level detector configured to generate and output information on whether the clock enable signal CKE is inverted from a corresponding processor; And And a command determiner configured to generate and output the refresh ingress signal when the result value indicates that the refresh command and the inversion information indicates that the clock enable signal is inverted from a first value to a second value. Portable terminal to be. The method of claim 9, And the command determining unit generates and outputs the refresh exit signal when the clock enable signal is inverted from a second value to a first value.

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