KR100754358B1 - Refresh method of shared memory area and multi-port memory device performing the method - Google Patents

Abstract

A method for refreshing a shared memory area and a multi-port memory device performing the same are provided stably to refresh the shared memory area of the multi-port memory device like a shared bank and perform refresh according to the shared memory area implemented by a plurality of blocks permitting the plurality of ports concurrently to access the shared memory area. The shared memory area(202) permits access to processors through each port(220.222). An access authority register logic(240) controls access authority for permitting each processor to access the shared memory area through each port. The shared memory area is refreshed by an auto-refresh command or a self-refresh command received from the processor having the access authority when the auto-refresh command is received from the processor having the access authority or any processor has no access authority. If the self-refresh command is received from more than two processors, the shared memory area performs self-refresh according to the self-refresh command received through the predetermined port.

Description

Refresh method of shared memory area and multi-port memory device performing the method}

1 is a diagram showing a bank structure of a dual port memory of a conventional multi-port memory.

2 is a schematic diagram illustrating a multi-port memory device according to an exemplary embodiment of the present invention.

3 illustrates a structure of a general MRS command and address combination.

4 illustrates an example of a modified MRS command in accordance with one preferred embodiment of the present invention.

5 illustrates shared bank and access rights register logic in accordance with one preferred embodiment of the present invention.

6 is a diagram showing the configuration of access right register logic according to an embodiment of the present invention.

7 to 11 illustrate a method of refreshing a shared bank not divided into shared blocks according to a preferred embodiment of the present invention.

12 to 16 illustrate a method of refreshing a shared block when the shared bank is divided into a plurality of shared blocks according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

200: A-port dedicated bank

202: shared bank

204: B-Port Dedicated Bank

220: A-port

222 B-port

240: access rights register logic

242: control logic

244 flag logic

246: refresh logic

The present invention relates to a multi-port memory device, and more particularly, to a refresh method of a shared storage area and a multi-port memory device for performing the method.

In general, memory is divided into various ways according to how it is divided. For example, depending on whether the stored contents are maintained according to whether the power is applied or not, it may be classified into volatile memory and nonvolatile memory. Generally, volatile memory is random access memory (RAM), and nonvolatile memory is ROM (Read Only). Memory).

Volatile memory is divided into DRAM (Dynamic RAM) and SRAM (Static RAM) according to whether or not the cells constituting the memory should be refreshed periodically.

In addition to the classification method, single port memory and dual port memory are classified according to the number of accessible ports.

The single port memory is accessible to all cells constituting the memory through a single port, whereas a plurality of port memories except for the single port memory may be limited to cells accessible from each port.

However, recent digital processing apparatuses each have a plurality of processors for performing a predetermined function, and each processor has a memory for storing data for operation, data for processing, processed data, and the like. Combined with.

In a memory system in which a plurality of processors share one memory, a multi-port memory including a plurality of ports is more efficient than a single port memory, and thus, multi-port memory has been widely used in recent years.

1 is a diagram illustrating a bank structure of a dual port memory of a conventional multi-port memory.

Referring to FIG. 1, a conventional dual port memory shared by a plurality of processors independently coupled through each of the A-port 110 and the B-port 112 is an A-port 110, a B-port ( 112, A-port dedicated bank 100, shared bank 102, and B-port dedicated banks 104, 106. The A-port dedicated bank 100 is a bank that accesses only through the A-port 110 to read or write data among the two A and B ports, and the B-port dedicated banks 104 and 106 are the B-port ( A bank that accesses only through 112) to read or write data.

The shared bank 102 is a bank that can be accessed through the A-port 110 or the B-port 112 to read or write data.

The shared bank 102 is a bank that can be used both through the A-port 110 and the B-port 112, or the shared bank (through either the A-port 110 or the B-port 112). If 102 is used, the shared bank 102 cannot be used through other ports. That is, while the first processor (not shown) coupled to the A-port 110 accesses the shared bank 102 and reads data, the second processor coupled to the B-port 112 is shared bank. 102 is restricted from access. Therefore, the shared bank 102 cannot be used through the B-port 112 while the shared bank 102 is being used through the A-port 110.

If the shared memory is accessed through multiple ports at the same time, if the access rights for each processor are not controlled, not only a malfunction may occur, but in the worst case, cell data may be damaged. In order to solve this problem, when a plurality of processors attempt to access a single shared bank through a plurality of ports at the same time, either processor that attempts to access first has access. In this case, the processor that has been authorized to use the first bank can continue to use the shared bank, and the processor that has attempted to access the other port can use another shared bank (not shown in FIG. 1 but a plurality of shared banks). Or access it first until the access rights of the occupied shared bank have been returned.

Memory such as SDRAM periodically refreshes to preserve the recorded data. The refresh may be divided into a self refresh and an auto refresh. Self-refresh is a command to enter self-refresh by a self-refresh command input from the outside (for example, an arbitrary processor) and to continuously perform refreshing for a predetermined time until there is a separate stop command. Auto refresh is performed only once by an auto refresh command that is periodically input from the outside. Refresh is a function to amplify the charge of the cell to hold the stored data.

In this case, a dedicated bank and a shared bank generally include a memory cell array including memory cells arranged by a plurality of rows and a plurality of columns, and a word corresponding to a row address of each memory cell. A row decoder 104 for selecting and activating a word line, and a column decoder for selecting and activating a bit line corresponding to a column address of each memory cell. And a sense amplifier. The sense amplifier performs a refresh operation by amplifying the data (charge) of the cell (capacitor) transferred through the bit line and storing it back into the original cell.

Each dedicated bank may perform refresh according to a refresh command from a corresponding processor. However, since a shared bank is accessible from a plurality of processors, a method for stable refresh of a shared bank is needed.

Accordingly, the present invention has been made to solve the above-described problem, and provides a refresh method and a multi-port memory device for performing the method to ensure that the shared storage of the multi-port memory, such as a shared bank, to stably refresh. Its purpose is.

Another object of the present invention is to provide a refreshing method according to a shared storage area formed of a plurality of blocks in which multiple ports can simultaneously access a shared storage area, and a multi-port memory device performing the method.

Other objects of the present invention will become more apparent through the preferred embodiments described below.

According to an aspect of the present invention for achieving the above object, a multi-port memory device having two or more ports, comprising: at least one shared storage area accessible by a plurality of processors through each port; And access rights register logic for controlling access rights for the processor to access the shared storage through each port, wherein the shared storage is an auto refresh command from a particular processor having access rights. A multi-port memory device is provided which is configured to receive or refresh according to an auto refresh command or a self refresh command from any processor when all processors do not have access rights.

Here, the storage device may further include one or more dedicated storage areas accessible only through specific ports.

In addition, when receiving a self refresh command from two or more processors, the shared storage area may self-refresh according to a self refresh command received through a predetermined port.

The shared storage area may include one or more blocks that divide the storage area into predetermined units, and the processor may independently access one of the blocks according to an access right granted by the access right register logic. Can be.

The command for accessing and using a specific block of the shared storage area in the processor may be a command in which an address part of a preset memory command is modified, and the modified address part is address information and sharing of a shared storage block. Command information related to the use of the storage area may be included.

The command related to the use of the shared storage area may include a SET command for requesting access to a specific block of the shared storage area, and a read for checking whether access to the specific block of the shared storage area has been granted. (READ) command and a reset command for requesting release of access to a specific block of the shared storage area.

In addition, the shared storage area or the dedicated storage area may be allocated in units of banks.

According to another aspect of the present invention for achieving the above object, a multi-port memory device having two or more ports, comprising: a shared storage area including a plurality of shared blocks accessible by a plurality of processors through each port; Access rights register logic for controlling access rights for the processor to access the shared block through each port, wherein each shared block is automatically allocated from any processor having access rights according to a predetermined refresh order. A multi-port memory device is provided which receives a refresh command or refreshes according to an auto refresh command or a self refresh command from any processor when all processors do not have access rights.

Here, the access right register logic may include a refresh order register for counting the refresh order.

In addition, the storage device may further include one or more dedicated storage areas accessible only through specific ports.

According to another aspect of the present invention for achieving the above object, in the method of refreshing the shared block in a multi-port memory device comprising at least one shared storage accessible by a plurality of processors through a multi-port, a) receiving a refresh command from any processor through a corresponding port; And (b) performing refresh when the access right to the shared storage is granted and the processor has the access right or when the access right to the shared storage is not granted. Provided is a refresh method of a shared storage including a.

Here, the refresh command may be an auto refresh command or a self refresh command.

The shared storage area may include one or more blocks that divide the storage area into predetermined units, and each processor may independently access one of the blocks according to an granted access right.

In addition, the step (b) may precede the step of recognizing the shared block to turn the current refresh in the predetermined order.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, a multi-port memory device for stable refresh of a shared storage area according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In addition, for convenience of description, a multi-port according to a preferred embodiment of the present invention will be described by taking an example of a dual port having two ports, but the same may also be applied to a multi-port having three or more ports. Will be more self-explanatory.

In the following description, a storage area is a bank, which will be described as an example. However, the storage area is not necessarily a bank and may be divided into a dedicated storage area and a common storage area in one bank. Accordingly, it will be further apparent from the following description that a storage area other than a bank can be equally or similarly applied to a refresh method of a shared storage area according to the present invention, and a multi-port memory device that performs the method.

2 is a block diagram schematically illustrating a multi-port memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a multi-port memory device (hereinafter, referred to as a memory device) according to an exemplary embodiment of the present invention may include an A-port 220, a B-port 222, an A-port dedicated bank 200, and a shared bank. 202, a B-port dedicated bank 204, and access rights register logic 240.

A-port 220 and B-port 222 are connection ports that allow the first and second processors using the memory device to access the bank. That is, in the memory device according to the preferred embodiment of the present invention, two processors may be connected through the A-port 220 and the B-port 222.

Hereinafter, a subject connected to the common bank 202 through each port is a processor, but for convenience of description, the corresponding port is represented as connecting to the shared bank, which is not limited to the present invention. Will be done.

A-port dedicated bank 200 is a storage area where only A-port 220 can access and write and read data, and B-port dedicated bank 204 is a storage area that only B-port 222 can access. Area.

In contrast, the shared bank 202 is accessible to both the A-port 220 and the B-port 222, and in particular, the shared bank 202 according to the preferred embodiment of the present invention may be one or more shared blocks. It can be formed into). That is, the shared bank 202 is formed of one or more shared blocks so that the A-port 220 and the B-port 222 independently write and read data in each shared block. Can have. However, the same shared block cannot be accessed simultaneously.

The access right register logic 240 controls the access right for the A-port 220 or the B-port 222 to access the shared bank 202. That is, when the access right register logic 240 is requested to access the shared bank 202 from any port, the access right register logic 240 determines whether the access right for the corresponding shared bank is currently granted. If not provided, grants access to the corresponding port if it is not granted.

Here, although a dedicated bank for each port is provided in the figure, the memory device according to another exemplary embodiment of the present invention may include only a shared block. That is, all banks included in the memory device may be designated as shared banks so that the A-port 220 and the B-port 222 can access them. In addition, it is apparent that only one of the A-port dedicated bank 200 and the B-port dedicated bank 204 and the shared bank 202 may be provided. In addition, the dedicated areas 200 and 204 and the shared area 202 corresponding to each port are not limited to be divided into bank units, and it is apparent that the division criteria of each area may be set in various ways.

The processor accessing the memory device through the port provides the command and address information to the memory device, thereby reading the processed data (for example, data stored in an arbitrary bank) corresponding to the command. Corresponding to the stored data) can be provided from the memory device. Command information between the application of the processor and the memory device is set in advance.

The application of the processor may include command information such as, for example, ACT, READ, WRITE, Precharge, Refresh, Mode Register Set (MRS). To a memory device.

The above-described commands may be composed of a combination of / RAS, / CAS, / CS, and / WE information. The information previously designated to mean according to the low or high state of each signal may be different and may be easily changed. Hereinafter, information meaning by each signal or a combination of signals will be described as an example.

For example, the act command is a command in which / RAS is enabled low, and a command for enabling a word (WORD) corresponding to a row address.

The read command is a command in which / CAS is enabled low. The read command reads data corresponding to the cell address transmitted with the read command and outputs the data through the DQ pins (eg, data pins).

The write command is a command for enabling / CAS and / WE low, and is a command for writing data input from an input / output terminal (for example, a DQ pin) to a cell address transmitted together with the write command.

The precharge command is a command for enabling / RAS and / WE to be low, and is a command for disabling the word line enabled in the ACT command.

The refresh command is a command in which / RAS and / CAS are enabled low so that the data is periodically refreshed so that data in the memory is not lost. Each port dedicated bank performs a refresh by a refresh command sent from each port. The refresh command may be divided into an auto refresh command for performing refresh according to the command, and a self refresh command for continuously refreshing according to one command.

The mode register set (MRS) command enables all of / RAS, / CAS, / CS, and / WE to be low. It is a command for setting a synchronization specification of a memory device. It is included in the setting address part (refer to FIG. 3) to be transmitted. Here, it is obvious that the signals specifying the above-described commands (for example, enabling / RAS, / CAS, / CS, and / WE all low) may be set differently for each memory device.

The application of the processor provides the control logic (see Fig. 6) with the command and address preset by the combination of / RAS, / CAS, / CS and / WE as described above. Here, the control logic functions to receive the command from the processor and deliver the command to the bank corresponding to the address included in the command. Here, the control logic may cover a plurality of processors, but more preferably may be provided for each processor to function independently. Hereinafter, a case in which the access right register logic 240 performs a corresponding function including the control logic will be described as an example, but it is natural that the control logic may be provided separately.

The banks 200, 202, and 204 are units that can read data from or write data to the memory. In the case of SDRAM, two bits are allocated to the bank address according to the JEDEC standard. Therefore, it is common to divide into four banks and perform multiple operations.

In FIG. 2, the A-port dedicated bank 200 is an area where only the A-port 220 can access to read data or write data. Thus, the B-port 222 is unable to access the A-port dedicated bank 200.

The B-port dedicated bank 204 is an area where only the B-port 222 can access to read data or write data. Thus, the A-port 220 is unable to access the B-port dedicated bank 204.

The shared bank 202 is an area where both the A-port 220 and the B-port 222 can access and read data and write data. Conventionally, it is possible to access any of the A-port 220 and the B-port 222 to the shared bank 202, but while the A-port 220 occupies the shared bank 202, Port 222 was unable to access shared bank 202, while A-port 220 accessed shared bank 202 while B-port 222 occupied shared bank 202. I could not.

According to a preferred embodiment of the present invention, one or more shared blocks (block 0, block 1, ..., block N) that are independently accessible as shown in the figure to solve this conventional problem are shared bank ( 202 is provided. Of course, the case where there is one shared block does not need to be divided into blocks, and only when two or more ports can access the shared bank 202 at the same time, and in this case, each port can access a different shared block. Of course.

Each shared block in the shared bank 202 can be freely selected by the access right register logic 240, and the A-port 220 and the B-port 222 can each have multiple operations for the selected shared block. . The same shared block within the shared bank 202 can be set, reset, and read for that shared block so that the A-port 220 and the B-port 222 can not be accessed at the same time. Execute the command Set is an operation for possessing an access right to a corresponding shared block, and Reset is an operation for returning an access right. Read is for checking whether the corresponding shared block has authority to another port and whether its own port has access to the shared block. That is, according to the read command, the access right register logic 240 outputs the value recorded in the access right register to inform the corresponding port whether or not to grant the access right.

Accordingly, each shared block (blocks 0, 1, ..., block N) of the shared bank 202 can operate independently, and the A-port 220 and the B-port 222 are each shared. One of the blocks can be accessed independently. For example, while the A-port 220 accesses shared block 0 211 to read or write data, the B-port 222 remains in shared block 1 212 for data read or write. I can access it. However, while occupying and using a specific shared block occupied and used by the A-port 220, the B-port 222 may not use a shared block occupied and used by the A-port 220.

3 is a diagram illustrating a structure of a general MRS command and address combination, and FIG. 4 is a diagram illustrating an example of a modified MRS command according to an exemplary embodiment of the present invention.

According to a preferred embodiment of the present invention, the access right register logic 240 is controlled using an extended MRS (EMRS) which extends the MRS of the conventional SDRAM. EMRS is an extension of MRS by controlling additional functions such as partial array self refresh (PASR) and driver strength (DS).

Referring to FIG. 3, a general MRS command is divided into a part 300 for setting a command type and a setting address 302 part. As shown in FIG. 4, in the part for setting a command type, / CAS, / RAS . Both / CS and / WE are set low, so the control logic identifies them as MRS commands.

In the setting address 302, information for setting an operation specification of the memory is recorded. Specifications set include Burst Length, Burst Type, CAS Latency, Operation Mode, and Write Burst Mode. The specifications set by the MRS command are retained until new specifications are set or power is lost to the memory device.

To set the burst length, typically 3 bits are allocated and the burst length is set to 1, 2, 4, or 8. Three bits are allocated to set the CAS latency, and typically three kinds of CAS latency are set. Allocate two bits to set the operation mode and one bit to set the light burst mode and burst type.

According to the present invention, the command type and the address of the MRS command are maintained as they are, but the A-port 220 and the B-port 222 independently use the shared block by using address bits different from the general MRS command. To be able. As such, the fact that the modified MRS command is used as a command for using the shared block of the shared bank 202 is preset between the application of the processor and the memory device.

Here, although the MRS command is illustrated as one piece of data, the / CAS and / RAS. Signals according to / CS and / WE and the setting address 302 may be input through respective input pins of the port, etc., which will be apparent to those skilled in the art, and thus detailed description thereof will be omitted.

Referring to FIG. 4, the command type part 400 of the modified MRS command (hereinafter, referred to as an 'EMRS command') for using a shared block is the same as a normal MRS command, and a shared block command is included in the set address part. Information 402 and shared block address information 404 are included. Hereinafter, the shared block command information 402 and the shared block address information of the EMRS command according to an embodiment of the present invention will be referred to as "key address".

As shown in Fig. 4, since the command type part is the same as the command type part of the normal MRS command, the control logic determines whether it is an EMRS command or a normal MRS command for use of a shared block through the information of the setting address part. do. Of course, a separate identification part (not shown) for determining whether the EMRS command is used for the shared block may be further included in the configuration address part. That is, through the address part of the EMRS command (that is, the part including the shared block command information 402 and the shared block address information 404), the control logic indicates that the corresponding MRS command is an EMRS command for using the shared bank 202. I can recognize it.

The shared block command information of the EMRS command includes command information set for use of the shared block. According to a preferred embodiment of the present invention, a command set for using a shared block includes a SET, READ, and RESET commands. For example, when two bits according to the shared block command information are allocated to the address, the set may be set if "00", read if "01", or reset if "10".

The SET command is a command for occupying a specific shared block of the shared bank 202. That is, the set command is a command for requesting access right to the access right register logic 240. Therefore, when a specific shared block is to be used in the A-port 220 or the B-port 222, first, an occupancy of the shared block is attempted by using a SET command. The access right register logic 240 enables the access right flag (see FIGS. 5 and 6) according to the corresponding port and the corresponding shared block according to the set command, and grants the access right to the corresponding port.

The READ command is a command for confirming whether a state is occupying a specific shared block (that is, a state in which access authority is granted). When a READ command is sent, the access right register logic 240 provides information to determine whether the port to which the current READ command is transmitted occupies the corresponding shared block. That is, when the A-port 220 or the B-port 222 wants to use a specific shared block of the memory device, the A-port 220 or the B-port 222 occupies the shared block through the SET command, and the corresponding block through the READ command. It can be checked whether the shared block is normally occupied. According to the read command, the access right register logic 240 provides data of the access right register in which the value for the access right flag is stored to the corresponding port through the DQ pins (see FIG. 6).

The reset command is a command for releasing the occupation of a specific shared block. When the use of the memory sharing block of the shared bank 202 is finished, the reset of the shared block is released through the reset command.

As described above, when three types of commands for using a shared block are used, two bits may be used as bits for setting commands. However, it will be apparent to those skilled in the art that various types of commands may be additionally set in addition to the above three types of commands, in which case additional bits for command setting may be used.

After the occupancy and occupancy confirmation of the specific shared block is performed by the SET command and the READ command, the data of the specific shared block is read or written through a normal read command or a write command. It is possible.

The shared block address information 404 includes address information for the shared block associated with the shared block command 402. As shown in FIG. 1, when four shared blocks are provided in the shared bank 202, two bits may be allocated for the shared block address. For example, eight shared blocks may be provided in the shared bank 202. In this case, three bits may be allocated for the shared block address. Of course, the number of bits for them may be allocated larger than the number of shared blocks.

Since the number of bits of the setting address (key address) must be the same as that of a normal MRS command, the extra bits other than the above-mentioned bits for setting the shared block command and the shared block address are set to a preset value. For example, all bits can be set to have a low value.

In the above, the case in which the MRS command is modified and used as a command using a specific shared block of the shared bank 202 has been described. However, the present invention is directed to modifying the MRS command to use a specific shared block of the shared bank 202. The present invention is not limited thereto, and other commands may be modified and used as a command using a specific shared block.

For example, the read command, the write command, and the like may be modified and used as a command for using a specific shared block.

Hereinafter, a method of controlling access right to each shared block of the shared bank 202 by the access right register logic 240 according to an exemplary embodiment of the present invention will be described in detail.

5 is a diagram illustrating a shared bank and access right register logic according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a configuration of access right register logic according to an exemplary embodiment of the present invention.

As described above, according to a preferred embodiment of the present invention, the A-port 220 and the B-port 222 may have access to any shared block using a modified MRS command (EMRS command). .

The access rights register logic 240 is assuming that the set address part is any key address when an MRS command comes in (i.e., when the MRS command is an EMRS command according to a preferred embodiment of the present invention as shown in FIG. 4). The corresponding set, reset or read is performed. In other words, if the EMRS command from the port is a set command, the access right register logic 240 enables the corresponding access right flag to provide the access right for the shared block to the corresponding port.

Referring to FIG. 5, the access right register logic 240 includes an access right register so as to correspond to the number of each shared block with the A-port 220 and the B-port 222, and the access right flag for the access right flag. Save the value. That is, the access authority flags flagA <0>, flagA <1>, ..., flagA <N>, and B-port 222 of the A-port 220 according to the N shared blocks. flagB <0>, flagB <1>, ..., flagB <N> are provided. For example, the access right flag flagA <0> according to shared block 0 controls the A-port 220 side, and flagB <0> controls the B-port 222 side.

Accordingly, when an EMRS command according to a set command is received from any port, the access right register logic 240 recognizes the corresponding shared block through the shared block address information of the key address, and the shared block command information of the key address. Recognizes the set command and grants access to it.

For convenience of understanding, for example, when a set command for shared block 1 is received from the A-port 220, the access right register logic 240 refers to flagA <1> and flagB <1>. If both access rights flags are disabled, flagA <1> is enabled to grant the A-port 220 access to shared block 1.

The configuration of access rights register logic 240 in accordance with a preferred embodiment of the present invention is shown in FIG.

As shown in FIG. 6, the access rights register logic 240 includes control logic 241, 242, flag logic 244, and refresh logic 246. Although not shown, for the control of each shared block, it further includes as many access rights registers as the number of shared blocks. The access rights register may be included in the flag logic 244.

Two control logics 241 and 242 may be provided for the A-port 220 and the B-port 222. Since the main functions of the control logic 241 and 242 have been described above, a detailed description thereof will be omitted. In particular, the control logic 241, 242 generates a set, reset, read signal in accordance with the EMRS command received from each corresponding port. In other words, the key address of the EMRS command is decoded to recognize the shared block to which the port is to be accessed, and to generate a corresponding signal (one of a set, a reset, and a read). The signal generated to control the access right register of the desired shared block is block <0: N> (that is, shared block address information for identifying the corresponding shared block among 0 to N shared blocks). Here, sets, resets, and reads are not performed at the same time, but are performed one by one command.

The set of outputs of the control logic 241 and 242 is a command for enabling the access right flag to create a right to access the corresponding shared block. The read is for outputting the values stored in the access right register to the output means (e.g., the DQ pin). Read is an operation that checks if the desired shared block is set properly in each port when the access right register is set in each port. The reset is to return the access right of the shared block. The reset operation resets the value of the access right register to return the access right and makes it available again to another port or one's own port.

Accordingly, the flag logic 244 enables the access right flag according to one of the set, reset and read signals and the information block <0: N> for the corresponding shared block from the control logic 241 and 242. Or disable or print the access register value.

The above cases represent the general operation when no port has access to the corresponding shared block. If one port (e.g., A-port 220) already has access rights, the access rights register is used to access the same shared block on the other port (e.g., B-port 222). There may be times when you set. In this case, since the A-port 220 already has access authority, even if the corresponding access authority register is set in the B-port 222, the internal operation does not cause any change, but the output of the B-port 222 side. A "/ busy" signal is enabled and output via a pin (e.g., a DQ pin). The / busy signal may serve as a prohibition signal, or may be recognized as "wait" to wait because a prohibition is currently being performed. Therefore, when the / busy signal is enabled, the processor according to the corresponding port waits until access to the shared block is prohibited or accessible. That is, the port is accessible only when this signal is disabled. The / busy signal is enabled when either port has access to the same shared block. When the / busy signal is disabled, the corresponding port having access authority resets the access right register of the same shared block or resets the port on which the / busy signal is enabled. That is, if the partner port having access authority resets the access right register of the same shared block, the port on which the / busy signal is enabled performs the reset, and then sends the set command back to the access right register logic 240. Access to the shared block can be granted.

As discussed above, the access right register logic 240 grants access to any shared block in the shared bank 202 in accordance with the EMRS command.

Here, since the present invention is related to the refresh of each shared bank 202 and the shared block, all the methods for controlling access right to the shared block other than the above-described access right control method can be equally applied. Will become more self-evident.

Hereinafter, a refresh method of a shared storage area (eg, a shared bank or a shared block) according to an exemplary embodiment of the present invention will be described in detail.

Although FIG. 6 shows that the means for refreshing the shared block (refresh logic 246) is included as a component of the access rights register logic 240, the refresh logic is separate from the access rights register logic 240. Of course, it may be implemented as.

Each shared block is assigned a refresh order in advance. The refresh order may be a sequential order implemented in hardware. The refresh logic 246 controls the shared block to be refreshed according to the refresh order. For example, if there are shared blocks 1, 2, 3, and 4, and the current refresh order is shared block 2, according to the auto refresh command from a specific port (for example, a port having access authority). Shared block 2 performs a refresh. Here, the refresh logic 246 may receive a refresh command (auto refresh command and self refresh command) from each port regardless of the access right. The refresh command for refreshing the shared block can be executed when receiving from a port having access authority. If the access authority is not granted to any port, it is refreshed according to the auto refresh command received from any port. The refresh may be performed at every self refresh period of the port that has entered the self refresh of each port. The refresh method according to the access right will be described later in detail with reference to the related drawings (FIGS. 7 to 16).

The refresh logic 246 may include a refresh order register (not shown) for counting the refresh order. That is, the refresh logic 246 may recognize the corresponding shared block to be refreshed through the refresh order register.

Accordingly, the refresh logic 246 recognizes the corresponding shared block to be currently refreshed through the refresh order register and receives information on the access right flag from the flag logic 244, and whether or not to grant access to the shared block. The authorized port can be recognized, and the shared block can be controlled to be refreshed according to the refresh command from the corresponding port.

Hereinafter, a method of performing refresh according to whether access authority is granted and a port granted access authority will be described.

7 to 11 illustrate a method of refreshing a shared bank that is not divided into shared blocks according to a preferred embodiment of the present invention. FIGS. 12 to 16 illustrate a plurality of shared banks according to a preferred embodiment of the present invention. It is a figure which shows the refresh method of a shared block when it is divided into shared blocks.

The refresh method in the case where no access right is granted to any port is shown in FIG. In this case, the shared bank performs the refresh in accordance with the refresh command (auto refresh or self refresh) received from any one of the two ports in the idle state. Although a refresh command is transmitted to each bank directly from each port in the figure, the refresh logic 246 receives a refresh command from a port, and accordingly, transmits a command for refresh to the corresponding bank. Will be self explanatory. However, for convenience of explanation, hereinafter, it will be assumed that each port directly transmits a refresh command to the bank.

8 illustrates a refresh method when any one port has access authority. In this case, the refresh of the shared bank is performed only according to the refresh command received from the port having the access right.

FIG. 9 is a case where any one port (A-port) enters self-refresh (S-Refresh: self refresh) (that is, self-refresh is performed at regular time intervals according to the self-refresh command received from the A-port. Therefore, the A-port dedicated bank performs self-refresh), and another port (B-port) does not have access to the shared bank. In this case, every self-refresh or B- of the A-port is shown. According to the port's auto refresh command, refresh is performed when the shared bank is idle.

Referring to FIG. 10, even if any one port (A-port) enters self-refresh, when another port, B-port, has access to the shared bank, sharing is performed only by the auto-refresh command of the B-port. Refreshing of the bank is performed.

Referring to FIG. 11, a case in which both ports enter self refresh is illustrated. In this case, refresh of the shared bank is performed only according to self refresh of a predetermined port (for example, A-port as shown in the figure). Can be performed.

The refresh method of each shared block of the shared bank divided into a plurality of shared blocks may also be performed similarly to the refresh method of the shared bank not divided into the plurality of shared blocks. However, in the method of refreshing a shared block, a refresh order is specified in advance for each shared block, and the shared block according to the order is refreshed.

Referring to FIG. 12, according to a predetermined refresh order, when the access right to the shared block to be refreshed is not granted to any port, refresh of the shared block is performed according to the refresh command received from any port.

Referring to FIG. 13, in the case where the current refresh order is shared block 1 and the A-port has access authority of shared block 1 (ie, shared block 1 performs refresh according to the refresh command of A-port). ) Is shown.

Referring to FIG. 14, even if the A-port has access rights of the shared block 1, if the shared block 2 is in the current refresh order and access rights to the shared block 2 are not granted to any of the ports, according to FIG. 12. As in the case, the refresh of the shared block 2 is performed according to the refresh command of the A-port or the B-port.

FIG. 15 illustrates a case in which the A-port enters self refresh and the B-port does not have access to any shared block. In this case, the shared block corresponding to the current sequence is the self-refresh or the A-port. Refresh is performed according to the refresh command of the B-port.

FIG. 16 illustrates a case in which both ports enter self refresh, in which case, a shared block corresponding to the refresh sequence is assigned to the self refresh of a specific port (for example, an A-port as shown in the figure). Refresh according to the operation.

As described above, the contents described with reference to the drawings that the A-port 220 or the B-port 222 accesses the memory device are merely for convenience of description, and in practice, through each port It is obvious that the processor accesses the memory device. In addition, it is obvious that the signals specifying the above-described commands (for example, enabling / RAS, / CAS, / CS, and / WE all low) may be set differently for each memory device.

In addition, although a dedicated storage area accessible only through a specific port and a common storage area accessible by a plurality of processors through multiple ports have been described in bank units, this does not necessarily need to be a bank. It may be divided into a common area. Therefore, since a bank may be a unit for a storage area, a multi-port memory device and a refresh method for performing a stable refresh of a shared bank according to the present invention may be applied to the storage area other than the bank in the same or similar manner. Will be self-evident.

The method of the present invention as described above may be implemented in a program and stored in a computer-readable recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, magneto-optical disk, etc.).

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, according to the present invention, it is possible to provide a multi-port memory device and a refresh method thereof in which a shared storage area such as a shared bank of the multi-port memory performs stable refresh.

In addition, the present invention also has the effect that it is possible to perform a stable refresh of each shared block even for a memory device having a shared storage area implemented by a plurality of shared blocks that multiple ports can simultaneously access the shared storage area.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art that various modifications of the present invention without departing from the spirit and scope of the invention described in the claims below And can be changed.

Claims (15)

A multi-port memory device having two or more ports, One or more shared storage areas accessible by a plurality of processors through each port; And Access rights register logic for controlling access rights for the processor to access the shared storage through each port, The shared storage area receives an auto refresh command from a specific processor having access authority or refreshes according to an auto refresh command or a self refresh command from an arbitrary processor when all processors do not have access authority. Multi-port memory device. The method of claim 1, Multi-port memory device further comprising one or more dedicated storage accessible only through specific ports. The method of claim 1, And receiving a self refresh command from two or more processors, wherein the shared storage area self refreshes according to a self refresh command received through a predetermined port. The method of claim 1, The shared storage area may include one or more blocks that divide a storage area into predetermined units, and the processor may independently access one of the blocks according to an access right granted by the access right register logic. Multiport memory device. The method of claim 4, wherein And a command for accessing and using a specific block of the shared storage area in the processor is a command obtained by modifying an address part of a preset memory command. The method of claim 5, And wherein the modified address part includes address information of a shared storage block and command information relating to use of the shared storage area. The method of claim 6, The command related to using the shared storage area may include a SET command for requesting access to a specific block of the shared storage area, and a read for checking whether access to the specific block of the shared storage area has been granted. Command) and a reset command for requesting release of access to a specific block of the shared storage area. The method according to any one of claims 1 to 7, The shared storage area or the dedicated storage area is a multi-port memory device, characterized in that allocated in units of bank (bank). A multi-port memory device having two or more ports, A shared storage area including a plurality of shared blocks accessible by a plurality of processors through the respective ports; Access rights register logic for controlling access rights for the processor to access the shared block through each of the ports, Each shared block receives an auto refresh command from any processor having access authority according to a predetermined refresh order, or auto refresh commands or self refresh from any processor when all processors do not have access authority. And refresh according to a command. The method of claim 9, And the access right register logic includes a refresh order register for counting the refresh order. The method of claim 9, Multi-port memory device further comprising one or more dedicated storage accessible only through specific ports. A method of refreshing the shared block in a multi-port memory device comprising one or more shared storages accessible by a plurality of processors through multiple ports (a) receiving a refresh command from any processor through a corresponding port; And (b) performing refresh when the access right to the shared storage is granted and the processor has the access right, or when the access right to the shared storage is not granted. Refresh method for containing shared storage. The method of claim 12, And wherein the refresh command is an auto refresh command or a self refresh command. The method of claim 12, The shared storage area includes at least one block that divides the storage area into predetermined units, and each processor independently accesses one of the blocks according to an granted access right. Refresh method. The method of claim 14, The step (b) is a method for refreshing a shared storage area, characterized in that the step of recognizing the shared block that is the turn to perform the current refresh in a predetermined order.

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