KR100715525B1 - Multi-port memory device including clk and dq power which are independent - Google Patents

Abstract

The present invention discloses a multi-port memory device. According to a preferred embodiment of the present invention, at least one dedicated bank allowing only access to a specific port, at least one shared bank allowing access to multiple ports, and an input / output pin through which input / output power (DQ power) is transmitted for each port (DQs pin) and a clock pin (CLK Pin) to provide a clock (CLK) per port, the input and output power (DQ power) and the clock (CLK) is a port-independent multi-port memory device. According to the present invention, an independent command in a corresponding region can be independently executed from a different application for each port in a multi-port memory without time delay, and each port uses a different level of input / output power (DQ power). It has the advantage that it can run smoothly and smoothly between interfaces.

I / O power, clock, multiple, port

Description

Multi-port Memory Device Including CLK and DQ power which are independent}

1 is a view showing a bank structure of a dual port memory of the multi-port memory according to the prior art.

2 illustrates an example of a chip architecture of a dual port memory of a multiport memory according to the prior art.

FIG. 3 is a diagram illustrating an example of a chip architecture of a dual port memory of a multi-port memory device including independent input / output power (DQ power) and a clock for each port according to an exemplary embodiment of the present invention. FIG.

4 is a diagram illustrating a configuration of a multi-port memory device including a plurality of shared blocks in a shared bank according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a state in which an A-port and a B-port access each bank according to an exemplary embodiment of the present invention.

FIG. 6 illustrates a chip architecture of a dual port memory device among a multi-port memory device including a plurality of shared blocks and including independent input / output power (DQ power) and a clock for each port in a shared bank according to an exemplary embodiment of the present invention. diagram showing an example of a (chip architecture).

FIG. 7 illustrates an example in which two different ports operate independently in a corresponding area in performing commands such as MRS, EMRS, Read, Write, and Refresh for each port according to an exemplary embodiment of the present invention. drawing.

The present invention relates to a multi-port memory device, and more particularly, to a multi-port memory device having core power and input / output power (DQ power) independent for each port.

In general, memory is divided into various ways according to how it is divided. For example, depending on whether the stored contents are maintained according to whether the power is applied or not, it may be classified into volatile memory and nonvolatile memory. Generally, volatile memory is random access memory (RAM), and nonvolatile memory is ROM (Read Only). Memory).

Again, it is divided into DRAM (Dynamic RAM) and SRAM (Static RAM) according to whether or not the cells constituting the memory should be periodically refreshed.

In addition to the classification method, single port memory and dual port memory are classified according to the number of accessible ports.

Single port memory is accessible to all cells constituting the memory through a single port, whereas a plurality of port memories except for single port memory are limited to cells accessible from each port.

However, recent digital processing apparatuses each have a plurality of processors for performing a predetermined function, and each processor has a memory for storing data for operation, data for processing, processed data, and the like. Combined with.

In a memory system in which a plurality of processors share one memory, a multi-port memory including a plurality of ports is more efficient than a single port memory, and thus, multi-port memory has been widely used in recent years.

1 is a diagram illustrating a bank structure of a dual port memory of a multi-port memory according to the prior art.

Referring to FIG. 1, a conventional dual port memory includes an A-port dedicated bank 100, a shared bank 102, and a B-port dedicated bank 104 and 106. The A-port dedicated bank 100 is a bank in which only the A-port accesses to read or write data, and the B-port dedicated banks 104 and 106 access only the B-port to access data. A bank for reading or writing. The shared bank 102 is a bank to which both the A-port and the B-port can access to read or write data.

2 is a diagram illustrating an example of a chip architecture of a dual port memory of a conventional multi-port memory.

Referring to FIG. 2, the dual-port memory of the conventional multi-port memory includes the A-port dedicated bank 200, the shared bank 202, the B-port dedicated banks 204 and 206, and the respective control, address, and per port. I / O pins 210 and 212, a common clock, common input / output power (common CLK, DQ power) 220, and common core power 230.

Conventionally, the shared bank 202 is a bank that can be used by both A-port and B-port, or when one of the A-port and B-port uses a shared bank, the other port uses a shared bank. Could not be used. That is, the B-port could not access the shared bank while the A-port accessed the shared bank and read data. Therefore, the B-port was forced to wait until the A-port finished using the shared bank before using the shared bank.

As half a century after the semiconductor industry was created, as many kinds of products were developed and demanded for higher performance and higher density, the conventional multi-port memory device can solve such problems by increasing the number of banks. As a result, the JEDEC standard only assigns 2 bits to a bank address, which means that more than four banks cannot be used.

Although the concept of a shared bank was introduced for efficient use of banks for each port, there was a limit in maximizing utilization of limited banks. In order to operate a plurality of different applications smoothly, each port must be independently operated in a multi-port memory device, but a common clock (common CLK) and a common input / output power (common DQ power) are used. There is a problem that there is a limit in executing independent commands in a corresponding area from different applications for each port.

In order to solve the above-mentioned problems, the present invention proposes a multi-port memory device in which each of the ports has independent input / output power (DQ power) and a clock (CLK). will be.

In addition, in the multi-port memory device, the memory area of the shared bank is divided into a plurality of blocks to maintain the number of banks, while providing an effect such that the number of banks is substantially increased. By having independent input / output power (DQ power) and clock (CLK), a multi-port memory device capable of performing independent commands in a corresponding area from a different application for each port is proposed.

Still other objects of the present invention will be readily understood through the following description of the embodiments.

In order to achieve the above object, according to an aspect of the present invention, a multi-port memory device having two or more ports, comprising: at least one dedicated bank to allow access only to a specific port; At least one shared bank to allow access to multiple ports; Input / output pins (DQs pin) through which input / output power (DQ power) is transmitted for each port; And a clock pin CLK that provides a clock CLK for each port, wherein the input / output power DQ power and the clock CLK are independent of each port.

The shared bank may include a plurality of blocks obtained by dividing a memory area of a bank into predetermined units, and the multiple ports may independently access and use one of the plurality of blocks.

One or more of the ports may include one or more ports that use a reference clock of a system in which the multi-port memory device is installed, and have an independent clock corresponding to an application among other ports.

One or more of the ports may include one or more ports having input / output power in common with the core power of the multi-port memory device and having independent input / output power corresponding to an application among other ports.

As one or more of the applications for each port are changed, one or more of the port-specific clock or input / output power corresponding to the changed application may include one or more ports independently changed.

According to another aspect of the invention, a first port dedicated bank for allowing access only to the first port; A second port dedicated bank to allow access only to the second port; A shared bank allowing access to the first port and the second port; Input / output pins (DQs pin) through which input / output power (DQ power) is transmitted for each port; And a clock pin CLK that provides a clock CLK for each port, wherein the input / output power DQ power and the clock CLK are independent of each port. .

The shared bank may include a plurality of blocks obtained by dividing a memory area of a bank into predetermined units, and the dual port may independently access and use one of the plurality of blocks.

One of the ports may use the reference clock of the system in which the dual port memory device is installed and include the other one having an independent clock corresponding to the application.

One of the ports may include the other one having input / output power common to the core power of the dual port memory device and having independent input / output power corresponding to the application.

As one or more of the applications for each port are changed, one or more of the port-specific clock or input / output power corresponding to the changed application may include one or more ports independently changed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

FIG. 3 is a diagram illustrating an example of a chip architecture of a dual port memory among a multi-port memory device including independent input / output power (DQ power) and a clock for each port according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a dual port memory device according to an exemplary embodiment of the present invention may include an A-port dedicated bank 330, a shared bank 332, two B-port dedicated banks 334 and 336, and a common core. Power (300, 302), input and output power (310, 312) of the A and B ports, input and output pins (320, 322) of the A and B ports and clock, control, address pins (340, 342) of the A and B ports It may include.

Although FIG. 3 illustrates a dual port memory device accessing a memory bank from two ports, the present invention may be applied to multiple ports accessing a memory bank from two or more ports.

In FIG. 3, one bank is allocated to the A-port dedicated bank and two banks are allocated to the B-port dedicated bank. However, this is only an example. It will be apparent to those skilled in the art that the number of dedicated banks allocated may vary.

In the past, the clocks of the A-port and the B-port were common. Therefore, when executing independent commands in the corresponding area from different applications, the A-port and B-port were limited in time to perform independent operations.

For example, the limitations of having a common clock are as follows. In synchronous DRAM (SDRAM), since the SDRAM is a synchronous DRAM, the state of each pin is read when the reference clock rises, and the information is read. It works on the basis of

For example, conventionally, when the reference clock is 5 ms (that is, the reference clock rises once every 5 ms), the SDRAM reads the state of each pin in 5 ms units and operates based on the information. do. In case of performing independent command in each area by different application from port to port, A-port should execute "write" command at 10ms and B-port should execute "read" command at 12ms. If the A and B ports use a common clock, the B-port cannot execute the "read" command at 12 ms and wait until the reference clock rises at 15 ms to read the state of each pin in line with the reference clock. There is a limit point. Therefore, in this case, a problem occurs that a delay of 3 ms occurs in the B-port.

According to a preferred embodiment of the present invention, in order to solve such a conventional problem, an independent clock is assigned to the A-port 340 and the B-port 342 to perform an independent command in a corresponding region from different applications. For each port, the operation can be performed independently without any time delay.

According to a preferred embodiment of the present invention, in the above example, the A-port 340 may independently perform the "write" command at 10 ms, and the B-port 342 may perform the "read" command at 12 ms independently for each port. There is no delay of 3ms.

For example, the A-port 340 can use an existing clock such as a main, server, or main body in which a memory device is installed, and the B-port 342 can use an independent clock for independent commands in a corresponding area from different applications. have.

For example, both A-port 340 and B-port 342 can use clocks that are independent of each other to perform independent commands in the region from different applications.

For example, in a mobile phone, the A-port 340 is an independent conventional clock used for baseband signal processing, while the B-port 342 is suitable for performing an image processing application of the LCD screen of the mobile phone. Independent conventional clocks can be used to execute independent commands for different applications.

For example, A-port 340 executes an independent command in the region from the a1 application at t1 clock, and B-port 342 executes an independent command in the region from the b1 application at t2 clock. In this case, when the B-port 342 needs to execute an independent command in the corresponding area from another application (for example, the b2 application), the B-port 342 may use the t3 clock for the b2 application in the corresponding area. Can perform independent commands.

At this time, when the application of the A-port 340 is changed, the clock of the A-port may also be changed to the clock for the application of the A-port is changed.

In the past, the input / output power of the A-port and the B-port was common. Therefore, when executing independent commands in the corresponding area from different applications, the A-port and B-port were limited in terms of speed or interface in performing independent operations.

For example, when the input and output power of the A-port and the input and output power of the B-port are 1.8 volts in common and the core power is 1.8 volts, the A-port and the B-port are currents. There is no difference in terms of speed or speed.

For example, if a high speed operation is to be performed at the A-port and a low speed operation is to be performed at the B-port, the input / output power (DQ power) of the A-port and the input / output power (DQ power) of the B-port are The same problem arises that the speed of each port must be the same, so that power cannot be efficiently used in the memory device.

For example, if you want a low current on the A-port and a relatively high current on the B-port, then the A-port's DQ power and the B-port's DQ power are the same. Inevitably, high currents were used, and power could not be used efficiently.

According to a preferred embodiment of the present invention, in order to solve such a conventional problem, independent input / output power (DQ power) is provided to the A-port and the B-port, so as to execute independent commands in a corresponding region from different applications. Therefore, each port can operate smoothly between aspects of speed and interfaces.

For example, the input / output power (DQ power) 310 of the A-port is 1.8 volts, the input / output power (DQ power) 312 of the B-port is 3.3 volts in common, and the core power (300) ) Is 1.8 volts can reduce the current between the core power (300) and the A-port 320, the relatively B-port 322 can be configured to perform commands at high speed Do.

In this case, while the A-port 320 performs a command at a low speed, the current between the core power 300 and the A-port 320 may be reduced, thereby increasing power efficiency.

At this time, the B-port 322 has a relatively high current between the core power 300 and the B-port 322, but may execute a command at a high speed.

For example, the A-port 320 executes an independent command in the corresponding area from the a1 application with the input / output power of v1 volts, and the B-port 322 uses the input / output power of the v2 volt in the corresponding area from the b1 application. If the B-port 322 needs to execute an independent command in the corresponding area from another application (for example, the b2 application), when the B-port 322 executes an independent command of the b2 application. v3 I / O power enables independent commands in the area.

At this time, when the application of the A-port is changed, the input-output power of the A-port 320 may also be changed to the input-output power for the application of the A-port.

Hereinafter, a multi-port memory device including a plurality of shared blocks and including independent input / output power (DQ power) per port and an independent clock per port in a shared bank according to an exemplary embodiment of the present invention will be described. Shall be.

4 is a view for explaining a plurality of shared blocks in the shared bank of the preferred embodiment of the present invention shown in FIG.

Referring to FIG. 4, a multi-port memory device according to a preferred embodiment of the present invention may include an A-port dedicated bank 400, a shared bank 402, two B-port dedicated banks 404 and 406, and a first and second port. The second control logic / registers 430, 432 may be included and the shared bank 402 may include a number of blocks 410, 412, 414, 416.

Although FIG. 4 illustrates a dual port memory device accessing a memory bank from two ports, the present invention may be applied to multiple ports accessing a memory bank from two or more ports.

The applications 420 and 422 provide command and address information to the memory device for use of the memory device, and receive processing data corresponding to the command from the memory device. Command information with the applications 420 and 422 and the memory device is set in advance.

The application 420 may include, for example, command information such as Act, Read, Write, Precharge, Refresh, Mode Register Set (MRS). To the memory device.

The above commands consist of a combination of / RAS, / CAS, / CS and / WE information.

For example, the act command is a command in which / RAS is enabled low, and a command for enabling a word (WORD) corresponding to a row address.

The read command is a command for enabling / CAS low and is a command for reading data corresponding to the cell address transmitted together with the read command and outputting the data to the DQ.

The write command is a command for enabling / CAS and / WE low, and is a command for writing data input from the DQ to a cell address transmitted together with the write command.

The precharge command is a command for enabling / RAS and / WE to be low, and is a command for disabling the word line enabled in the ACT command.

The refresh command is a command that enables / RAS and / CAS to be low, and is a command to periodically refresh so that data in the memory is not lost.

The mode register set command is a command for enabling ./RAS, / CAS, / CS, and / WE all low. It is a command for setting a synchronization specification of a memory device, and a value for setting synchronization is transmitted with the command. It is included in the address field.

The application 420 provides the register 408 with a command and address preset by the combination of / RAS, / CAS, / CS and / WE as described above.

The first and second control / logic registers 430 and 432 serve to receive a command from the application 420 and deliver the command to a bank corresponding to the address contained in the command.

The banks 400, 402, 404, and 406 are units that can read data from or write data to the memory. In the case of SDRAM, two bits are allocated to the bank address according to the JEDEC standard. Therefore, it is common to divide into four banks and perform multiple operations.

In FIG. 4, the A-port dedicated bank 400 is an area where only the A-port can access to read data or write data. Thus, the B-port is unable to access the A-port dedicated bank 400.

The dedicated B-port banks 402 and 404 are areas in which only the B-port can access to read data or write data. Thus, the A-port is unable to access the B-port dedicated banks 402 and 404.

In FIG. 4, one bank is allocated to the A-port dedicated bank and two banks are allocated to the B-port dedicated bank. However, this is only an example. It will be apparent to those skilled in the art that the number of dedicated banks allocated to can be changed.

The shared bank 402 is an area in which both A and B ports can access and read data and write data. Conventionally, it is possible to access either port A or port B to the shared bank 402, but port B can access the shared bank 402 while port A occupies the shared bank 402. No, port A could not access shared bank 402 while port B was occupying shared bank 402.

Therefore, according to the related art, the A port and the B port could alternately use the shared bank 402 but could not use the shared bank 402 at the same time. For example, while port A connects to the shared bank and reads data written to the shared bank, port B was unable to write data to the port A to transfer to the shared bank.

According to a preferred embodiment of the present invention, a plurality of independently accessible blocks 410, 412, 414, 416 are provided in the shared bank to solve this conventional problem.

The plurality of blocks 410, 412, 414, 416 may operate independently, and the A port and the B port may independently access one of the plurality of blocks. For example, if port A accesses block 0 (410) to read or write data, port B may access block 1 (412) to read or write data. However, while using and occupying a specific block occupied by port A, port B cannot be used for a block occupied and used by port A.

A structure in which the A port and the B port independently access blocks provided in the shared bank 402 will be described with reference to FIG. 5.

4 illustrates a case in which the shared bank 402 includes four blocks 410, 412, 414, and 416, the number of shared blocks may be variously changed to one of 2 ^N. For example, the number of shared blocks may be changed as needed, such as 2, 4, 8, 16, and the like.

Between the applications 420 and 422 and the memory, the A and B ports independently access the blocks 410, 412, 414 and 416 provided in the shared bank 402 to preset a combination of instructions for using the block. It is.

5 is a diagram illustrating a state in which an A-port and a B-port access each bank according to an exemplary embodiment of the present invention.

In FIG. 5, bank 0 500 is an A-port dedicated bank, bank 1 502 is a shared bank, and bank 3 504 is a B port dedicated bank.

In FIG. 5, the X decoder of each bank performs coding for row addresses, and the Y decoder performs coding for addresses in columns. In addition, S or C of each bank serves as a control circuit for processing a command transmitted to the bank.

As shown in FIG. 5, only the A port is accessed to the bank 0 500, and the control circuit of the bank 0 processes a command signal input from the A-port, and determines, for example, address information included in the command. And read data from or write data to a cell corresponding to the address information.

Only the B port is accessed by the bank 2 504, and the control circuit of the bank 2 processes the command information input from the B-port.

An X decoder, a Y decoder, and control circuits S0, S1, S2, and S3 are provided for each block of the bank1 502, which is a shared bank, and each control circuit S0, S1, S2, and S3 is provided with an A-port or The B-port accesses. The control circuit of each block of the bank 1 502 allows access of only one port occupied first among the A-port and the B-port, and performs the data occupied operation with the occupied port.

When the A-port occupies block 0 of bank 1 502, the B-port may occupy blocks 1 to 3 of bank 1 to be used. Each block operates independently and independently determines whether to allow access from a particular port.

That is, the A-port and the B-port can simultaneously access the bank 1, which is a shared bank, to read and write data. Therefore, while the A-port reads data from the block 0, the B-port is the A-port. The data to be delivered to can be accessed by writing to block 1. In the conventional case, when the A-port reads data from the shared bank, the B-port was able to write data to the shared bank only after the A-port completed reading data from the shared bank. According to this, it is possible for the A-port and the B-port to simultaneously read and write data in the shared bank.

FIG. 6 illustrates a chip architecture of a dual port memory device among a multi-port memory device including a plurality of shared blocks and including independent input / output power (DQ power) and a clock for each port in a shared bank according to an exemplary embodiment of the present invention. It is a figure which shows an example of a (chip architecture).

Referring to FIG. 6, a dual port memory device according to an exemplary embodiment of the present invention includes an A-port dedicated bank 630, a shared bank 632, two B-port dedicated banks 634 and 636, and a common core. Power (600, 602), I / O power (610, 612) on ports A and B, I / O pins (620, 622) on ports A and B, and clock, control, and address pins (640, 642) on ports A and B. The shared bank 632 may include a plurality of blocks 640, 642, 644, 646.

Although FIG. 6 illustrates a dual port memory device accessing a memory bank from two ports, the present invention may be applied to multiple ports accessing a memory bank from two or more ports.

6 illustrates a case in which one bank is allocated to the A-port dedicated bank 630 and two banks are allocated to the B-port dedicated banks 634 and 636. However, this is only an example. It will be apparent to those skilled in the art that the number of dedicated banks allocated to ports and B-ports may vary.

In FIG. 6, although the shared bank 632 includes four blocks 640, 642, 644, and 646, the number of shared blocks may be variously changed to one of 2 ^N. For example, the number of shared blocks may be changed as needed, such as 2, 4, 8, 16, and the like.

In the related art, the shared bank 632 is a bank that can be used by both the A-port and the B-port, but when one of the A-port and the B-port uses the shared bank 632, Shared bank was not available. That is, the B-port could not access the shared bank while the A-port accessed the shared bank and read data. Therefore, the B-port had to wait until the A-port finished using the shared bank before using the shared bank.

Even if the concept of the shared bank 632 is introduced in the related art, for example, according to FIG. 6, the number of banks that can be occupied at the moment is two A-ports (A-port dedicated bank and shared bank). There are 2 B-Ports (2 B-Port Dedicated Banks), and 1 A-Port (A-Dedicated Bank) has 3 B-Ports (Shared Bank and 2 B-Port Dedicated Banks). There was a problem of being limited to).

Therefore, this problem can be solved by increasing the number of banks. However, since the JEDEC standard only allocates 2 bits for the bank address, there is a problem in that more than four banks cannot be used.

According to a preferred embodiment of the present invention, a plurality of independently accessible blocks 210, 212, 214, and 216 are provided in a shared bank to solve this conventional problem.

For example, according to FIG. 6, the actual number of banks that can be occupied instantaneously includes two A-ports (A-port dedicated bank 630 and block 0 632 of shared banks). 5 (2 B-port dedicated banks (634, 636), and blocks (642, 644, 646) except for block 0 of the shared banks), even though the A-port occupies block 0 (640) in the shared bank. In addition, the B-port can independently access blocks 642, 644, and 646 except for block 0.

In the related art, although a bank in which a A-port and a B-port can be occupied instantaneously in a dual port memory device has been limited, according to a preferred embodiment of the present invention, an effect of substantially increasing a bank under the standard of JEDEC can be obtained. .

At this time, if there is a shared bank having a plurality of independently accessible blocks (610, 612, 614, 616), if the input and output power (DQ power) and the clock is common, the A-port and B-port to different applications There was a problem in that it is more limited to execute an independent command in the corresponding area.

For example, in the case of a common clock in an SDRAM having a shared bank having a plurality of blocks 616, 612, 614, and 616, the SDRAM is a synchronous DRAM, so when the reference clock rises, it reads the state of each pin. The point of operation based on the information has been described above.

For example, if the reference clock is 5 ms (that is, the reference clock rises once every 5 ms), the A-port and B-port are common, and the A-port accesses block 0 640 of the shared bank. When accessing block 1 when the B-port is 12ms to execute independent command according to different application while recording data, the reference clock is increased to 15ms to read the status of each pin per port. There is a threshold to wait until you do. Therefore, in this case, since the shared bank 632 has a plurality of blocks independently accessible by port, the bank has a common existing clock for each port despite the effect of increasing the bank under the JEDEC standard. The limitation is that there is a delay in time.

In this case, in a multi-port memory device having a shared bank having a plurality of blocks independently accessible by each port, a time delay may occur more than an example of the dual port memory device when a common existing clock is provided for each port.

According to a preferred embodiment of the present invention, independent clocks 650 and 652 are provided for each A-port and B-port. In this example, the B-port is configured to perform independent commands in a corresponding region from different applications. With an independent clock 652, at 12 ms with no delay of 3 ms, one can immediately access block 1 and execute the command.

According to a preferred embodiment of the present invention, the shared bank has a plurality of blocks that can be independently accessed for each port, with the effect of increasing the bank, and having an independent reference clock for performing instructions according to different applications for each port. The command can be executed independently without delay.

For example, A-port 650 executes an independent command in the region from a1 application at block 0 640 with t1 clock, and B-port 652 at block 1642 with t2 clock. In the case of executing an independent command in the corresponding area from an application b1, the B-port 642 needs to execute an independent command in the corresponding area from another application (for example, the b2 application) in block 2 (644). The B-port 652 may execute an independent command in a corresponding region as a t3 clock for a b2 application.

At this time, when the application of the A-port 650 is changed, the clock of the A-port may also be changed to the clock for the application of the A-port 650 is changed.

In addition, in a multi-port memory device including a shared bank having a plurality of blocks independently accessible for each port, efficient management of power when having common input / output power (common DQ power) is a problem.

For example, in the prior art, in the dual port memory device, only two dedicated banks 634 and 636 can be accessed while the A-port is accessing the shared bank 632.

However, if the shared bank 632 has four blocks 640, 642, 644, and 646 that are independently accessible by port, the A-port accesses block 0 640 to read a record, for example. In the meantime, the B-Port can access blocks 1 to 3 (642, 644, 646).

At this time, there was an effect of substantially increasing the number of banks accessible by the B-port than in the prior art. Accordingly, independent command execution according to different applications of the B-port may be smoother in the corresponding area.

In this case, in case of having a common input / output power (common DQ power) for each port, for example, even though the B-port has a low current and executes a low speed command, the corresponding input of the common input / output power (common DQ power) is used. It consumes much, causing a problem in power efficiency.

For example, the A-port's input / output power (DQ power) and the B-port's input / output power (DQ power) are in common at 3.3 volts, the core power is 3.3 volts, and the A-port must perform high speed commands. When the low speed command must be executed in the B-port, the common input / output power (common DQ power) is used. Therefore, the A-port and the B-port have no difference in terms of current or speed.

At this time, although the B-port can perform a low speed command with a low input / output power (DQ power), in the above example, as in the A-port, there is a problem of consuming power while having a high current.

According to a preferred embodiment of the present invention, in the execution of an independent command in a corresponding field according to a different application for each port, the shared bank 632 having four blocks 640, 642, 644, and 646 independently accessible for each port. In the memory device having the A-port and the B-port, independent input / output power (DQ power) (610, 612) can be given to each port to maximize the power efficiency according to the speed.

In the above example, the core power 600 is 3.3 volts, and the A-port input / output power DQ power 610 that executes the high speed command is 3.3 volts, and B performs the low speed command. The port input / output power (DQ power) 612 is 1.8 volts to provide independent input / output power (DQ power) for each port, thereby maximizing power efficiency according to the speed.

Accordingly, according to a preferred embodiment of the present invention, the shared bank 632 has four blocks 640, 642, 644, and 646 that are independently accessible, so that the banks have substantially increased effects and independent input / output for each port. By providing power (DQ power) (610, 612) to perform independent commands in the corresponding area by different applications can maximize the efficiency of power according to the speed for each port.

For example, the A-port 620 executes an independent command in the corresponding area from the a1 application with the input / output power of v1 volts at block 0 640, and the B-port 622 at block 1642. In the case of executing an independent command in the corresponding area from the b1 application with the input / output power of v2 volts, the B-port 622 is independent in the corresponding area from another application (for example, the b2 application) in block 2 (644). When the command needs to be executed, the B-port 622 may perform an independent command in a corresponding region with v3 input / output power for a b2 application.

In this case, when the application of the A-port is changed, the input / output power 620 of the A-port may also be changed to the input / output power for the application of the A-port.

Furthermore, even in a multi-port memory device having a plurality of shared banks having a plurality of blocks independently accessible for each port, the number of banks can be substantially increased by a plurality of blocks, and can be independent in a corresponding area by different applications for each port. In performing the In command, independent input / output power (DQ power) is provided for each port according to the speed to smoothly operate various speeds and interfaces for each port, and maximize power efficiency according to the speed.

FIG. 7 includes a plurality of shared blocks 710, 712, 714, and 716 in the shared bank 702 according to the preferred embodiment of the present invention illustrated in FIG. 6, and independent input / output power (DQ power) for each port. And an operation of a dual port memory device among a multi port memory device including a clock.

Referring to FIG. 7, the core power of the A-port and the B-port is 1.8 volts in common, but the input / output power of the A-port is 1.8 volts and the input / output power of the B-port (DQ power). ) Is independent of 3.3 volts. The clock of the A-port and the clock of the B-port are also independent as shown in FIG.

At this time, if the reference clock rises in SDRAM, the pin information is executed and the commands are executed for each port.In addition, the reference clocks of the A-port and B-port not only have different periods, but also the first of the reference clock in the A-port. The write command is executed at the first rise, and the read command is performed at the second rise of the reference clock in the B-port. Therefore, according to the present invention, it is possible to perform an independent command in a corresponding area from a different application for each port.

In this case, according to FIG. 7, the shared bank 702 has four divided blocks 710, 712, 714, and 716. The four blocks 710 of the shared bank 702 are independently of the A-port and the B-port. , 712, 714, and 716, which have the effect of substantially increasing the number of banks.

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the preferred embodiment of the present invention, as each port performs a different application in the multi-port memory, there is an advantage that the command can be independently performed in the corresponding area without delay.

In addition, according to a preferred embodiment of the present invention, each port in the multi-port memory using a different level of input / output power (DQ power) is possible to perform a smooth operation between the command execution speed and the interface, the independent command execution speed There is an advantage that the efficiency of the power can be maximized.

Further, according to a preferred embodiment of the present invention, by dividing the memory area of the shared bank into a plurality of blocks, each port is commanded in the corresponding area, with the effect that the number of banks is substantially increased while maintaining the number of banks. There is an advantage that can be performed independently.

Claims (14)

A multi-port memory device having two or more ports, At least one dedicated bank to allow access only to specific ports; At least one shared bank to allow access to multiple ports; Input / output pins (DQs pin) through which input / output power (DQ power) is transmitted for each port; And And a clock pin (CLK Pin) for providing a clock (CLK) for each port, wherein the input / output power (DQ power) and the clock (CLK) are independent for each port. The method of claim 1, The shared bank includes a plurality of blocks in which a memory area of a bank is divided into preset units. The multi-port memory device, characterized in that to independently access and use one of the plurality of blocks. The method according to claim 1 or 2, As one or more of the ports-specific applications change, And at least one port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed. The method according to claim 1 or 2, At least one of the ports uses a reference clock of a system in which the multi-port memory device is installed, but among other ports And at least one port having an independent clock corresponding to the application. The method of claim 4, wherein As one or more of the applications for each port are changed, And at least one port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed. The method according to claim 1 or 2, At least one of the ports has input and output power in common with the core power of the multi-port memory device, among other ports And at least one port having independent input and output power corresponding to the application. The method of claim 6, As one or more of the applications for each port are changed, And at least one port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed. A first port dedicated bank to allow access only to the first port; A second port dedicated bank to allow access only to the second port; A shared bank allowing access to the first port and the second port; Input / output pins (DQs pin) through which input / output power (DQ power) is transmitted for each port; And And a clock pin (CLK Pin) for providing a clock (CLK) for each port, wherein the input / output power (DQ power) and the clock (CLK) are independent of each port. The method of claim 8, The shared bank includes a plurality of blocks obtained by dividing a memory area of a bank into predetermined units, and the dual port independently accesses and uses one of the plurality of blocks. The method according to claim 8 or 9, As one or more of the ports-specific applications change, And at least one port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed. The method according to claim 8 or 9, One of the ports uses a reference clock of a system in which the dual port memory device is installed, And a second port having an independent clock corresponding to the application. The method of claim 11, As the port-specific application is changed, And a second port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed. The method according to claim 8 or 9, One of the ports has an input / output power in common with the core power of the dual port memory device, And a second port having independent input / output power corresponding to the application. The method of claim 13, As one or more of the applications for each port are changed, And at least one port in which at least one of the port-specific clock or input / output power corresponding to the changed application is independently changed.

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