KR20030023345A - Rambus dram - Google Patents

Abstract

PURPOSE: A Rambus DRAM is provided to reduce power consumption by controlling a portion to be accessed among a data write control signal and a data read control signal to be operated, thereby simplifying a domain control block at the case of the data read control signal. CONSTITUTION: A Rambus DRAM includes an upper and a lower memory bank block(101) provided with a plurality of unit memory banks(102,103) and a data read/write control signal generation block(107) for controlling the upper memory bank block and the lower memory bank block operated independently each other during the operation of data read/write operation by generating the upper data write control signal and the upper data read control signal from the upper memory bank block and the lower data write control signal and the lower data read control signal from the lower memory bank block.

Description

Rambus DRAM

The present invention relates to a Rambus DRAM, and in particular, to control only the data read / write control signals of a memory bank accessed between an upper memory bank and a lower memory bank to reduce power consumption. It is about Rambus DRAM which can reduce the layout area.

1 is a block diagram of a RAM bus DRAM according to the prior art, in which an upper memory bank portion 1 and a lower memory bank portion 4 having a plurality of memory banks, and the upper and lower memory bank portions 1 and 4 are shown. A data read / write control signal generator 7 for generating a data read / write control signal is shown.

The upper memory bank unit 1 includes a DQA memory bank unit 2 composed of nine unit memory banks S1-S9 controlled by a data signal received through a data input / output pin DQA, and a DQB. A DQB memory bank section 3 composed of nine unit memory banks S1-S9 controlled by a data signal received through a pin is provided.

Similarly, the lower memory bank unit 4 receives the DQA memory bank unit 5 composed of nine unit memory banks S1-S9 controlled by the data signal received through the DQA pin, and the DQB pin. A DQB memory bank section 6 composed of nine unit memory banks S1-S9 controlled by the data signal is provided.

The conventional data read / write control signal generator 7 shown in FIG. 1 transmits the data write control signal writeD0123 (writeD4567) to the upper and lower memory bank units 1 and 4 during the data write operation. It is generated by two unit memory banks and operated simultaneously. In the data read operation, the data read control signal loadRDpipe is generated to each of 36 memory banks irrespective of the upper and lower memory bank units 1 and 4 to operate the upper and lower memory banks simultaneously. Due to this operation, conventional Rambus DRAMs consume a lot of power.

FIG. 2A is a data write transfer circuit diagram controlled by the data write control signal writeD0123 of each unit memory bank shown in FIG. 1, and includes four latch units 11 and one controller 12.

The four latch units 11 latch data received through an input pad (not shown) and transmit the data to a memory cell (not shown), and the control unit 12 receives a write data control signal writeD0123. To generate a signal for controlling the operations of the four latch units 11.

FIG. 2B is a data write transfer circuit diagram controlled by the data write control signal writeD4567 of each unit memory bank shown in FIG. 1, and is composed of eight latch units 13 and one controller 14.

The eight latch units 13 latch data received through a pad (not shown) and transmit the data to a memory cell (not shown), and the controller 14 receives a data write control signal writeD4567. A signal for controlling the operations of the eight latch sections 13 is generated.

FIG. 3A is a data read transfer circuit diagram controlled by the data read control signal loadRDpip of each memory bank shown in FIG. 1, and is composed of eight latch units 15 and one controller 16.

The eight latch units 15 transmit data received from a memory cell (not shown) to a pad (not shown), and the control unit 16 receives a data read control signal loadRDpipe. A signal for controlling the operation of the latch unit 15 is generated.

FIG. 3B is a data read transfer circuit diagram controlled by the data read control signal drainRDpipe of each memory bank shown in FIG. 1, and is composed of eight latch units 17 and one control unit 16.

The eight latch units 17 latch data received from a memory cell (not shown) and transmit the data to a pad (not shown), and the control unit 16 receives a data read control signal drainRDpipe. A signal for controlling the operation of the eight latch sections 17 is generated.

FIG. 4A is a waveform diagram of a conventional data write control signal including an external clock rclk, an upper memory enable clock sclk_en_top, a lower memory enable clock sclk_en_bot, a pre data write signal writeD0123_pre, and a pre data write signal writeD4567_pre, a data write control signal writeD0123 and a data write control signal writeD4567 are shown.

The first clock of the data write control signal writeD0123 and the data write control signal writeD4567 is a signal for operating the upper memory bank, and a second clock is a signal for operating the lower memory bank. Upper and lower memory banks are formed by the data write control signal writeD0123 and the data write control signal writeD4567 in a section 5-c where the upper memory enable clock sclk_en_top and the lower memory enable clock sclk_en_bot overlap. Are operated simultaneously.

FIG. 4B is a conventional data write control signal generation circuit diagram, which shows a data write control signal writeD0123 generator 21 and a data write control signal writeD4567 generator 23. As shown in FIG.

The data write control signal writeD0123 generator 21 includes two inverters 23 and 24 connected in series with the first pre data write generator 22. The first pre data write generator 22 generates a pre data write signal writeD0123_pre, and the two inverters 23 and 24 receive the pre data write signal writeD0123_pre to receive a data write control signal writeD0123).

The data write control signal writeD4567 generator 25 includes two inverters 27 and 28 connected in series with the second free data write generator 26. The second pre data write generator 26 generates a pre data write signal writeD4567_pre, and the two inverters 27 and 28 receive the pre data write signal writeD4567_pre to receive the data write control signal writeD4567).

5A is a waveform diagram of a conventional data read control signal loadRDpipe, in which an external clock rclk, a pre data read signal loadRDpipe_pre, and a data read control signal loadRDpipe are shown. The data read control signal loadRDpipe includes clock signals for accessing the upper and lower memory banks in the period 8-c of the external clock rclk.

FIG. 5B is a conventional circuit diagram for generating a data read control signal loadRDpipe and includes two inverters 32 and 33 connected in series with the predata read generator 31.

The pre data read generator 31 generates a pre data read signal loadRDpipe_pre, and the two inverters 32 and 33 receive the pre data write signal loadRDpipe_pre to receive a data read control signal loadRDpipe. Occurs.

5C is a waveform diagram of a conventional data read control signal drainRDpipe, and includes an external clock rclk, a domain control block signal load_out, an upper bank select signal top_bank_sel, a lower bank select signal bot_bank_bank_sel, and a lower data read. The clock signal load_outpipe_bot, the upper data read clock signal load_outpipe_top, the lower data read control signal drainRDpipe_bot, and the upper data read control signal drainRDpipe_top are shown.

The lower data read control signal drainRDpipe_bot is generated by the lower data read clock signal load_outpipe_bot, and the upper data read control signal drainRDpipe_top is generated by the upper data read clock signal load_outpipe_top.

The lower data read clock signal load_outpipe_bot and the upper data read clock signal load_outpipe_top are generated by the domain control block signal load_out.

FIG. 5D is a circuit diagram of a conventional data read control signal (drainRDpipe) and includes an upper data read control signal including a domain controller 41, two inverters 42 and 43, and an upper data read control signal generator 44. (drainRDpipe_top) generating circuit section 40, domain control section 51, two inverters 52, 53, upper data read control signal generating section 54 consisting of a lower data read control signal (drainRDpipe_bot) generating circuit section ( 50).

The upper data read control signal drainRDpipe_top generation circuit 40 receives the domain control block signal load_out according to the upper bank select signal top_bank_sel and outputs a pre-data read clock signal load_outpipe_pre. ), Two inverters 42 and 43 connected in series for receiving the output signal load_outpipe_pre of the domain controller 41 and outputting the upper data read clock signal load_outpipe_top, and the inverter 43 An upper data read control signal generator 44 for receiving an output signal load_outpipe_top and outputting an upper data read control signal drainRDpipe_top is provided.

The lower data read control signal drainRDpipe_bot generation circuit unit 50 receives the domain control block signal load_out according to the lower bank select signal bot_bank_sel and outputs a pre-data read clock signal load_outpipe_pre. ), Two inverters 52 and 53 connected in series to receive the output signal load_outpipe_pre of the domain controller 51 and output the lower data read clock signal load_outpipe_bot, and the inverter 53 A lower data read control signal generator 54 for receiving an output signal load_outpipe_bot and outputting a lower data read control signal drainRDpipe_bot is provided.

However, in the conventional Rambus DRAM configured as described above, when data is written to the upper memory bank, the data write control signal writeD0123 (writeD4567) toggles to simultaneously operate both the data write paths of the upper and lower memory banks. Even when reading the data of the upper memory bank unit, the data read control signal loadRDpipe is toggled to operate the data read paths of the upper and lower memory banks, thereby consuming a lot of power.

In addition, although the conventional data read control signal (drainRDpipe) path operates by dividing the upper and lower memory banks, the operation of the data read control signal (drainRDpipe) is generated by each block path as shown in FIG. 5D and the circuit of the domain controller is complicated to consume power. There was a problem in that many occupy the layout area.

Accordingly, an object of the present invention is to solve the above problems, and an object of the present invention is to control the operation of only the data read / write control signal of a memory bank accessed from an upper memory bank and a lower memory bank. It is to provide Rambus DRAM with reduced consumption and optimized layout area.

1 is a block diagram of a Rambus DRAM according to the prior art.

FIG. 2A is a data write transfer circuit diagram controlled by the data write control signal writeD0123 of each memory bank shown in FIG.

FIG. 2B is a data write transfer circuit diagram controlled by the data write control signal writeD4567 of each memory bank shown in FIG.

3A is a data read transfer circuit diagram controlled by a data read control signal loadRDpip of each memory bank shown in FIG. 1.

FIG. 3B is a data read transfer circuit diagram controlled by a data read control signal drainRDpipe of each memory bank shown in FIG. 1.

4A is a waveform diagram of a conventional data write control signal.

Figure 4b is a conventional data write control signal generation circuit diagram

5A is a waveform diagram of a conventional data read control signal loadRDpipe.

5B is a circuit diagram of a conventional data read control signal loadRDpipe.

5C is a waveform diagram of a conventional data read control signal drainRDpipe.

FIG. 5D is a circuit diagram of a conventional data read control signal drainRDpipe.

6 is a block diagram of a Rambus DRAM according to the present invention.

7A is a waveform diagram of a data write control signal used in the present invention.

7B is a circuit diagram of a data write control signal generation used in the present invention.

7C is a circuit diagram of a data write enable signal generation used in the present invention.

8A is a waveform diagram of a data read control signal loadRDpipe used in the present invention.

8B is a circuit diagram of a data read control signal loadRDpipe used in the present invention.

FIG. 8C is a circuit diagram of upper and lower bank selection signal generation shown in FIG. 8B.

8D is a waveform diagram of a data read control signal drainRDpipe according to the present invention.

8E is a circuit diagram of upper and lower data read control signal generation used in the present invention.

Explanation of symbols on the main parts of the drawings

101: upper memory bank section 102: DQA memory bank section

103: DQB memory bank section 104: lower memory bank section

105: DQA memory bank section 106: DQB memory bank section

107: data read / write control signal generator

In order to achieve the above object, the Rambus DRAM of the present invention generates an upper data write control signal and an upper data read control signal to the upper and lower memory bank parts including a plurality of unit memory banks, and the lower memory bank parts. A data read / write control signal generator for generating a lower data write control signal and a lower data read control signal to a memory bank to control the upper memory bank unit and the lower memory bank unit independently during data read / write operation. It is characterized by one.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

FIG. 6 is a block diagram of a Rambus DRAM according to the present invention, in which an upper memory bank unit 101 and a lower memory bank unit 104 having a plurality of memory banks, and upper data banks are written to the upper memory bank unit 101. A control signal (writeD0123_top) (writeD4567_top) and an upper data read control signal (loadRDpipe_top) (drainRDpipe_top) are generated and a lower data write control signal (writeD0123_bot) (writeD4567_bot) and a lower data read control signal (write) to the lower memory bank unit 104. a data read / write control signal generator 107 which generates loadRDpipe_bot) to control only one of the upper memory bank 101 and the lower memory bank 104 to operate during a data read / write operation. Equipped.

The upper memory bank unit 101 includes a DQA memory bank unit 102 composed of nine unit memory banks S1-S9 controlled by a data signal received through a data input / output pin DQA, and a DQB. A DQB memory bank unit 103 composed of nine unit memory banks S1-S9 controlled by a data signal received through a pin is provided.

Similarly, the lower memory bank unit 104 also receives the DQA memory bank unit 105 including nine unit memory banks S1-S9 controlled by the data signal received through the DQA pin, and the DQB pin. And a DQB memory bank section 106 composed of nine unit memory banks S1-S9 controlled by the data signal.

The Rambus DRAM of the present invention operates only the data write / read path of the upper memory bank unit 101 when accessing the memory cells of the upper memory bank unit 101, and lowers the memory cells of the lower memory bank unit 101 when accessing the memory cells of the lower memory bank unit 101. Only the data write / read path of the memory bank unit 104 is operated. To this end, the conventional data write control signal writeD0123, which has been commonly input to the upper and lower memory banks, is divided into the upper data write control signal writeD0123_top and the lower data write control signal writeD0123_bot, so that the upper memory bank unit 101 is separated. And the lower memory bank section 104 operate independently. Similarly, the data write control signal writeD4567 is converted into the upper data write control signal writeD4567_top and the lower data write control signal writeD4567_bot, and the data read control signal loadRDpipe is the upper data read control signal loadRDpipe_top and the lower data read control. The upper memory bank unit 101 and the lower memory bank unit 104 operate independently by separating the signal loadRDpipe_bot.

Fig. 7A is a waveform diagram of a data write control signal according to the present invention, showing a case where data is written to the upper memory bank section 101 and immediately written to the lower memory bank section 104 in succession.

As shown in FIG. 7A, a time point when the upper write enable signal write_en_top is enabled as 'high' in the 'high' section of the upper write clock signal sclk_en_top enabled during the write command of the upper memory bank unit 101 is shown. The upper data write control signal writeD0123_top is generated and the lower data write control signal write_en_bot is enabled in the 'high' section of the lower write clock signal sclk_en_bot at 'high'. writeD0123_bot) is generated. The upper data write control signal writeD4567_top is generated after a period of the clock rclk after the upper data write control signal writeD0123_top is generated, and the lower data write control signal writeD4567_bot is generated by the lower data write control signal ( It occurs after one period of clock rclk after writeD0123_bot.

That is, the upper data write control signals writeD0123_top and writeD4567_top and the lower data write control signals writeD0123_bot and writeD4567_bot are conventional data write control signals using the upper write clock signal sclk_en_top and the lower write clock signal sclk_en_bot. writeD0123_pre, writeD4567_pre).

If the upper and lower write clock signals sclk_en_top and sclk_en_bot are used as they are, the upper and lower portions of the upper and lower write clock signals sclk_en_top and the lower write clock signals sclk_en_bot are operated simultaneously as in the conventional Rambus DRAM. . In order to prevent this, as shown in FIG. 7C, an upper data write enable signal write_en_top and a lower data write enable signal write_en_bot are generated using a flip-flop and a 2-input NAND gate, so that the data write control signal writeD0123 is on top. Alternatively, only the interval for accessing the lower memory bank is enabled.

In FIG. 7A, the first pulse section (8-9 sections based on the clock) of the data write control signal writeD0123_pre and the first pulse section (ab sections based on the clock) of the data write control signal writeD4567_pre correspond to the upper memory bank. A data write control signal to be accessed, each second pulse is a data write control signal to access the lower memory bank.

In addition to the waveforms illustrated in FIG. 7A, even when the upper memory bank is accessed after the lower memory bank is accessed or not continuously, only the control signals to be accessed can be operated as described above, thereby reducing power consumption by half. .

FIG. 7B is a circuit diagram of a data write control signal generation according to the present invention, and includes a NAND gate 111 for inputting two upper data write enable signals write_en_top and a data write control signal writeD0123_pre, and the NAND gate 111 of FIG. An inverter 112 for inverting the output signal to generate the upper data write control signal writeD0123_top, a NAND gate 113 for inputting the lower data write enable signal write_en_bot and the data write control signal writeD0123_pre; And an inverter 114 for inverting the output signal of the NAND gate 113 to generate a lower data write control signal writeD0123_bot. In addition, the NAND gate 116 for inputting the upper data write enable signal write_en_top and the data write control signal writeD4567_pre, and the output signal of the NAND gate 116 are inverted to write the upper data write control signal writeD4567_top. Inverter 117 for generating a signal, a NAND gate 118 for inputting the lower data write enable signal write_en_bot and the data write control signal writeD4567_pre, and an output signal of the NAND gate 118 are inverted. The inverter 119 generates a lower data write control signal writeD4567_bot.

7C is a circuit diagram of a data write enable signal generation according to an embodiment of the present invention, including a flip-flop 121 for inputting an upper write clock signal sclk_en_top and a clock signal rclk, an output signal of the flip-flop 121, and A flip-flop 122 for inputting a clock signal rclk, an output signal of the flip-flop 122, a flip-flop 123 for inputting the clock signal rclk, and an output signal of the flip-flop 123 And a flip-flop 124 for inputting the clock signal rclk, a flip-flop 125 for inputting the output signal of the flip-flop 124 and the clock signal rclk, and a flip-flop 125 of the flip-flop 125. The upper data write enable using the flip-flop 126 for inputting the output signal and the clock signal rclk, and the output signal sclk_en_top_6f of the upper write clock signal sclk_en_top and the flip-flop 126 as two inputs. The NAND gate 127 generates a signal write_top. In addition, the flip-flop 128 for inputting the lower write clock signal sclk_en_bot and the clock signal rclk, the flip-flop 129 for inputting the output signal of the flip-flop 128 and the clock signal rclk, A flip-flop 130 for inputting the output signal of the flip-flop 129 and the clock signal rclk, and a flip-flop 131 for inputting the output signal of the flip-flop 130 and the clock signal rclk. ), A flip-flop 132 for inputting the output signal of the flip-flop 131 and the clock signal rclk, and a flip-flop for inputting the output signal and the clock signal rclk of the flip-flop 132. 133 and a NAND gate 134 for generating a lower data write enable signal write_bot by using the lower write clock signal sclk_en_bot and the output signal sclk_en_bot_6f of the flip-flop 133 as two inputs. do.

Next, the operation and configuration of the data read control signal will be described with reference to FIGS. 8A to 8E.

First, FIG. 8A is a waveform diagram of a data read control signal loadRDpipe according to the present invention, which shows a case where data of an upper memory bank is immediately read after first reading data of a lower memory bank.

The lower data read control signal loadRDpipe_bot and the upper data read control signal loadRDpipe_top are generated by being separated from the conventional data read control signal loadRDpipe using the lower bank select signal bot_bank_sel_4f and the upper bank select signal top_bank_sel_4f. will be.

As shown in FIG. 8C, the upper bank select signal top_bank_sel_4f and the lower bank select signal bot_bank_sel_4f are generated by using a flip-flop and an inverter so that the data read control signal loadRDpipe is enabled only in a section where the upper and lower data access signals are accessed. do.

In FIG. 8A, the first pulse section (8-9 sections based on the clock signal) of the conventional data read control signal loadRDpipe is a data read control signal that accesses the lower memory bank, and the second pulse section (based on the clock signal). cd interval) is a data read control signal for accessing the upper memory bank.

8B is a circuit diagram of a data read control signal loadRDpipe according to the present invention, including a NAND gate 141 for inputting two upper bank select signals top_bank_sel_4f and a data read control signal loadRDpipe_pre, and the NAND gate 141. An inverter 142 that inverts an output signal of the upper data read control signal loadRDpipe_top, a NAND gate 143 that inputs two lower bank select signals bot_bank_sel_4f and a data read control signal loadRDpipe_pre, and An inverter 144 for inverting the output signal of the NAND gate 143 to generate the lower data read control signal loadRDpipe_bot is provided.

FIG. 8C is a circuit diagram for generating the upper and lower bank selection signals shown in FIG. 8B. The flip-flop 151 for inputting the top bank selection signal top_bank_sel and the clock signal rclk, and the output signal of the flip-flop 151 is shown in FIG. And a flip-flop 152 for inputting the clock signal rclk, a flip-flop 153 for inputting the output signal of the flip-flop 152 and the clock signal rclk, and a flip-flop 153 A flip-flop 154 for inputting an output signal and the clock signal rclk to generate an upper bank selection signal top_bank_sel_f4, and a lower bank for inputting an upper bank selection signal top_bank_sel_f4 outputted from the flip-flop 154; An inverter 156 for generating a selection signal bot_bank_sel_f4 and an inverter 155 for inputting an upper bank selection signal top_bank_sel_2f output from the flip-flop 152 to generate a lower bank selection signal bot_bank_sel_2f. .

FIG. 8D is a waveform diagram of the data read control signal drainRDpipe according to the present invention, wherein the lower data read control signal drainRDpipe_bot is generated by the lower data read clock signal load_outpipe_bot and the upper data read control signal drainRDpipe_top. Is generated by the upper data read clock signal load_outpipe_top. The lower data read clock signal load_outpipe_bot and the upper data read clock signal load_outpipe_top are generated by the domain control block signal load_out.

FIG. 8E is a circuit diagram for generating upper and lower data read control signals drainRDpipe_top and drainRDpipe_bot used in the present invention, and includes two NAND gates 161 for inputting the upper bank select signal top_bank_sel_2f and the data read clock signal load_outpipe_pre. The inverter 162 receives the output signal of the NAND gate 161 and outputs the upper data read clock signal load_outpipe_top, and receives the upper data read clock signal load_outpipe_top output from the inverter 162. An upper data read control signal generator 163 for generating an upper data read control signal drainRDpipe_top, a NAND gate 164 for inputting two lower bank select signals bot_bank_sel_2f and a data read clock signal load_outpipe_pre; An inverter 165 that receives an output signal of a NAND gate 164 and outputs the lower data read clock signal load_outpipe_bot, and to the inverter 165. The lower data read control signal generator 166 is configured to receive the lower data read clock signal load_outpipe_bot and to generate the lower data read control signal drainRDpipe_bot.

As described above, the Rambus DRAM according to the present invention controls the data write control signal writeD0123 (writeD4567) and the data read control signal loadRDpipe to operate only the portion of the upper memory bank and the lower memory bank to be accessed. Power consumption can be reduced. In addition, in the case of a data read control signal (drainRDpipe) path, a domain control block can be simplified, and by using only one block of the data read control signal (loadRDpipe), the power consumption can be reduced and the layout area can be reduced. There is this.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (10)

For Rambus DRAM, An upper and lower memory bank unit having a plurality of unit memory banks; The upper memory bank unit generates an upper data write control signal and an upper data read control signal, and generates a lower data write control signal and a lower data read control signal to the lower memory bank unit. And a data read / write control signal generator for controlling the lower memory bank units to operate independently of each other. The method of claim 1, The upper memory bank unit, An upper DQA memory bank portion consisting of nine unit memory banks controlled by a data signal received via a deq (DQ) pin A (A), An upper DQB memory bank portion consisting of nine unit memory banks controlled by a data signal received via a deq (DQ) pin ratio (B), The lower memory bank unit, A lower DQA memory bank portion consisting of nine unit memory banks controlled by a data signal received via a deq (DQ) pin A; Rambus DRAM comprising a lower DQB memory bank portion consisting of nine unit memory banks controlled by a data signal received through a deq (DQ) pin ratio (B). The method of claim 1, wherein the data write control signal generator, The data write control signal writeD0123 is received and separated into an upper data write control signal writeD0123_top and a lower data write control signal writeD0123_bot by the upper data write enable signal write_en_top and the lower data write enable signal write_en_bot. A first data write control signal generator, The data write control signal writeD4567 is received and the upper data write control signal writeD4567_top and the lower data write control signal writeD4567_bot are generated by the upper data write enable signal write_en_top and the lower data write enable signal write_en_bot. And a second data write control signal generator that is generated by separating the signals. The method of claim 3, wherein the first data write control signal generator, A first NAND gate configured to input two upper data write enable signals write_en_top and data write control signals writeD0123_pre; A first inverter for inverting an output signal of the first NAND gate to generate an upper data write control signal writeD0123_top; A second NAND gate configured to input two lower data write enable signals write_en_bot and the data write control signal writeD0123_pre; And a second inverter configured to invert an output signal of the second NAND gate to generate a lower data write control signal (writeD0123_bot). The method of claim 3, wherein the second data write control signal generator, A third NAND gate configured to input two upper data write enable signals write_en_top and data write control signals writeD4567_pre; A third inverter for inverting the output signal of the third NAND gate to generate an upper data write control signal writeD4567_top; A fourth NAND gate configured to input two lower data write enable signals write_en_bot and two data write control signals writeD4567_pre; And a fourth inverter configured to invert the output signal of the fourth NAND gate to generate a lower data write control signal (writeD4567_bot). The method of claim 5, wherein the upper data write enable signal generation unit, A first flip-flop for inputting an upper write clock signal sclk_en_top and a clock signal rclk, a second flip-flop for inputting an output signal of the first flip-flop and the clock signal rclk, and the second flip-flop A third flip-flop for inputting an output signal of the flop and the clock signal rclk, a fourth flip-flop for inputting the output signal of the third flip-flop and the clock signal rclk, and a fourth flip-flop of the fourth flip-flop A fifth flip-flop for inputting an output signal and the clock signal rclk, a sixth flip-flop for inputting the output signal of the fifth flip-flop and the clock signal rclk, and the upper write clock signal sclk_en_top And a fifth NAND gate configured to generate the upper data write enable signal (write_top) by using the output signal of the sixth flip-flop as two inputs. The method of claim 5, wherein the lower data write enable signal generator, A seventh flip-flop for inputting the lower write clock signal sclk_en_bot and the clock signal rclk, an eighth flip-flop for inputting the output signal of the seventh flip-flop, and the clock signal rclk, and the eighth flip-flop A ninth flip-flop for inputting an output signal of the flop and the clock signal rclk, a tenth flip-flop for inputting the output signal of the ninth flip-flop and the clock signal rclk, An eleventh flip-flop for inputting an output signal and the clock signal rclk, a twelfth flip-flop for inputting the output signal of the eleventh flip-flop and the clock signal rclk, and the lower write clock signal sclk_en_bot And a sixth NAND gate configured to generate the lower data write enable signal (write_bot) by using the output signal of the twelfth flip-flop as two inputs. The method of claim 1, wherein the data read control signal generator, A seventh NAND gate for inputting the upper bank selection signal top_bank_sel_4f and the data read control signal loadRDpipe_pre, and a fifth for inverting the output signal of the seventh NAND gate to generate the upper data read control signal loadRDpipe_top With inverter, An eighth NAND gate for inputting the lower bank selection signal bot_bank_sel_4f and the data read control signal loadRDpipe_pre, and a sixth inverter for inverting the output signal of the eighth NAND gate to generate the lower data read control signal loadRDpipe_bot Rambus DRAM characterized in that provided with. The method of claim 8, The circuit for generating the upper bank selection signal top_bank_sel_4f and the lower bank selection signal bot_bank_sel_4f includes: A thirteenth flip-flop for inputting an upper bank selection signal top_bank_sel and a clock signal rclk, a fourteenth flip-flop for inputting an output signal of the thirteenth flip-flop and the clock signal rclk, and a fourteenth flip-flop A fifteenth flip-flop for inputting an output signal of the flop and the clock signal rclk, and a sixteenth flip-flop for outputting the output signal of the fifteenth flip-flop and the clock signal rclk to generate an upper bank selection signal top_bank_sel_f4 A seventh inverter for inputting a flip-flop, an upper bank selection signal top_bank_sel_f4 output from the sixteenth flip-flop to generate a lower bank selection signal bot_bank_sel_f4, and an upper bank selection signal output from the fourteenth flip-flop and an eighth inverter configured to input top_bank_sel_2f to generate a lower bank selection signal bot_bank_sel_2f. The method of claim 9, The circuit for generating the upper and lower data read control signals, A ninth NAND gate configured to input the upper bank select signal top_bank_sel_2f and the data read clock signal load_outpipe_pre, and a ninth NAND gate configured to receive the output signal of the ninth NAND gate and output the upper data read clock signal load_outpipe_top. An upper data read control signal generator configured to receive an upper data read clock signal load_outpipe_top output from the ninth inverter and generate an upper data read control signal drainRDpipe_top; A tenth NAND gate for inputting the lower bank selection signal bot_bank_sel_2f and the data read clock signal load_outpipe_pre, and a tenth for receiving the output signal of the tenth NAND gate and outputting the lower data read clock signal load_outpipe_bot And an inverter and a lower data read control signal generator configured to receive the lower data read clock signal (load_outpipe_bot) output from the tenth inverter and generate a lower data read control signal (drainRDpipe_bot).