KR100931703B1 - Multiprocessor data transfer method using multi-port memory, recording medium recording packet structure, multi-processor data transfer protocol using multi-port memory, and multi-processor system - Google Patents

Abstract

A multiprocessor data transmission method using multi-port memory that can provide data transfer compatibility among multiple processors, a recording medium recording a packet structure, a multi-processor data transmission protocol using multi-port memory, and a multi-port memory A multiprocessor system is disclosed. A multiprocessor data transmission method using a multiport memory includes generating a packet by adding a header to a data generated by a first task executed in a first processor based on a predetermined protocol, and generating the packet by using the multiport memory. Storing in a shared memory area. Thus, compatibility in data transfer between multiple processors using multi-port memories can be provided.

Multiport Memory, Dualport Memory, Processor, Protocol, Packet, Header

Description

Multi-processor data transmission method using multi-port memory, recording medium recording packet structure, multi-processor data transmission protocol using multi-port memory and multi-port memory Using Multi-port Memory, Recorded Medium For Storing Packet Structure, Data Communication Protocol For Multi-processor System Using Multi-port Memory And Multi-processor System Having Multi-port Memory}

The present invention relates to a multi-processor system having a multi-port memory, and more particularly, to a multi-processor data transmission method using a multi-port memory that can maintain the compatibility of data transfer between the multi-processor, a recording medium in which the packet structure is recorded The present invention relates to a multiprocessor data transfer protocol using a multi-port memory and a multi-port memory.

Recently, portable terminals such as mobile communication terminals and PDAs (Personal Digital Assistants) have various additional application services such as image and video recording, video calling, mobile Internet, and multimedia data playback in addition to wireless communication functions such as voice calls. To this end, a separate processor is included in addition to a processor that performs overall control of the wireless communication and the portable terminal.

That is, recent portable terminals include a baseband processor for performing the original functions of the mobile communication and an application processor for performing various additional applications.

In addition, as described above, in a multiprocessor system having two processors, data is transmitted and received using a dual port memory having two ports. That is, a processor generating data transmits the generated data to a shared memory area of the dual port memory using its own port, and a processor performing a predetermined process using the data stores data stored in the shared memory area. Read out and perform the process.

Since there is no separate standardized communication protocol in the communication between the processors using the conventional dual port memory as described above, the manufacturer of each processor and the manufacturer of the dual port memory use the processor and the dual port memory based on different criteria or definitions. In this case, there is a disadvantage in that the data communication between the processors becomes incompatible.

Accordingly, a first object of the present invention is to provide a data transfer method of a multiprocessor using a multi-port memory capable of providing data transfer compatibility among multiple processors.

It is also a second object of the present invention to provide a recording medium in which a structure of a packet is recorded, which can provide compatibility of data transmission between multiple processors.

In addition, a third object of the present invention is to provide a data transfer protocol of a multiprocessor using a multi-port memory that can provide compatibility of data transfer between multiple processors.

It is also a fourth object of the present invention to provide a multiprocessor system having a multi-port memory capable of providing data transfer compatibility between multiple processors.

According to an aspect of the present invention, there is provided a data transmission method of a multiprocessor using a multi-port memory according to an aspect of the present invention. Adding a header to generate a packet and storing the generated packet in a shared memory area of the multi-port memory. The multiprocessor data transmission method using the multi-port memory may include: reading, by the second processor, a packet stored in the shared memory area; and extracting the data by parsing the read packet by the second processor. The method may further include providing the extracted data to a second task by the second processor. The header may include at least one of transmission task information indicating information of the first task for generating the data and reception task information indicating information of the second task for receiving the data. The header may include an interface type of the multi-port memory, information of the first processor transmitting the data, information of the second processor receiving the data, information indicating the start of the data transmission, and bandwidth of the multi-port memory. Information indicating the manufacturer, information indicating the manufacturer of the multi-port memory, information indicating the size of the multi-port memory, and information indicating whether a shared memory area exists. The header may include at least one of semaphore control information for synchronizing access to the shared memory area between the first processor and the second processor, and preliminary information for emergency transmission and retransmission of the data. The header is a unit of one of a start address information and an end address information of a shared memory area shared by the first task and the second task, and data generated by any one of the first task and the second task. It may include at least one piece of information about the session that is a set of data to be processed. The header may include at least one of information on the data encryption method, information on a modulation method, and information on a type of an application generating or consuming the data. The storing of the generated packet in the shared memory area of the multi-port memory may include obtaining an access right to the shared memory area, storing the packet in the shared memory area and the shared memory area. It may include the step of releasing access to the.

In addition, a recording medium in which a structure of a packet is recorded according to an aspect of the present invention for achieving the above-described second object of the present invention, wherein the packet includes a header and the data, wherein the header is configured to generate the data. And at least one of transmission task information indicating information of one task and information of a reception task indicating information of a second task that receives the data. The header may include an interface type of the multi-port memory, information of a processor transmitting the data, information of a processor receiving the data, information indicating the start of transmission of the data, information indicating a bandwidth of the multi-port memory, the multiple It may include at least one of information indicating the manufacturer of the port memory, information indicating the size of the multi-port memory and information indicating the presence or absence of a shared memory region. The header may further include a synchronization layer header including semaphore control information for synchronizing access to the shared memory region by the at least one processor and preliminary information for emergency transmission and retransmission of the data.

In addition, in the data transfer protocol of a multiprocessor using a multi-port memory according to an aspect of the present invention for achieving the third object of the present invention, at least one processor is configured to transmit the data through a packet consisting of a header and data In exchange, the header includes at least one of transmission task information indicating information of a first task generating the data and reception task information indicating information of a second task receiving the data. The header is an interface type of the multi-port memory, information of the processor transmitting the data, information of the processor receiving the data, information indicating the start of data transmission, information indicating the bandwidth of the multi-port memory, the multi-port memory The link layer header may further include a link layer header including at least one of information indicating a manufacturer, information indicating a size of the multi-port memory, and presence or absence of a shared memory region. The header may further include a synchronization layer header including at least one of semaphore control information for synchronizing access to the shared memory area, and preliminary information for emergency transmission and retransmission of the data. Can be.

In addition, a multi-processor system having a multi-port memory according to an aspect of the present invention for achieving the fourth object of the present invention described above is provided in a multi-port memory, shared memory commonly used by the first processor and the second processor An area, and receives data generated from the first task executed in the first processor, generates a packet by adding a header to the provided data according to a predetermined protocol, and then provides the generated packet to the shared memory area. A second protocol for reading the packet from the first protocol processor and the shared memory area, parsing the read packet, extracting the data, and providing the extracted data to a second task executed in the second processor; And a token processing unit. The packet includes a header and the data, wherein the header includes at least one of transmission task information indicating information of the first task generating the data and reception task information indicating information of the second task receiving the data. Information may include The header may further include at least one of an interface type of the multi-port memory, information of a processor transmitting the data, and information of a processor receiving the data. The header may further include semaphore control information for synchronizing access to the shared memory area of the first processor and the second processor.

According to a multi-processor system having a multi-processor data transmission method using the multi-port memory as described above, a recording medium recording a packet structure, a multi-processor data transmission protocol using a multi-port memory, and a multi-port memory, the first protocol When the data is generated in a predetermined task of the first processor, the processor adds a link layer header, a synchronization layer header, a task layer header, a session layer header, a presentation layer header, and an application layer header to the data generated based on a predetermined protocol. Generate the data and store the data in a shared memory area, the second protocol processor reads a packet stored in the shared memory area, parses the read packet, extracts data, and then extracts the extracted data to a corresponding task executed in the second processor. to provide.

Thus, compatibility in data transfer between multiple processors using multi-port memories can be provided. In addition, the above-described compatibility may reduce development time and development cost of the multiprocessor system, and contribute to the popularization of the multiprocessor system.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In the following description of the present invention, the same reference numerals are used for the same elements in the drawings and redundant descriptions of the same elements will be omitted.

1 is a block diagram illustrating a configuration of a multi-processor system having a multi-port memory according to an embodiment of the present invention, and illustrates a multi-processor system composed of a dual-port memory having two processors and two ports. do. Hereinafter, the multi-port memory is a concept including a dual port memory.

Referring to FIG. 1, a multi-processor system having a multi-port memory according to an embodiment of the present invention may include a first processor 110, a second processor 130, and a multi-port. Memory 150.

The first processor 110 and the second processor 130 may each perform at least one different task 111, 131, and each task 111, 131 may have at least one session. ) 112 and 132. In this case, the sessions 112 and 132 mean a set of data that is processed as a unit in a predetermined task 111 or 131.

In addition, the first processor 110 and the second processor 130 may include a first protocol processor 115 and a second protocol processor 135, respectively.

The first protocol processing unit 115 and the second protocol processing unit 135 receive data generated from a predetermined task when data is transmitted, and generate a predetermined packet by adding a header according to a predetermined protocol. Then, the data is stored in a predetermined shared memory area 159 of the multi-port memory 150, and when data is received, the packet is read after reading a packet from the predetermined shared memory area 159 of the multi-port memory 150. After extracting the data based on the information included in the header of the packet, the extracted data is provided to the task.

Here, the first protocol processor 115 and the second protocol processor 135 may be implemented in hardware logic such as a field-programmable gate array (FPGA), or may be implemented in software. When the first protocol processor 115 and the second protocol processor 135 are implemented in software, the first protocol processor 115 and the second protocol processor 135 are respectively executed in the first processor 110 and the second processor 130 to monitor whether data is generated or not. Is generated, it may operate as a predetermined memory access task that processes data and controls access of the multi-port memory 150 according to a preset protocol.

The first processor 110 performs input / output of data with the multi-port memory 150 through a first external bus interface (EBI) 120, and the second processor 130 performs a second external bus interface. Input and output data to and from the multi-port memory 150 through the 140.

The first processor 110 and the second processor 130 are packets generated by the multi-port memory 150 and a predetermined protocol through a first external bus interface (EBI) and a second external bus interface, respectively. Performs input and output.

The first external bus interface 120 and the second external bus interface 140 may serve as a kind of memory controller, and an external bus interface of a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) may be used. In the following embodiment of the present invention, it is assumed that the first external bus interface 120 and the second external bus interface 140 are SDRAM external bus interfaces.

The first processor 110 provides an address, data, a plurality of control signals and a clock to the multi-port memory 150 through the first port 121 of the multi-port memory 150, and the multi-port memory 150 Input / output of the packet is performed with the first processor 110 through the first port 121 and the first external bus interface 120.

The second processor 130 provides an address, data, a plurality of control signals and a clock to the multi-port memory 150 through the second port 141 of the multi-port memory 150, and the multi-port memory 150 Input / output of the packet is performed with the second processor 130 through the second port 141 and the second external bus interface 140.

Here, the address, the data, the plurality of control signals, and the clock are respectively connected to the first processor 110 or the second processor 130 and the multi-port memory 150 through the first bus, the second bus, the third bus, and the fourth bus. ) May be transmitted and received, or may be multiplexed with an address and data to a first bus, a plurality of control signals to a second bus, and a clock to and from a second bus.

Here, the first processor 110 may be, for example, an ARM-based baseband processor mounted on a portable terminal to process a mobile communication function, and the second processor 130 may be a multimedia processor to process additional applications. Can be.

The multi-port memory 150 may be composed of a first memory interface 151, a second memory interface 153, and a memory cell array. The memory cell array may be divided into a first dedicated memory area 155, a second dedicated memory area 157, and a shared memory area 159. Here, the shared memory area 159 may be divided into at least one shared memory area. Here, the memory cell array of the multi-port memory 150 may be composed of DRAM cells.

In addition, the multi-port memory 150 includes the first processor 110 and the second processor (by allowing the first processor 110 or the second processor 130 to acquire exclusive access rights to the shared memory area 159). 130 includes a semaphore control unit 161 to ensure synchronization. The semaphore control unit 161 may include a control register (not shown) indicating an access right and an access state of the first processor 110 and the second processor 130 with respect to the shared memory area 159.

The first dedicated memory area 155 is a memory area dedicated to the first processor 110, and the second dedicated memory area 157 is a memory area dedicated to the second processor 130. In addition, the shared memory area 159 is a memory area that the first processor 110 and the second processor 130 can use in common, and the first processor 110 and the second processor 130 are the semaphore control unit 161. After obtaining the exclusive right for the shared memory area 159 by using the can input and output packets.

The first memory interface 151 may be configured as an SDRAM memory interface. The first memory interface 151 may receive an address, a control signal, a clock, and data from the first processor 110 through the first port 121, and assign an address to a row address and a column address. After decoding, the decoded address is output to the memory cell array, and data is read from the memory cell array or written to the memory cell array according to the operation timing of reading, writing, and refreshing the memory cell array.

To this end, the first memory interface 151 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and input / output used in a general SDRAM interface. And a buffer (not shown).

The second memory interface 153 may be configured as an SDRAM memory interface. The second memory interface 153 receives an address, a control signal, a clock, and data from the second processor 130 through the second port 141, and assigns addresses to row addresses and column addresses. After decoding, the decoded address is output to the memory cell array, and packets are read from or written to the memory cell array according to the operation timing of the memory cell array, such as reading, writing, and refreshing.

To this end, the second memory interface 153 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), an input / output buffer (not shown), and the like used in a general SDRAM interface.

In the multi-processor system having a multi-port memory 150 according to an embodiment of the present invention shown in FIG. 1, two processors, that is, a first processor 110 and a second processor 130, and a multi-port memory Although a processor system has been described as an example, in another embodiment of the present invention, a multiprocessor system includes a multi-port memory having two or more processors and two or more ports, and each processor is configured to multiplex through different ports. Of course, it can be configured to perform input and output of the port memory and the packet.

2 illustrates a data transfer protocol of a multiprocessor using a multi-port memory according to an embodiment of the present invention.

Referring to FIG. 2, a data transmission protocol of a multiprocessor includes a physical layer 210, a link layer 220, a synchronous layer 230, and a task layer. 240 may include seven layers, such as a session layer 250, a presentation layer 260, and an application layer 270.

The application layer 270 includes information about the type of application running on a given processor, that is, the type of application that generates or receives data. For example, the application layer 270 may include information about the type of application such as MPEG-4, H.264, display data, sensor data, text data, and the like.

The presentation layer 260 includes information about a data presentation method such as a data encryption method and / or a data modulation method. For example, the presentation layer 260 may include information about a data encryption method such as Message Digest 5 (MD5), Data Encryption Standard (DES), and the like.

The session layer 250 includes a set of data that is processed in one unit of data generated by a predetermined task executed in a predetermined processor, that is, information about a session. For example, session layer 250 may include information such as session start and end information, session size, and the like.

The task layer 240 includes information on tasks that share or transmit data between processors belonging to multiple processors and location information of the shared memory area 159 shared by the tasks in the multi-port memory 150. For example, task layer 240 may include information about a task that generates data, information about a task that receives data, and a shared memory area 159 shared by the task that generates data and the task that receives data. It can include a start and end address.

The sync layer 230 includes semaphore control information to maintain the correct order of tasks to be processed between processors belonging to multiple processors and to ensure mutual exclusive access to common recordable data. In addition, the synchronization layer 230 may include information for requesting retransmission of data and information for transmitting data in the highest priority when a data transmission error occurs.

The link layer 220 includes memory and processor information such as memory interface type, memory bandwidth, memory manufacturer, information on the sending and receiving processor, and the like.

The physical layer 210 may define requirements for the connection between the memory interface of the multi-port memory 150 and the external bus interface of the processor.

In the data transmission protocol according to an embodiment of the present invention shown in FIG. 2, the application layer 270, the presentation layer 260, the session layer 250, the task layer 240, the synchronization layer 230, and the link layer ( Each information included in 220 may be included in a header of a packet transmitted and received between processors using a multi-port memory.

FIG. 3 illustrates a structure of a packet generated according to a data transmission protocol according to an embodiment of the present invention shown in FIG.

Referring to FIG. 3, a packet 300 according to an embodiment of the present invention is largely composed of a header 310 and a payload 390. The payload 390 includes data generated by a task executed in a predetermined processor, and the header 310 includes additional information necessary for successfully transmitting data to a processor or a task that receives the data.

The header 310 may include a link layer header 320, a sync layer header 330, a task layer header 340, a session layer header 350, a presentation layer header 360, and an application layer header 370. have.

The header 310 may have a size of 36 bytes, and the payload 390 may vary in size depending on the type of data generated in a predetermined task and the size of the shared memory area 159.

4 shows a detailed configuration of the link layer header shown in FIG.

Referring to FIG. 4, the link layer header 320 may include a start value definition field 321, a version information field 322, a memory bandwidth field 323, and an interface type. (Interface Type) field 324, Manufacturer ID field 325, Memory Information (Product ID) field 326, Source Processor ID field 327, and Destination Processor information (Destination) Processor ID) field 328 and may be configured in total of 32 bits.

The start value definition field 321 includes information indicating the start of data transmission and may be configured with 8 bits. The version information field 322 may include version information of a protocol used when data is transmitted, and may include 8 bits.

The memory band field 323 may include information about a bandwidth (eg, 8 bits, 16 bits, or 32 bits) of the memory, and may be configured as 2 bits. The interface type field 324 includes information about the memory interface type (eg, PSRAM, SRAM, SDRAM, or DDR SDRAM) of the multi-port memory 150, and may be composed of 2 bits.

The manufacturer information field 325 may include summary information about the manufacturer of the multi-port memory 150, and may include 4 bits to include information about 16 different memory manufacturers.

The memory information field 326 includes summary information about the multi-port memory 150 and may be configured with 4 bits. The memory information field 326 may include a subfield indicating the size of the multi-port memory 150 and a subfield indicating the presence or absence of the shared memory area 159.

For example, three bits of the memory information field 326 may indicate information about the size of the multi-port memory 150 (eg, 64, 128, 256, 512, 1024, 2048, 4096, or 8192Mb). The remaining 1 bit may indicate information about the presence or absence of the shared memory region 159 (for example, logic value '1' is present and '0' is non-existence).

The transmit processor information field 327 includes information about a processor that produces or transmits data, and may include two bits. The receive processor information field 328 includes information about a processor that receives data and may be configured in 2 bits.

In FIG. 4, for example, each field included in the link layer header 320 has a fixed size composed of predetermined bits. However, in another embodiment of the present invention, each field has a different size from that shown in FIG. 4. Of course it may have.

For example, although the transmission processor information field 327 and the reception processor information field 328 illustrated in FIG. 4 are each configured as 2 bits, for example, the number of processors included in the multiprocessor system is 4 or more. The transmit processor information field 327 and the receive processor information field 328 may have a size of 2 bits or more.

FIG. 5 shows a detailed configuration of the sync layer header shown in FIG.

Referring to FIG. 5, the sync layer header 330 includes information for guaranteeing synchronization between processors and may be 32-bit.

Specifically, the sync layer header 330 includes semaphore control information for ensuring mutually exclusive access between the processors to the shared memory area 159 provided in the multi-port memory 150. In addition, the sync layer header 330 may include information for requesting retransmission of data when information transmission error occurs and information for transmitting data first.

The sync layer header 330 may be divided into a transmission processor semaphore information control information field 331 and a reception processor semaphore control information field 335, and the transmission processor semaphore control information field 331 and the reception semaphore control information field 335 ) May be divided into semaphore control information fields 332 and 336 and reserved fields for emergency and / or retransmission of high-priority data, respectively. Can be.

For example, the sync layer header 330 may include a 16-bit transmit processor semaphore control information field 331 and a 16-bit receive processor semaphore control information field 335, and a transmit processor semaphore control information field 331. ) And the receiving processor semaphore control information field 335 may include preliminary fields 333 and 337 composed of 8 bits and semaphore control information fields 332 and 336 composed of 8 bits, respectively.

The semaphore control information field 335 of the sync layer header illustrated in FIG. 5 may have the same value as that of the control register included in the semaphore control unit 161, and the transmitting processor and the receiving processor may respectively transmit transmitting semaphore control information fields. The value stored in the 331 and the receiving processor semaphore control information field 335 may be read to recognize an access state of the shared memory area 159.

FIG. 6 shows a detailed configuration of the task layer header shown in FIG. 3.

Referring to FIG. 6, the task layer header may include 12 bytes in total, and includes a 16-bit source task ID field 341 and a 16-bit destination task ID field 342. ), A 32-bit Start Address field 343, and a 32-bit End Address field 344.

The transmit task information field 341 contains ID information for a task for producing or transmitting data, and in combination with the transmit processor information field 327 of the link layer header 320 shown in FIG. Knows whether to produce or transmit data.

The receive task information field 342 contains ID information for the task receiving the data, and in combination with the receive processor information field 328 of the link layer header 320 shown in FIG. You can see if you receive.

The start address information field 343 includes a start address of a memory area shared among predetermined tasks in the shared memory area 159. The end address information field 344 includes the last address of the memory area shared among certain tasks in the shared memory area 159.

As shown in FIG. 6, in the exemplary embodiment of the present invention, the shared memory area 159 may be freely used between predetermined tasks sharing data using the start address information field 343 and the end address information field 344. Can be set and used.

FIG. 7 shows a detailed configuration of the session layer header shown in FIG. 3.

Referring to FIG. 7, the session layer header may include 12 bytes in total, a 16-bit session ID field 351, a 16-bit sequence ID field 352, and 32 A total length field 353 composed of bits and a current length length field 354 composed of 32 bits are included.

The session information field 351, in combination with the transmission task information field 341 of the task layer header 340, indicates a set of data to be processed in one transmission unit in a predetermined task, that is, session information.

For example, when the session information field includes '0x0000', it indicates that a new session is started within a predetermined task. Whenever the session is increased, the value included in the session information field is also increased by one. When '0xFFFF' can be defined to indicate that the last session is started within the predetermined task. In addition, when the session is increased again after the last session, the value of the session information field may be reset to have '0x0000'.

The sequence information field 352 indicates sequence information for at least one data transport block included in a given session.

For example, when the sequential information field 352 includes '0x0000', this indicates that the data transmission block is transmitted first among the data transmission blocks included in the predetermined session, and the data transmission block included in the predetermined session. Each time is transmitted, the value included in the sequential information field 352 also increases by one. When the sequential information field 352 is '0xFFFF', the last data transmission block included in the predetermined session is transmitted. It can be defined to indicate that it is sent.

The total data length information field 353 includes information on the total size of a given session, which is a set of data processed in one unit. The current data length information field 354 includes information about the size of data that is divided or transmitted in a given session.

FIG. 8 illustrates a detailed configuration of the presentation layer header and the application layer header shown in FIG. 3.

Referring to FIG. 8, the presentation layer header 360 may include 16 bits, and includes information about an encryption method or a modulation method when data is encrypted or modulated. For example, the presentation layer header 360 may include information about an encryption method of data such as Message Digest 5 (MD5) or Data Encryption Standard (DES).

The application layer header 370 includes information about the type of application generating or receiving data. For example, the application layer header 370 may include information about the type of application such as MPEG-4, H.264, display data, sensor data, text data, and the like.

9 is a flowchart illustrating a data transmission process of a multiprocessor using a multi-port memory according to an embodiment of the present invention. 9 illustrates a process in which data generated in a predetermined task of the first processor 110 is provided to a corresponding task of the second processor 130 using the shared memory area 159 of the multi-port memory 150. Explain. The data transmission process illustrated in FIG. 9 may be processed by the first protocol processor 115 and the second protocol processor 135 provided in the first processor 110 and the second processor 130, respectively. The protocol processor 115 and the second protocol processor 135 may each be executed by a predetermined task.

First, when data is generated in a predetermined task of the first processor 110 (step 501), the first protocol processing unit 115 performs a data transmission protocol according to an embodiment of the present invention as shown in FIGS. 2 to 8. In step 503, a packet is generated by adding a header to the generated data.

Thereafter, the first protocol processor 115 acquires an access right to the shared memory area 159 provided in the multi-port memory 150 (step 505). Here, the first protocol processor 115 provides an access request signal (for example, acc_req1 = '0') to the semaphore control unit 161 provided in the multi-port memory 150 and in response thereto, an access authority signal. (Eg, ready1 = '1'), the access right to the shared memory area 159 can be obtained.

After obtaining the access right to the shared memory area 159, the first protocol processor 115 provides the generated packet to the shared memory area 159 (step 507), and then selects a predetermined location of the shared memory area 159. The packet provided from the first protocol processor 115 is stored (step 509).

Thereafter, the first protocol processor 115 requests the release of the access right to the shared memory area 159 (step 511). In this case, the first protocol processor 115 provides an access release request signal (eg, acc_req1 = '1') to the semaphore control unit 161 of the multi-port memory 150, and in response thereto, the access release signal ( For example, access to the shared memory area 159 may be released by being provided with ready1 = '0').

After the second processor 130 is initialized, the second protocol processor 135 checks whether data is generated at a predetermined time interval (step 513), and determines whether data has been generated (step 515).

Here, the second protocol processor 135 may provide the semaphore controller 161 with an access request signal (for example, acc_req2 = '0') periodically and check the response to confirm whether the data is generated or not, or determine the host processor. By receiving an interrupt signal from the first processor 110 through an interface (Host Processor Interface), it is also possible to check whether data is generated.

The semaphore control unit 161 of the multi-port memory 150 may provide an access release signal (eg, acc_req1 = '1') when the first protocol processor 115 provides an access release request signal (eg, acc_req1 = '1'). ready1 = '0') is provided to the first protocol processor 115 and at the same time, an access right signal (for example, ready2 = '1') is provided to the second protocol processor 135.

The second protocol processor 135 receives the access right signal from the semaphore controller 161 and reads the packet stored in the shared memory area 159 accordingly (step 517).

Thereafter, the second protocol processor 135 parses the packet (step 519) and extracts data from the packet (step 521). The extracted data is then provided to the corresponding task of the second processor 130 based on the information included in the header of the packet (step 523).

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a block diagram illustrating a configuration of a multiprocessor system having a multi-port memory according to an embodiment of the present invention.

2 illustrates a data transfer protocol of a multiprocessor using a multi-port memory according to an embodiment of the present invention.

FIG. 3 illustrates a structure of a packet generated according to a data transmission protocol according to an embodiment of the present invention shown in FIG.

4 shows a detailed configuration of the link layer header shown in FIG.

FIG. 5 shows a detailed configuration of the sync layer header shown in FIG.

FIG. 6 shows a detailed configuration of the task layer header shown in FIG. 3.

FIG. 7 shows a detailed configuration of the session layer header shown in FIG. 3.

FIG. 8 illustrates a detailed configuration of the presentation layer header and the application layer header shown in FIG. 3.

9 is a flowchart illustrating a data transmission process of a multiprocessor using a multi-port memory according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: first processor 115: first protocol processing unit

130: second processor 135: second protocol processing unit

150: multi-port memory 159: shared memory area

Claims (24)

In the data transmission method of the first processor and the second processor using a multi-port memory, Generating a packet by adding a header to a data generated by a first task executed by the first processor based on a predetermined protocol; And Storing the generated packet in a shared memory area of the multi-port memory, The header may include the first processor information transmitting the data, the second processor information, transmission task information indicating information of the first task generating the data, information of a second task receiving the data, and the first information. 1 is a data transmission method of a multiprocessor using a multi-port memory, characterized in that it comprises at least one of information on the session generated by the task. The method of claim 1, wherein the multiprocessor data transmission method using the multi-port memory includes: Reading, by the second processor, a packet stored in the shared memory area; The second processor parsing the read packet to extract the data; And And providing, by the second processor, the extracted data to a second task. delete The method of claim 1, wherein the header is Interface type of the multi-port memory, information indicating the start of transmission of the data, information indicating the bandwidth of the multi-port memory, information indicating the manufacturer of the multi-port memory, information indicating the size of the multi-port memory and the shared memory And at least one of the information indicating the presence or absence of a region. The method of claim 1, wherein the header is And at least one of semaphore control information for synchronizing access to the shared memory area between the first processor and the second processor, and preliminary information for emergency transmission and retransmission of the data. Data transfer method of multiple processors using memory. The method of claim 1, wherein the header is And a start address information and an end address information of the shared memory area shared by the first task and the second task. The method of claim 1, wherein the header is At least one of information on the data encryption method, information on the modulation method, and information on the type of the application generating or consuming the data. . delete A recording medium in which a structure of a packet that can be processed by multiple processors exchanging data by using a multi-port memory is recorded. The packet includes a header and the data, The header is received indicating information of a processor transmitting the data, information of a processor receiving the data, transmission task information indicating information of a first task generating the data, and information indicating a second task receiving the data. And at least one of information of a task and information about a session generated by the first task. The method of claim 9, wherein the header is Interface type of the multi-port memory, information indicating the start of transmission of the data, information indicating the bandwidth of the multi-port memory, information indicating the manufacturer of the multi-port memory, information indicating the size of the multi-port memory and shared memory area And a link layer header including at least one of the information indicating the presence or absence of a packet. The method of claim 9, wherein the header is At least one processor further comprises a synchronization layer header including semaphore control information for synchronizing access to a shared memory region of the multi-port memory and preliminary information for emergency transmission and retransmission of the data Recording medium recording the structure of the. The method of claim 9, wherein the header is And a task layer header including start and end address information of a shared memory area shared by the first task and the second task. delete The method of claim 9, wherein the header is And a representation layer header including at least one of information of the information on the data encryption method and the modulation method. The method of claim 9, wherein the header is And an application layer header including information on the type of application generating or consuming the data. A data transfer protocol of a multiprocessor having a multiport memory and a first at least one processor, The at least one processor exchanges the data through a packet consisting of a header and data, The header includes information of a processor transmitting the data, information of a processor receiving the data, transmission task information representing the data of the first task, information of a second task receiving the data, and the first task. And at least one of the information on the session generated by the multi-processor data transfer protocol using the memory. The method of claim 16 wherein the header is Interface type of the multi-port memory, information indicating the start of data transmission, information indicating the bandwidth of the multi-port memory, information indicating the manufacturer of the multi-port memory, information indicating the size of the multi-port memory and the presence of a shared memory area The data transmission protocol of the multi-processor using a multi-port memory, characterized in that it further comprises a link layer header including at least one information. The method of claim 16 wherein the header is At least one processor further includes a synchronization layer header including at least one of semaphore control information for synchronizing access to a shared memory region of the multi-port memory and preliminary information for emergency transmission and retransmission of the data; Multiprocessor data transfer protocol using a multi-port memory, characterized in that. The method of claim 16 wherein the header is And a task layer header including start and end address information of a shared memory area shared by the first task and the second task. The method of claim 16 wherein the header is An expression layer header including at least one of information on the data encryption method and information on a modulation method; And And at least one header from among application layer headers including information on the type of application generating or receiving the data. In a multiprocessor system having multi-port memory, A shared memory area provided in the multi-port memory and commonly used by a first processor and a second processor; A first step of receiving data generated from a first task executed in the first processor and generating a packet by adding a header to the provided data according to a predetermined protocol and providing the generated packet to the shared memory area A protocol processing unit; And A second protocol processor configured to read the packet from the shared memory area, parse the read packet to extract the data, and then provide the extracted data to a second task executed by the second processor; The header may include information about the first processor, information about the second processor, information about the first task, information about the second task, information about a session generated by the first task, and an interface type of the multi-port memory. A multi-processor system having a multi-port memory, characterized in that it comprises at least one of the information. delete delete delete

Images