JPH04258020A - Input circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption by connecting a 1st conduction type MOSFET between an element of a power supply side of an input circuit of differential amplifier circuit configuration and a power supply and connecting a 2nd conduction type MOSFET between an element at ground side and ground in series. CONSTITUTION:The input circuit is a differential amplifier circuit using a P- channel MOS field effect transistor (FET)Ma and an N-channel MOSFETM4 as differential inputs and an N-channel MOSFETM5 is a load. Furthermore, a P-channel MOSFETM1 is a current source at the source side. The FETM3 is a switch element and has a larger mutual conductance in comparison with that of the FETM5. In this case, with the MOS TR turned on, it is equivalent to the state that a drain of the P-channel MOSFETM2 connects to ground. Thus, when an input signal of the CMOS level is processed and the input signal is at a ground level or a power supply level, the power supply current flows to the input circuit.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit whose signal level is a power supply level or a ground level, and more particularly to a circuit configuration of an input circuit that prevents through current when the input level is a power supply level or a ground level.

0002

2. Description of the Related Art A circuit diagram of an example of a conventional input circuit is shown in FIG.

The circuit configuration of this input circuit is a complementary MOS transistor (hereinafter referred to as CMOS) configuration, in which a P-channel MOS transistor P and an N-channel MOS transistor N are connected in series between a power supply and ground. . A common gate of these two MOS transistors becomes an input end, a common drain is connected to an input of an inverting circuit 1, and an output of this inverting circuit 1 becomes an output end.

The sizes of the above two MOS transistors are determined by the ratio of the channel width and channel length of each MOS transistor to (W/L)P and (W/L)N.
When, (W/L)P < (W/L)N

(1).

Therefore, the input/output characteristics of this inverting amplifier as an input circuit are such that the logic threshold shifts toward the ground potential side,
The characteristics are as shown in FIG.

In FIG. 3, when the input Vin is lower than the threshold voltage VTN of the N-channel MOS transistor N, the N-channel MOS transistor N is off, so the output VO is at the "1" level.

Conversely, when the potential falls within the threshold voltage VTP of the P-channel MOS transistor P from the power supply potential, P
Since the channel MOS transistor P is turned off, the output VO is fixed at the "0" level.

In this input circuit, as shown in equation (1), the W/L ratio of the N-channel MOS transistor N is made larger than the W/L ratio of the P-channel MOS transistor P. The mutual conductance of N is larger than the mutual conductance of P channel MOS transistor P.

Therefore, during the period when both MOS transistors are on, the N-channel MOS transistor N is stronger, and the logic threshold of this input circuit is close to the threshold voltage VTN of the N-channel MOS transistor. It's wet.

By the way, in general, in a TTL level signal, the "0" level is 0.8V or less, and the "1" level is 2.0V or more, so the logic threshold of the input circuit is (0. 8+0.2)/2=1.4V has the most margin.

Therefore, if the circuit is designed to satisfy the above equation, it is possible to input a TTL level signal even with a CMOS input circuit.

0012

[Problems to be Solved by the Invention] By the way, when the above input circuit receives a TTL level input signal, the switching speed is limited by the mutual conductance of the P-channel MOS transistor P and the load capacitance added to the output terminal. Therefore, the higher the speed, the more power is consumed.

Furthermore, since a normal CMOS inverter uses P-channel MOS transistors and N-channel MOS transistors with the same mutual conductance,
Its logic threshold is hardly affected by temperature changes and is located at approximately half of the power supply voltage.In contrast, in the input circuit described above, the logic threshold is equal to the threshold voltage VTN of the N-channel MOS transistor N. It becomes a logical threshold that strongly depends on .

[0014] Now, let us consider the fluctuation range of the logic threshold value of the input circuit.

[0015] In this input circuit, the width of the change in the threshold voltage of the MOS transistor that occurs due to variations in the manufacturing process is calculated by Takashi Tokuyama, "MOS Devices", 3rd edition, Industrial Research Association, 1976. As described on page 16, ±0.2V and temperature change of -40 to +85°.
The range of change in threshold voltage when C is
As stated on page 6, if it is ±0.15V,
Even if you think about it simply, the range of change in threshold voltage is ±0.2±
0.15=±0.35V.

Furthermore, since there is no guarantee that changes in threshold voltage that occur during the manufacturing process of P-channel MOS transistors and N-channel MOS transistors will be linked, it is possible for the threshold voltage to actually change by ±0.4 to 0.45V. Conceivable.

By the way, the above discussion concerns the DC logic threshold of the input circuit, and the logic threshold in this case follows the input/output characteristics shown in FIG. 3, but in reality, the input circuit has Since a discontinuous pulse signal is input, let's consider an alternating current logic threshold.

This alternating current logical threshold is the output VO
The point at which the switching speeds of the two transistors become the same is regarded as the logic threshold. From this viewpoint, it is understood that the output VO needs to be placed below the power supply in order to cover the P-channel MOS transistor with small mutual conductance. ing.

In other words, the alternating current logical threshold value deviates depending on the power source. However, this shift amount cannot be accurately estimated because the frequency of the input pulse is uncertain.

[0020] To summarize the above, TTL level "1"
The width of the level separating the "0" level is 1.
There is 2V, but it is 0 due to fluctuations in threshold voltage during the manufacturing process.
．． Considering that there is a fluctuation of 8 to 0.9 V and that the AC logic threshold shifts toward the power supply when a pulse signal is actually input, conventional input circuits have TTL
It is difficult to receive high level input signals.

[0021]

[Means for Solving the Problems] The input circuit of the present invention fixes one input of a differential amplifier circuit to a reference voltage, inputs an input signal to the other input via an input terminal, and fixes one input of a differential amplifier circuit to a reference voltage. A first conductivity type first conductivity type is provided between the power supply side element of the circuit and the power supply.
MOS field effect transistors are connected in series, a second MOS field effect transistor of a second conductivity type is connected in series between the ground side element and the ground, and the gate of the first MOS field effect transistor and The present invention is characterized in that the gate of the second MOS field effect transistor is connected to an input terminal.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the route configuration of a first embodiment of the present invention.

This embodiment consists of three P-channel MOS transistors M1, M2, and M4, two N-channel MOS transistors M3 and M5, and an inverting circuit 1.

The P-channel MOS transistor M1 has a source connected to the power supply, a gate connected to the input terminal 2, and a drain connected to the P-channel MOS transistor M2.
and connected to the source of M4.

The P-channel MOS transistor M2 has a gate applied with a reference voltage VREF from the constant voltage source 3, and a drain connected to the drain of the N-channel MOS transistor M3. Note that the source of the N-channel MOS transistor M3 is grounded.

The drain of P-channel MOS transistor M4 is connected to the drain of N-channel MOS transistor M5. Note that the source of the N-channel MOS transistor M5 is grounded.

The gates of P-channel MOS transistor M4 and N-channel MOS transistors M3 and M5 are connected to input terminal 2.

The output of this differential amplifier circuit is P channel M
The signal is outputted from the output terminal 4 from the common drain of the OS transistor M4 and the N-channel MOS transistor M5 via the inverting circuit 1 at the next stage. The inverting circuit 1 is provided for waveform shaping.

Next, the operation of this embodiment will be explained. This circuit is a differential amplifier circuit having a P-channel MOS transistor M2 and an N-channel MOS transistor M4 as differential inputs, and an N-channel MOS transistor M5 is a load. Furthermore, the P-channel MOS transistor M1 is a source-side current source.

Here, the N-channel MOS transistor M3 is a switching element and has a larger mutual conductance than the N-channel MOS transistor M5. Therefore, when this MOS transistor is on, it is equivalent to the drain of P-channel MOS transistor M2 being grounded.

In a normal differential amplifier circuit, the P-channel MOS transistor M1 and the N-channel MOS transistor M in FIG.
The main reason for using a MOS transistor whose gate is connected to input terminal 2 in this embodiment is that while the OS transistor M5 is composed of a constant current source element or a resistor element, the input level is This is to prevent a through current from flowing between the power source and the ground of the input circuit when the potential or ground potential is reached.

In this embodiment, the CMOS LSI has the above-described configuration in order to maximize the feature of not consuming power when the signal does not change.

The reason why a differential amplifier circuit is generally not used in the input circuit of a CMOS LSI is that the above-mentioned through current cannot be prevented.

The biggest advantage when using a differential amplifier circuit is
This is the point where the logic threshold becomes less susceptible to temperature changes. It is also less susceptible to variations in the manufacturing process.

As a result, in this embodiment, the logic threshold value becomes approximately equal to the reference voltage VREF, and it becomes possible to easily design an input circuit for TTL level signals, which has been difficult in the past.

Next, a second embodiment of the present invention will be described. In this embodiment, in the first embodiment, the reference voltage VREF
was obtained from a constant voltage source 3, whereas the reference voltage is generated by changing the threshold voltage of the differential input transistor.

In FIG. 2, the gate of P-channel MOS transistor M6 is grounded, and the gate of P-channel MOS transistor M6 is grounded.
P from threshold voltage VTM4 of S transistor M4
Threshold voltage V of channel MOS transistor M6
By setting TM6 higher by about 1.4 V (logic threshold of TTL level), an input circuit for a TTL level signal can be realized.

In this circuit, the logic threshold is affected by variations in the threshold voltage of the MOS transistor due to variations in the manufacturing process, but the P-channel MOS transistor M4 and the P-channel MOS transistor M6 have the same conductivity type. Since it is a channel, the difference in threshold voltage does not increase so much, and it is easy to suppress it to within ±0.15V.

In this embodiment, it is possible to connect the gate of P-channel MOS transistor M6 to the power supply terminal, but in this case, input signal level (1.4V) - VTM4 = power supply voltage -
The threshold voltages of the two P-channel MOS transistors may be set so as to satisfy the formula VTM6.

[0040] Also, P-channel MOS transistor M1
drain side and N-channel MOS transistor M5
Another method is to increase the DC gain of this circuit by inserting a current source element or a resistance element on the drain side of the circuit.

In the first and second embodiments, the case where P-channel MOS transistors were used as the differential input was explained, but it is also possible to obtain the same effect by using N-channel MOS transistors. can.

[0042]

As explained above, the present invention incorporates a differential amplifier circuit as an input circuit, so that its logical threshold value is free from the effects of fluctuations in the threshold voltage of MOS transistors due to fluctuations in the manufacturing process. , and is less susceptible to temperature changes, so it can be used as an input circuit for TTL level input signals.

Furthermore, when the input circuit of the present invention handles a CMOS level input signal instead of a TTL level input signal, when the input signal is at the ground level or power supply level, a power supply current flows through the input circuit. It also has the characteristic of not having any.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

FIG. 3 is a circuit diagram of a conventional input circuit.

FIG. 4 is a diagram showing input/output characteristics of a conventional input circuit.

[Explanation of symbols]

1 Inversion circuit 2 Input terminal 3 Constant voltage source 4 Output terminal

Claims (1)

[Claims] [Claim 1] One input of a differential amplifier circuit is fixed to a reference voltage, an input signal is inputted to the other input via an input terminal, and an element on the power supply side of this differential amplifier circuit is connected to the power supply. A first MOS field effect transistor of a first conductivity type is connected in series to the ground, a second MOS field effect transistor of a second conductivity type is connected in series between the ground side element and the ground, and An input circuit characterized in that a gate of the first MOS field effect transistor and a gate of the second MOS field effect transistor are connected to an input terminal.