JPH0425715A - Scale signal dividing circuit - Google Patents

Abstract

PURPOSE:To take an accurate measurement without any measurement error due to the jitters, etc., of a clock by putting a digital sine wave generating means and a counter means in operation according to the same clock signal. CONSTITUTION:An A-phase and a B-phase scale signal are inputted to D/A converters 3 and 4 through buffer amplifiers 1 and 2. An (n)-scale counter 5, on the other hand, receives the clock signal from a clock signal generation part 13 to perform (n)-scale counting operation and outputs a corresponding address signal. Then ROMs 6 and 7 receive this address signal and output trigonometric function signals corresponding to the address signal. The digital signals are supplied to an adder 8 through converters 3 and 4 and a phase modulating signal (MOD) is outputted. A counter 11 counts up to a specific counted value according to the MOD. Then a discriminating circuit 12 discriminates whether or not the rising of a synchronizing signal MOD and the counting point of an (n)-scale counter 11 are out of phase and outputs a clock signal corresponding to the phase difference when there is the phase difference. Consequently, the accurate measurement becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a scale signal dividing circuit used in a measuring instrument that measures length or the like based on the amount of movement of a sample.

[Prior Art] A conventional scale signal dividing circuit has a circuit configuration as shown in FIG. In the same figure, one input terminal of the scale signal dividing circuit receives an A-phase scale signal output from a detector (not shown) due to the movement of the sample, and similarly, the other input terminal receives a B-phase scale signal. A scale signal is input. The A-phase and B-phase scale signals are respectively supplied to buffer amplifiers 101 and 102 to improve the S/N ratio. Outputs from buffer amplifiers 101 and 102 are input to one input terminal of analog multipliers 103 and 104, respectively. The other input terminal of this multiplier 103, 104 is supplied with an analog sine wave as a modulation signal generated by a trigonometric function generator 105. Analog multipliers 103 and 104 multiply the supplied scale signal and modulation signal and output the respective multiplication results. here,
The modulation signal supplied to the analog multiplier 103 is
The modulation signal supplied to the ωt1 analog multiplier 104 is
If s1nωt, the multiplication results are 2π, respectively, ABs in (-x)cosωt.

These multiplication results are supplied to adder 106 and added. Therefore, adder 106 outputs a signal.

The comparator 107 binarizes this phase modulation signal and
Outputs the value code. Therefore, by measuring one period of this binary code, the amount of movement of the sample can be determined and the length can be measured.

A clock generator is used for this measurement, and the period is determined by the number of clocks corresponding to one period.

[Problem to be solved by the invention] However, in the scale signal dividing circuit having the circuit configuration described above, the analog sine wave from the trigonometric function generator is unstable, and the clock used for measurement has jitter. When this occurs, there are problems in that the phase modulation signal contains an error, or the measured value changes due to the clock for phase modulation signals of the same cycle, making it impossible to perform accurate measurements.

The scale signal dividing circuit of the present invention was created with attention to such problems, and its purpose is to provide a scale signal dividing circuit that can perform accurate measurements without measurement errors caused by clock jitter, etc. It is about providing.

[Means for Solving the Problems] In order to solve the above problems, the scale signal divider of the present invention includes means for generating a digital sine wave as a modulation signal, and a means for generating a plurality of scales having different phases by this digital sine wave. A D/A converter that multiplies each signal, and this D/A converter that multiplies each signal.
means for adding the multiplication results from the /A converter and outputting a phase modulation signal; a counter means for counting a predetermined count value based on the phase modulation signal; means for outputting a signal representing a phase shift with respect to the end of counting;
The digital sine wave generating means, the counter means, and the output means are operated based on the same clock signal.

[Operations] The present invention includes means for generating a digital sine wave as a modulation signal, a D/A converter for multiplying each of a plurality of scale signals having different phases by the digital sine wave, and a D/A converter for multiplying each of the digital sine waves by a plurality of scale signals having different phases. means for adding the multiplication results to output a phase modulation signal; a counter means for counting a predetermined count value based on the phase modulation signal; and a counter means for counting a predetermined count value based on the phase modulation signal; Since the digital sine wave generating means, the counter means, and the output means are operated based on the same clock signal, the influence of clock jitter etc. during measurement is reduced. or be canceled out.

[Embodiment] An embodiment of the scale signal dividing circuit of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the scale signal dividing circuit of the present invention. First, Asln is input to each input terminal of the scale signal dividing circuit. where A is the amplitude, λ is the scale pitch, and X
is the amount of displacement. I have it. These scale signals are S
/ through buffer amplifiers 1 and 2 to improve the N ratio.
Reference voltage terminal V t of multiplier type D/A converters 3 and 4
*1 is respectively input as an analog input signal.

On the other hand, the n-ary counter 5 receives the clock signal from the clock signal generator 13, performs n-ary counting, and outputs a corresponding address signal. ROMs 6 and 7 receive these address signals and output trigonometric function signals corresponding to the addresses. These trigonometric function signals are COSω and si
This is a digital signal expressed as nωt. These digital signals are input as modulation signals to the other input terminals of the multiplication type D/A converters 3 and 4. Multiplying type D/A converters 3 and 4 have the same function as the analog multiplier described above, and have reference voltage terminals V1. ．． The scale signal input to the ROM 6 and 7 is attenuated or multiplied by the digital modulation signals from the ROMs 6 and 7. Multiplying D/A
The multiplication results from con l<-93 and h4 are supplied to adder 8 and added. Therefore, the adder 8 outputs a signal λ expressed as A B sin (×10ωt) as the addition result, and the signal is binarized by the comparator 9.

A binarized signal as a phase modulation signal (MOD) is output from the comparator 9 and supplied to the control circuit 10. The control circuit 10 receives this phase modulation signal (MOD) and outputs control signals A RESET and B RESET to an n-ary counter 1 consisting of two n-ary counters A and B. This control signal is a signal for starting or stopping the operation of the n-ary counters A and B. That is, the n-ary counters A and B are connected to the clock signal generator 13.
and starts an n-ary count in response to the control signal. The control circuit 10 also converts the phase modulation signal (MOD) into a synchronization signal MOD.
(SYNC) and supplies it to the discrimination circuit 12, and also outputs a counter selection signal for selecting one of the n-ary counters A and B to the discrimination circuit 12.

The discrimination circuit 12 is similarly operated based on the clock signal from the clock signal generator 13, and generates a synchronization signal MOD (
It is determined whether or not there is a phase shift (amount of movement) between the rise of SYNC) and the point in time when the n-ary counters A and B perform n-ary counting, and if there is a phase shift, a clock signal corresponding to the shift is output. In this case, when receiving a signal to select n-ary counter A, that is, when there is a movement amount in the positive direction, an up (UP) pulse signal is output, and n
A signal for selecting advance counter B, that is, a DOWN pulse signal is output when there is a movement amount in the negative direction. Thereafter, by counting the number of pulses with a counter (not shown) and measuring the amount of movement of the sample, the length can be determined.

The operation of the circuit shown in FIG. 1 will be explained below while comparing the film charts shown in FIGS. 2(a), 2(b), and 2(c). Second
Figure (a) shows a state where there is no amount of movement, that is, the length of the sample is not measured.

Figure 2 (b) shows that when there is movement in the positive direction, (C)
is the case where there is a movement amount in the negative direction.

In FIG. 2(a), CLK is the waveform of the clock generated by the clock generator 13, and MOD is the waveform of the digital phase modulation signal output from the comparator 9. In FIG. As shown by the shaded area in the figure, the phase modulation signal has a cycle width equivalent to one clock cycle. The control circuit 10 generates a synchronization signal MOD (SYNC) that rises at the timing shown no matter where MOD rises. As mentioned above, A RESET.

B RESET is a signal supplied from control circuit 10 to n-ary counter 11 to control counters A and B, respectively. That is, in the figure, A RE
Counter A starts n-ary counting when SET is released, and is reset when n-ary counting ends. As described above, the discriminator circuit 12 has MOD (SYN
Compare the rising edge of C) and the end timing of n-ary counting.

In FIG. 2(a), since no measurement has been made and there is no amount of movement, the timing of both is the same and there is no phase shift. Therefore, the discrimination circuit 12 does not output the output signals (UP and DOWN).

On the other hand, Fig. 2(b) shows a case where there is a movement amount in the positive direction, and since the rise of MOD (SYNC) is delayed, there is a difference between the end timing of n-ary counting and the timing shown in the figure. There is a phase shift, and therefore, the output of the discrimination circuit 12 (UP in this case) is a clock corresponding to this shift.

Also, if there is a movement amount in the positive direction, see Figure 2 (C).
As shown in the figure, the rising edge of MOD (SYNC) becomes early, and a phase shift as shown in the figure occurs between the timing and the end timing of n-ary counting. Therefore, the output of the discrimination circuit 12 (in this case, DOWN) is a clock corresponding to this phase shift.

Note that the present invention is not limited to the above embodiments, and various modifications and changes are possible.

For example, in this embodiment, two scale signals with a - phase shift have been described, but the present invention is not limited to this, and three or more signals with a phase shift may be used.

[Effects of the Invention] As detailed above, the scale signal dividing circuit of the present invention generates a digital sine wave signal and a phase shift signal for measurement based on the same clock signal. , it is possible to provide an accurate scale signal dividing circuit that eliminates measurement errors due to clock jitter and the like.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of the scale signal dividing circuit of the present invention, and FIGS. 2(a), (b), and (c) are diagrams for explaining the operation of the circuit in FIG. "This is a time chart, and FIG. 3 is a circuit configuration diagram of a conventional scale signal dividing circuit. 1.2... Buffer amplifier, 3.4... Multiplying type D/
A converter, 5...N-ary counter, 6.7...R
OM, 8... Adder, 9... Comparator, 10.
...Control circuit, 11...N-ary counter, 12...Discrimination circuit, 13...Clock signal generation unit. Applicant's agent Patent attorney Atsushi Tsuboi

Claims (1)

[Claims] A means for generating a digital sine wave as a modulation signal, a D/A converter that multiplies a plurality of scale signals with different phases by the digital sine wave, and phase modulation by adding the multiplication results from the D/A converter. means for outputting a signal; counter means for counting a predetermined count value based on the phase modulation signal; and outputting a signal representing a phase shift between a level change of the phase modulation signal and a time when counting by the counter means is completed. 2. A scale signal dividing circuit comprising: means for generating a digital sine wave, wherein the digital sine wave generating means, the counter means, and the output means are operated based on the same clock signal.