JPH0425705B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device including two or more types of vertical transistors.

Conventionally, planar bipolar transistors diffuse impurities by selectively etching the oxide film on the substrate surface. However, in response to demands for higher speed and higher integration of transistors, selective oxidation using a nitride film as a mask and formation of transistors using polysilicon are being carried out.

On the other hand, when forming vertical transistors with various characteristics in semiconductor integrated circuits, impurities are injected many times under different conditions using ion implantation or thermal diffusion to form the required regions. They can be introduced selectively using the method. However, as a practical matter, it is difficult to perform the process so many times, and as the number of steps for introducing impurities increases, the quality and manufacturing yield of semiconductor integrated circuits deteriorate significantly. Therefore, for example, if the base and emitter diffusion conditions are the same, the current amplification factor and breakdown voltage will be the same, the base width will be the same, and each transistor will exhibit similar characteristics, and the degree of freedom in design will be extremely small.

Furthermore, when a normal bipolar transistor and an integrated injection logic circuit (IIL) are fabricated together in a single semiconductor integrated circuit, both vertical transistors may be fabricated using the same impurity introduction process. It is extremely difficult to obtain the desired properties.

The present invention eliminates the drawbacks of the above-mentioned prior art and enables multiple types of transistors or transistors to be integrated into a semiconductor device without increasing the number of impurity introduction steps.
The present invention provides a method for manufacturing a semiconductor device having a structure in which each IIL element can be formed to have desired characteristics.

The present invention relates to a semiconductor device including two or more types of vertical transistors, including a transistor in which the edge of the emitter region is formed inside the edge of the base region, and a transistor in which the edge of the emitter region is formed inside the edge of the base region; This method of manufacturing a semiconductor device includes a transistor in which an edge of a collector region of the transistor overlaps an edge of a base region.

The present invention will be described in detail below based on Examples. First, an embodiment in which the present invention is applied to a semiconductor device including two types of bipolar transistors will be described with reference to FIGS. 1 and 2.
The left side of FIG. 1 is a plan view of a transistor in which the emitter pattern overlaps the base pattern to form a so-called wall emitter, and the right side of the figure is a plan view of a transistor in which the emitter pattern is inside the base pattern. In addition, Fig. 2 shows A- in Fig. 1.
It is a sectional view taken along the line A′.

The N-type substrate or N-type epitaxial layer 21 is selectively oxidized to form a field oxide film 22 of about 1.3 μm, and base impurities are introduced by ion implantation or diffusion to form base regions 11, 11'. Next, polysilicon 24, 24' with a thickness of 5000 Å is formed,
Oxide films 23 and 23' are formed by selective oxidation.

Next, N-type impurities are introduced into the polysilicon by a diffusion method, and the emitter region 12,
12' is formed. At this time, as in the transistor on the left side of FIG. 1, if an emitter window is formed so as to overlap the edge 11a of the base region 11 and impurities are introduced, a so-called wall emitter 12 surrounded by an insulating film is formed. It is formed. on the other hand,
If the emitter region 12' is formed inside the edge 11'a of the base region 11', as in the transistor on the right side of FIG. 1, no wall emitter is formed.

At this time, in the case of a wall emitter, the base width facing the side surface of the emitter is narrower than or equal to the base width of the bottom surface, and the current gain h _FE can be made sufficiently large. On the other hand, when the emitter is formed inside the base, the width of the base at the side surface is larger than that at the bottom, the current gain becomes smaller, and the collector-emitter breakdown voltage can be increased.

Also, if you change the shape of the emitsa and base,
h _FE changes accordingly. For example, if the h _FE of a double base transistor with an emitter area of 4 microns x 19 microns with the emitter inside is 100, then the h _FE of a single base transistor with a wall emitter with an emitter area of 4 microns x 4 microns is approximately 1.5 times. It will be 150. Conversely, the h _FE of a triple base transistor with an emitter area of 4 microns x 40 microns x two emitters on the inner side is
It has been experimentally confirmed that it becomes 80, which is 0.8 times.

If you use the shape effect of the emitsa mentioned above,
For circuits that require a high collector-emitter breakdown voltage and require a small h _FE , a large transistor with an internal emitter can be used.A wall-emitter transistor with a small collector-emitter breakdown voltage is sufficient for a device that requires a large h _FE . It can be seen that the ivy uses a transistor with a small area.

Therefore, according to the present invention, two types of vertical transistors and reverse transistors having different characteristics can be easily formed in one integrated circuit without increasing the number of steps for introducing impurities.

Next, an embodiment will be described in which an integrated injection logic element (IIL) and a linear element are formed into one integrated circuit.

It is known that the current gain of IIL is proportional to the collector area/base area ratio. For this reason, it is desirable that the collector area be as similar to the base area as possible. Therefore, in order to increase the current gain of IIL,
If the collector polysilicon diffusion region 34 is placed outside the base pattern 30a as in the structure shown in FIG. Except for the graft base region 32, the collector and base areas can be made equal. This allows the inverse h _FE of IIL to be increased.

On the other hand, the linear part that requires high withstand voltage is not shown in FIG. 3, but as shown on the right side of FIG. The linear section and the high current gain IIL section can be formed simultaneously without adding any extra steps.

As described above, according to the present invention, by forming a so-called wall emitter type transistor and a non-wall emitter type transistor in a semiconductor device on the same substrate, it is possible to form transistors with significantly different characteristics in a relatively simple process. By providing multiple types of transistors, the performance of the semiconductor device can be significantly improved.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are a plan view and a sectional view taken along the line A-A', respectively, for explaining one embodiment of the present invention;
FIG. 3 is a sectional view for explaining another embodiment of the present invention. 11, 11', 30...Base area, 12, 1
2'... Emitter region, 13, 13'... Collector region, 21... N-type substrate or epitaxial layer,
22, 37...field oxide film, 23, 23',
38... Polysilicon oxide film, 24, 24'...
...Emitter polysilicon, 30a...Selective oxidation pattern of base, 31...Injector, 32...
... Graft (external) base, 33 ... Collector region, 34 ... Collector polysilicon diffusion region, 3
5... Emitter region, 36... Emitter polysilicon N ⁺ region.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including two or more types of vertical transistors, including the step of selectively forming a plurality of first diffusion layers of opposite conductivity type on one main surface of a semiconductor substrate of one conductivity type; forming a polycrystalline semiconductor layer on a surface of the polycrystalline semiconductor layer in a region where a first vertical transistor is to be formed, leaving a part of the polycrystalline semiconductor layer including an edge of the first diffusion layer surface region;
The polycrystalline semiconductor layer in the region where the second vertical transistor is to be formed is selectively oxidized leaving a partial region not including the edge of the first diffusion layer surface region, and one conductive layer from the one principal surface. 1. A method of manufacturing a semiconductor device, comprising the step of introducing a high concentration impurity of type into the selective oxide film as a mask.