JPS59191372A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59191372A JPS59191372A JP58065822A JP6582283A JPS59191372A JP S59191372 A JPS59191372 A JP S59191372A JP 58065822 A JP58065822 A JP 58065822A JP 6582283 A JP6582283 A JP 6582283A JP S59191372 A JPS59191372 A JP S59191372A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- transistor
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置、特に２ｆ＊以上の垂直形トランジ
スタを含む半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device including a vertical transistor of 2f* or more.
従来ブレーナ形バイポーラトラ／リスタは基板表面の酸
化膜を選択的にエツチングして不純物を拡散していた。Conventional Brehner-type bipolar transistors/listers diffuse impurities by selectively etching the oxide film on the substrate surface.
しかるに、トランジスタの高速化。However, the speed of transistors has increased.
高集積化の要求から、窒化膜をマスクにした選択酸化や
ポリシリコンを利用したトランジスタの形成が行なわれ
ている。Due to the demand for higher integration, selective oxidation using a nitride film as a mask and the formation of transistors using polysilicon are being carried out.
一方、半導体集積回路の中に種々の特性ヶ有する垂直形
トランジスタを形成する場合、原理的には必要とする領
域全形成するために１条件を変えて何回でも不純物をイ
オン注入法や熱拡散法を用いて選択的に導入すればよい
。しかし、笑際問題としてそう多数回の処理を行なうこ
とは難しく。On the other hand, when forming vertical transistors with various characteristics in a semiconductor integrated circuit, in principle, impurities can be added using ion implantation or thermal diffusion as many times as necessary under different conditions to form the entire required area. They can be introduced selectively using the method. However, as a practical matter, it is difficult to perform processing so many times.
また不純物の導入工程が増えれば増えるほど半導体集積
回路の品質及び製造歩留シが大幅に低下する。したがっ
て１例えば、電流増幅率や耐圧はベース及びエミッタの
拡散条件が同一ならばベース幅も同じになシ、各トラン
ンスタとも同様な特性を示し、設計の自由度がきわめて
小さくなる。Furthermore, as the number of steps for introducing impurities increases, the quality and manufacturing yield of semiconductor integrated circuits decreases significantly. Therefore, for example, if the base and emitter diffusion conditions are the same, the current amplification factor and breakdown voltage are the same, the base width is also the same, and each transistor exhibits similar characteristics, which greatly reduces the degree of freedom in design.
また、１個の半導体集積回路の中に、通常のバイポーラ
トランジスタと集積注入論理回路（Ｉｎｔｅｇｒａｔｅ
ｄ Ｉｎｊｅｃｔｉｏｎ Ｌｏｇｉｃ ： Ｉ ＩＬ
） ｆ−絽に作シ込む場合１両者の垂直形トランジスタ
を同一の不純物導入工程で作ったのでは所望の籍性？得
ることがきわめて困難である。In addition, a single semiconductor integrated circuit contains a normal bipolar transistor and an integrated injection logic circuit.
d Injection Logic: IIL
) When fabricating f-cells 1.If both vertical transistors were fabricated in the same impurity introduction process, would it be the desired property? It is extremely difficult to obtain.
本発明は、上記従来技術の欠点全解消し、不純物導入工
程を増加させることなく、半導体装置内に複数棟のトラ
ンジスタ、またはトランジスタとＩＩＬ素子をそれぞれ
所望の特性をもつように形成することができる構造の半
導体装置を提供するものである。The present invention eliminates all the drawbacks of the above-mentioned conventional techniques, and makes it possible to form a plurality of transistors or transistors and IIL elements each with desired characteristics in a semiconductor device without increasing the number of steps for introducing impurities. The present invention provides a semiconductor device having the following structure.
本発明は、２種以上の垂直形トランジスタを含む半導体
装置において、エミッタ領域の縁部がベース領域の縁部
よシも内４ＥＪＫ形成されたトランジスタと、順動作ト
ランジスタのエミッタ領域の縁部または逆動作トランジ
スタのコレクタ領域の縁部がベース領域の縁部と重なっ
て形成されたトランジスタとを含むことを特徴とする半
導体装置である。The present invention relates to a semiconductor device including two or more types of vertical transistors, including a transistor in which the edge of the emitter region is formed within the edge of the base region, and a transistor in which the edge of the emitter region is formed within the edge of the base region, and A semiconductor device characterized in that it includes a transistor formed such that an edge of a collector region of the operational transistor overlaps an edge of a base region.
以下実施例にもとづき、本発明の詳細な説明する。まず
本発明ｆｔ２ａ１ｍのバイポーラトランジスタを含む半
導体装置に適用した場合の一実施例について、第１図及
び第２図を参照して説明する。The present invention will be described in detail below based on Examples. First, an embodiment in which the present invention is applied to a semiconductor device including a bipolar transistor ft2a1m will be described with reference to FIGS. 1 and 2.
第１図の左側はエミッタバター／がベースパターンと重
なって所謂ウォールドエミッタを形成するトラ／ジスタ
、同図の右側はエミッタパターンがベースパターンの内
側にあるトランジスタのツレぞれ平面図である。また、
第２図は第１図のＡ−Ａ′線断面図である。The left side of FIG. 1 is a plan view of a transistor in which the emitter butter overlaps with the base pattern to form a so-called walled emitter, and the right side of the same figure is a plan view of a transistor in which the emitter pattern is inside the base pattern. Also,
FIG. 2 is a sectional view taken along line A-A' in FIG. 1.
Ｎ形基板またはＮ形エピタキシャル層２１を選択酸化し
、フィールド酸化膜２２を約１．３μ形成し、ベース不
純物をイオノ注入法又は拡散法で導選択的に酸化して酸
化膜２３．２３’ｅ形成する。The N-type substrate or the N-type epitaxial layer 21 is selectively oxidized to form a field oxide film 22 of approximately 1.3 μm, and the base impurity is conductively selectively oxidized by ion implantation or diffusion to form an oxide film 23.23'e. Form.
次にポリシリコンにＮ形不純物を拡散法によシ導入して
、そこからの拡散でエミッタ領域１２゜１２’を形成す
る。このとき第１図の左側のトランジスタのように、ベ
ース領域１１の縁ｔｔａにオーバラップするようエミツ
タ窓を形成して不純物を導入すると１周囲を絶縁膜でか
こまれた所餉ウォールドエミッタ１２が形成される。一
方、第１図の右側のトランジスタのように、工きツタ領
域１２”ｋベース領域１１′の１ｉｌｌ’Ｈの内側に形
成するとウォールドエミッタは形成されない。Next, N-type impurities are introduced into the polysilicon by a diffusion method, and emitter regions 12.degree. and 12' are formed by diffusion therefrom. At this time, as in the transistor on the left side of FIG. 1, if an emitter window is formed so as to overlap the edge tta of the base region 11 and impurities are introduced, a walled emitter 12 surrounded by an insulating film is formed. be done. On the other hand, if it is formed inside 1ill'H of the vine region 12''k base region 11' as in the transistor on the right side of FIG. 1, no walled emitter is formed.
この時ウォールドエミッタの場合、エミッタ側面部に面
するベース幅は、底面部のベース幅よシ狭いか同等で１
ハ電流利得ｈｐＢ ｋ十分大きくすることができる。ま
た、一方、エミッタパターンの内側に形成する場合、側
面部のベース幅は底面に比して大きく、電流利得は小さ
くなシ、コレクタエミッタ耐圧を大きくできる。In the case of a walled emitter, the base width facing the side of the emitter is narrower than or equal to the base width of the bottom.
(c) Current gain hpBk can be made sufficiently large. On the other hand, when the emitter pattern is formed inside the emitter pattern, the base width of the side surface is larger than that of the bottom surface, the current gain is small, and the collector-emitter breakdown voltage can be increased.
またエミッタとベースの形状ｋＫ化させると。Also, if the shape of the emitter and base is changed to kK.
それに対応してｈＦＢは変化する。例えば、エミッタを
内側に入れたエミツタ面積４ミクロン×１９ミクロンの
ダブルベーストランジスタのｈｐＢ ｋｌｏｏとすると
、エミッタ面積４ミクロン×４ミクロンのウォールドエ
ミッタのシングルベーストランジスタのｈＦＢは約１．
５倍の１５０になる。また。hFB changes accordingly. For example, if hpB kloo is a double base transistor with an emitter area of 4 microns x 19 microns with the emitter inside, hFB of a walled single base transistor with an emitter area of 4 microns x 4 microns is approximately 1.
It becomes 150 times 5 times. Also.
逆にエミッタ面積４ミクロンＸ４０ミクロン×２本のエ
ミッタ内（１１１１，）リプルベーストランジスタのｈ
ｉｐは０．８倍の８０になることが実験的に撫かめられ
ている。On the other hand, the emitter area is 4 microns x 40 microns x 2 ripple base transistors (1111,) inside the emitter h
It has been experimentally suggested that IP will be increased by 0.8 times to 80.
以上述べたエミッタの形状効果音利用すれば。If you use the emitter shape sound effect mentioned above.
コレクタエミッタ耐圧が必要でｈｐＢが小さくてもよい
回路にはエミッタが内側に入った大きいトランジスタを
用いればよく、コレクタエミッタ耐圧は小さくてよいか
らｈｐＢ ｋ大きくしたい素子にはウォールドエミッタ
で面積の小さいトランジスタを用いるとよいことがわか
る。For circuits that require a collector-emitter breakdown voltage and require a small hpB, a large transistor with the emitter placed inside can be used.For devices that require a large collector-emitter breakdown voltage and a small hpB, a walled emitter transistor with a small area can be used. It turns out that it is better to use
従って本発明によれは、不純物導入工程を増やすことな
く、特性の異なる２種の垂直トランジスタや逆方向トラ
ンジスタｔｔりの集積回路の中に容易に形成できる。Therefore, according to the present invention, two types of vertical transistors or reverse direction transistors tt having different characteristics can be easily formed in an integrated circuit without increasing the number of steps for introducing impurities.
次に集積注入論理素子（ＩＩＬ）とリニア素子？１つの
集積回路に形成する場合の一実施例について説明する。Next, integrated injection logic elements (IIL) and linear elements? An example of forming one integrated circuit will be described.
ＩＩＬの電流利得はコレクタ面積／ベース面積の比に比
例することが知られている。このためコレクタ面積は可
能な限シベース面積と同じ方が望ましい。従ってＩＩＬ
の電流利得を大きくするために、第３図（ａｔの構造の
ように、コレクタポリシリコン拡散領域３４をベースパ
ターン３０ａより外側にすれは、コレクタ拡散領域３３
はフイールド酸化膜３７の啄で決まシ、ベース拡散領域
３０と重ねることができ、グラフトベース領域３２以外
はコレクタとベース面積全等しくできる。これによって
ＩＩＬの逆１１ｐｇＴｈ大きくできる。It is known that the current gain of IIL is proportional to the collector area/base area ratio. For this reason, it is desirable that the collector area be as similar to the base area as possible. Therefore IIL
In order to increase the current gain of FIG.
Determined by the thickness of the field oxide film 37, it can be overlapped with the base diffusion region 30, and the areas other than the graft base region 32 can be made to have the same total area as the collector. This allows the inverse IIL to be increased by 11 pgTh.
、一方、耐圧が要求されるリニア部は、第３図には示し
てないが、第１図の右側に示すように、ベース領域１１
′の内側にエミッタ領域１２’を形成すればよく、高耐
圧リニア部と高電流利得ＩＩＬ部を、余分な工程？付加
することなく、同時に形成することができる。, On the other hand, the linear part that requires high voltage resistance is not shown in FIG. 3, but as shown on the right side of FIG.
It is only necessary to form the emitter region 12' inside the ', and the high breakdown voltage linear part and the high current gain IIL part need no extra process. They can be formed at the same time without being added.
以上のように１本発明によれは、同一基板の半導体装置
内に、所謂ウォールドエミッタ形のトランジスタとそう
でないトランジスタとを形成することによシ、比教的簡
単な工程で、特性の大幅に異なる被数種のトランジスタ
を設け、半導体装置の性能を大幅に向上させることがで
きる。As described above, according to the present invention, by forming a so-called walled emitter type transistor and a non-walled emitter type transistor in a semiconductor device on the same substrate, characteristics can be greatly improved with a relatively simple process. By providing different types of transistors, the performance of the semiconductor device can be significantly improved.
第り図及び第２図はそれぞれ本発明の一実施例倉説明す
るための平面図及びＡ−Ａ’線断面図、第３図は本発明
の他の笑施例會説明するための断面図である。
１１．１１’、３０・・・・・・ベース領域、１２．１
２’０．。
・・・エミッタ領域、１３．１３’・・・・・・コレク
タ領域。
２１・・・・・・Ｎ形基板又はエピタキシャル層、２２
゜３７・・・・・・フィールド酸化膜、２３．２３’、
３Ｂ・・・・・・ポリシリコンの酸化膜、２４．２４’
・・・・・・エミッタポリシリコン、３０ａ・・・・・
・ベースの選択酸化パターン、３１・・・・・・インジ
ェクタ％ ３２・・・・・・グラフト（外部）ベース、
３３・・・・・・コレクタ領域、３４・・・・・・コレ
クタポリシリコン拡散領域、３５・・・・・・エミッタ
領域、３６・・・・・・エミッタポリシリコンＮ子領域
。Figures 1 and 2 are a plan view and a cross-sectional view taken along the line A-A' to explain one embodiment of the present invention, respectively, and Figure 3 is a cross-sectional view to explain another embodiment of the present invention. be. 11.11', 30...Base area, 12.1
2'0. . ...Emitter region, 13.13'...Collector region. 21...N-type substrate or epitaxial layer, 22
゜37...Field oxide film, 23.23',
3B...Polysilicon oxide film, 24.24'
...Emitter polysilicon, 30a...
・Selective oxidation pattern of base, 31... Injector% 32... Graft (external) base,
33...Collector region, 34...Collector polysilicon diffusion region, 35...Emitter region, 36...Emitter polysilicon N-type region.
Claims (1)
て、エミッタ領域の縁部がベース領域の縁部よりも内側
に形成された第１のトランジスタと、順動作トラ／リス
タのエミッタ領域の縁部または逆動作トラ／２スタのコ
レクタ領域の縁部がベース領域の縁部と重なって形成さ
れた第２のトランジスタとを含むことを特徴とする半導
体装量。In a semiconductor device including two or more types of vertical transistors, a first transistor in which the edge of the emitter region is formed inside the edge of the base region, and a first transistor in which the edge of the emitter region is formed inside the edge of the base region; A semiconductor device comprising: a second transistor formed such that an edge of a collector region of an operating transistor/two-star overlaps an edge of a base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065822A JPS59191372A (en) | 1983-04-14 | 1983-04-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58065822A JPS59191372A (en) | 1983-04-14 | 1983-04-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59191372A true JPS59191372A (en) | 1984-10-30 |
| JPH0425705B2 JPH0425705B2 (en) | 1992-05-01 |
Family
ID=13298100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58065822A Granted JPS59191372A (en) | 1983-04-14 | 1983-04-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59191372A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121675A (en) * | 1979-03-12 | 1980-09-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5661138A (en) * | 1979-10-23 | 1981-05-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS57194566A (en) * | 1981-05-27 | 1982-11-30 | Hitachi Ltd | Semiconductor device and manufacture thereof |
-
1983
- 1983-04-14 JP JP58065822A patent/JPS59191372A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55121675A (en) * | 1979-03-12 | 1980-09-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5661138A (en) * | 1979-10-23 | 1981-05-26 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS57194566A (en) * | 1981-05-27 | 1982-11-30 | Hitachi Ltd | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0425705B2 (en) | 1992-05-01 |
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