JPH04255494A - Power control circuit - Google Patents

Abstract

PURPOSE:To suppress the power consumption of a motor without supplying power to the circuit part when the load is off and, at the same time, to prevent the malfunction of the motor. CONSTITUTION:A counter 4 is provided for counting the number of turned-on times of a switch SW. The state of the switch SW is switched to each other among states where an oscillation circuit 5 is operated to oscillate, where the output of the circuit section 5 is set at a H level, and where the power supply from a power source circuit section 6 is stopped in accordance with the count value of the counter 4. When the switch 4 is turned on while no power supply is made to a motor M, a trigger pulse is generated from a trigger pulse generation circuit 1 and a transistor TR1 is turned on, resulting in the power supply to each circuit section 3 from a power supply circuit section 10. When the circuit section 10 starts the power supply, a reset circuit section 3 outputs a reset signal for resetting the counter 4. A delay circuit section 5 outputs a delayed pulse by delaying the trigger pulse and the counter 4 counts the delayed pulse after resetting.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power control circuit that sets power supplied to a load in stages according to the number of input pulses generated when a switch is operated.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 4, each time a switch SW is turned on, a power control switching element Q connected in series to a motor M, which is a load, is turned on and off. A circuit for rotating and stopping M is provided. In this circuit, switch SW
When turned on, the voltage across the Zener diode ZD connected in series with the switch SW (see Figure 5(a)) is input to the trigger pulse generation circuit 1, and remains high for a certain period of time as shown in Figure 5(b). A trigger pulse that reaches the level is output from the trigger pulse generation circuit section 1. This trigger pulse causes transistors TR1, TR2, TR3
is only on for a certain period of time. When the transistor TR1 is turned on, power supply from the power supply circuit section 10 to each circuit section is started, and when the transistor TR3 is turned on, the timer circuit section 2 starts a time-limiting operation. In addition, the timer circuit section 2
During the time-limited operation, the output from the output terminal OUT of the timer circuit section 2 becomes L level as shown in FIG.
As shown in (c), power supply from the power supply circuit section 10 to each section continues. In this way, while the power supply from the power supply circuit section 10 continues, the switching element Q is turned on and power is supplied to the motor M. When the timer circuit unit 2 completes its time-limited operation and the timer expires, the output is set to H level, so that the transistor TR1 is turned off, the switching element Q is turned off, and the power supply to the motor M is stopped.

By the way, the timer circuit section 2 starts the time-limiting operation when the input to the input terminal SET becomes L level while the time-limiting operation is stopped, and during the time-limiting operation, the timer circuit section 2 starts the time-limiting operation.
It is configured to stop the time-limited operation when the input to ET becomes L level. Since the trigger pulse is input to the input terminal SET via the transistor TR3,
When a trigger pulse occurs while the time-limited operation is stopped, the time-limited operation is started and the switching element Q is turned on.
When a trigger pulse is generated during the time-limited operation, the time-limited operation is stopped and the switching element Q is turned off.

As described above, when the switch SW is turned on while the motor M is stopped, the motor M rotates, and when the switch SW is turned on again while the motor M is rotating, the motor M is stopped. Furthermore, when the time set by the timer circuit section 2 has elapsed after the motor M started rotating, the motor M automatically stops. This circuit has the advantage that no power is wasted while the motor M is stopped, since power is not supplied to the power supply circuit section 2 from the power supply when the motor M is stopped.

By the way, in the above configuration, since the operation of the switch SW only instructs the motor M to rotate and stop, the rotational speed of the motor M cannot be changed by adjusting the power supplied to the motor M. It is something. On the other hand, a circuit configuration as shown in FIG. 6 has been considered to control the power supplied to the motor M. In this circuit, the structures denoted by the same numbers as in FIG. 4 are equivalent to those in FIG. In this circuit, the microcomputer 11
By using this, the power supplied to the motor M is configured to change stepwise each time the switch SW is turned on. In other words, when the switch SW is turned on while the motor M is stopped, a small amount of power is supplied to the motor M to make it rotate at a low speed, and when the switch SW is turned on again, a larger amount of power is supplied to the motor M than before and the motor M is rotated at a high speed. When the switch SW is turned on again, the motor M
This will stop the power supply to.

However, the microcomputer 11
When using this method, it takes time and cost to develop the program, and the problem arises that it is difficult to make changes because it is necessary to review the entire program when changing the design. Therefore, it is conceivable to combine a general-purpose integrated circuit such as a counter in place of the microcomputer 11 to provide the same function. That is, the trigger pulses output from the trigger pulse generation circuit section 1 are counted by a counter, and the power supplied to the motor is set in stages according to the count value of the counter. Further, when the count value of the counter reaches the maximum value that can be counted, the power supply to the load is stopped the next time a trigger pulse is input.

[0007]

[Problems to be Solved by the Invention] By the way, if we try to prevent wasteful power consumption during the period when the motor is stopped, as shown in the circuit configuration shown in FIG. Electricity must be supplied to the parts. Therefore, when the switch is turned on, it is necessary to start feeding power from the power supply circuit section and at the same time count the fact that the switch has been turned on using a counter. Here, since the counter is supplied with power from the power supply circuit section, the counting operation of the counter is started during a period when the operation is unstable immediately after the start of power supply to the counter. Further, since the output value of the counter is not guaranteed unless it is reset after the start of power supply, the output value is not guaranteed if counting is started at the same time as the power supply from the power supply circuit section starts.

That is, in a configuration using a counter, there is a problem in that it is difficult to prevent wasteful power consumption and guarantee the output value of the counter at the same time. The present invention aims to solve the above problems,
An attempt is made to provide a power control circuit that uses a counter to set the power supplied to a load in stages, prevents wasteful power consumption, and allows the counter to operate reliably. It is something to do.

[0009]

[Means for Solving the Problems] The present invention includes a counter that counts the number of occurrences of input pulses, and a power supply setting section that sets the power supplied to the load in a plurality of stages according to the count value of the counter. The power supply setting section is a power control circuit that stops power supply to the load when the next input pulse occurs when the count value of the counter reaches the maximum value. A power supply circuit section that starts power supply when receiving a pulse, a reset circuit section that generates a reset signal to reset the counter when the power supply circuit section starts supplying power, and a reset circuit section that outputs a delayed pulse that is a delay of the input pulse and resets the counter. A delay circuit section is provided that causes a counter to count delayed pulses after being reset by a reset signal.

0010

[Operation] According to the above configuration, the number of occurrences of input pulses is counted by a counter, and the power supplied to the load is set in stages according to the count value of the counter, and the power supply to the load is stopped. Since a power supply circuit section is provided that starts power supply when it receives an input pulse when the load is off, there is no unnecessary power consumption when the load is off. In addition, there is a reset circuit section that generates a reset signal to reset the counter at the start of power supply by the power supply circuit section, and a reset circuit section that outputs a delayed pulse that delays the input pulse and outputs the delayed pulse after the counter is reset by the reset signal. Since the counter is provided with a delay circuit unit that performs counting, the counter can be reset by a reset signal generated at the start of power supply by the power supply circuit unit and the output value of the counter can be guaranteed, and after the counter is reset, By using a counter to count delayed pulses obtained by delaying input pulses, counting can be started after the operation of the counter has stabilized. As a result, the counter operates reliably and malfunctions do not occur.

[0011]

[Example] This example shows an example in which the load is a motor and the power supplied to the motor is set in two stages, but the type of load and the number of stages set for supply power are not necessarily limited to this. It's not a thing. As shown in FIG. 1, a switching element Q made of a field effect transistor is connected in series to a motor M as a load, and this series circuit is connected to a power source. The power supplied to the motor M is set in two levels depending on whether the switching element Q is turned on continuously or intermittently, and when the switching element Q is turned off, the motor M stops. When the switching element Q is turned on intermittently, the power supplied to the motor M is small, so the motor M rotates at a lower speed, and when the switching element Q is turned on continuously, the power supplied to the motor M is lower than when it is turned on intermittently. Since the power supplied to the motor M increases, the motor M rotates at high speed. The state in which the switching element Q is turned off, intermittently turned on, and continuously turned on can be switched each time the switch SW is turned on.

[0012] As the switch SW, a switch such as a push button switch that is turned on only during operation is used. Switch SW is connected in series with resistor R1 and Zener diode ZD, and this series circuit is connected across the power supply. The connection point between the resistor R1 and the Zener diode ZD is connected to the input terminal of the trigger pulse generation circuit section 1, and the trigger pulse generation circuit section 1 generates a trigger pulse that becomes H level for a certain period of time when the switch SW is turned on. . That is, although the period during which the switch SW is on is not constant, when the switch SW is turned on, the trigger pulse generation circuit section 1 outputs a trigger pulse with a constant width determined by the resistors R2 to R4 and the capacitor C1. . The trigger pulse generation circuit section 1 is supplied with power from both ends of the Zener diode ZD while the switch SW is on, and power consumption in the trigger pulse generation circuit section 1 is prevented from occurring during the period when the switch SW is off. . In this way, a trigger pulse is generated, which becomes the input pulse.

When a trigger pulse is generated from the trigger pulse generating circuit section 1, the transistors TR1 and TR2 are turned on while the trigger pulse is at H level. The transistor TR1 is inserted between the power supply and the power supply circuit section 10, and when the transistor TR1 is turned on, power supply from the power supply circuit section 10 to each circuit section is started. When power supply from the power supply circuit section 10 is started, the reset circuit section 3
A reset signal is output from. The reset circuit section 3 is
It is constructed using one of two monostable multivibrators built into the integrated circuit IC1. The reset circuit section 3 is triggered by the start of power supply from the power supply circuit section 10, and outputs a pulse with a constant time width determined by the resistor R5 and the capacitor C2 from the output terminal OA. This pulse becomes a reset signal and is input to the reset terminal MR of the counter 4 to reset the counter 4. The reset signal is also input to the set terminal SET of the timer circuit section 2 via the transistor TR3, and the timer circuit section 2 starts the time-limiting operation from the time the reset signal is generated.

The timer circuit section 2 has an integrated circuit IC2 as its main component, and is configured to start the time-limiting operation when the input to the set terminal SET becomes L level when the time-limiting operation is stopped. has been done. Therefore, when the reset signal rises, transistor TR3
is turned on and the input to the set terminal SET becomes L level, thereby starting the time-limited operation. The time limit in the timer circuit section 2 is determined by resistors R6 and R7.
and capacitor C3. The output terminal OUT of the timer circuit section 2 is connected to the base of the transistor TR1, and the output from the output terminal OUT of the timer circuit section 2 becomes L level during the time-limiting operation. The transistor TR1 is kept in the on state. That is, after a trigger pulse is generated and transistors TR1 and TR2 are turned on, when the trigger pulse falls, transistor TR2 is turned on.
is turned off, but the transistor TR1 remains on while the timer circuit section 2 continues its time-limiting operation. Therefore, when the power supply circuit section 10 starts supplying power to each circuit section in response to a trigger pulse, the power supply continues until the timer circuit section 2 stops its time-limited operation. In the timer circuit section 2, when the time limit elapses, the output from the output terminal OUT becomes H level, turning off the transistor TR1, and also turning off the reset terminal RES.
Even when the input to the output terminal becomes L level, the output terminal OUT
The output from the transistor TR1 is set to H level to turn off the transistor TR1.

By the way, the trigger pulse output from the trigger pulse generation circuit section 1 is also input to the delay circuit section 5. The delay circuit section 5 is a circuit 2 built in the integrated circuit IC1.
It is configured using one of two monostable multivibrators, and is triggered by inputting to input terminal IB a signal in which the trigger pulse is delayed by a time constant set by resistor R8 and capacitor C4. ,
The output of the non-inverting output terminal OB is set to H level for a certain period of time set by the resistor R9 and the capacitor C5. That is, the output from the non-inverting output terminal OB of the delay circuit section 5 becomes a delayed pulse obtained by delaying the trigger pulse by a certain period of time. The delayed pulse is connected to the inverting input terminal NC of counter 4.
It is input to P.

The counter 4 is made up of a Johnson counter, and has three output terminals O1 to O3. Each output terminal O1 rises each time the input to the inverting input terminal NCP rises.
It is configured to sequentially and selectively set the outputs of .about.O3 to H level. That is, when the counter 4 starts supplying power from the power supply circuit section 10 as shown in FIG. 3(a) by turning on the switch SW, the counter 4 receives an output from the reset circuit section 3 as shown in FIG. 3(b). The output terminals O1 to O3 are reset by a reset signal, and the outputs of all output terminals O1 to O3 are temporarily set to L level. After that, as shown in Figure 3(d), the trigger pulse was delayed (Figure 3(c) is resistor R8
A delay pulse (indicating the potential at the connection point of capacitor C4 and
It becomes a level. Here, by inputting the output of the non-inverting output terminal OB of the delay circuit section 5 to the inverting input terminal NCP of the counter 4, the sum of the delay time by the delay circuit section 5 and the pulse width of the delayed pulse can be calculated. , can be used to reset the counter 4, and the counter 4 can be reset more reliably than when a delayed pulse is input to the non-inverting input terminal CP. After that, when the switch SW is turned on, the output of the output terminal O2 and the output of the output terminal O3 are selectively set to H.
become the level. The output terminal O1 of the counter 4 is not connected to any other circuit section, but the output terminal O2 is connected to the oscillation circuit section 6.
The output terminal O3 is connected to control the time-limiting operation of the timer circuit section 2.

The oscillation circuit section 6 is connected to the output terminal O of the counter 4.
When the output of counter 2 is at H level, the oscillation operation is stopped and the output level is set to H level, and when the output level of output terminal O2 of counter 4 is at L level, resistors R10, R11 and capacitor C6 It is configured to perform an oscillation operation with a period and duty ratio determined by. That is, when the switch SW is turned on and power supply from the power supply circuit section 10 is started, and the output of the output terminal O1 of the counter 4 becomes H level, the output of the output terminal O2 is L level, so at this time, The oscillation circuit section 6 performs an oscillation operation at a constant cycle. switch SW
When is turned on again, the output of the output terminal O2 of the counter 4 becomes H level and the oscillation operation is stopped.

The output of the oscillation circuit section 6 is inputted to the control terminal (gate) of the switching element Q via the compensation circuit section 9. This compensation circuit section 9 allows the output of the oscillation circuit section 6 to pass through, controls the switching element Q to be turned on and off by the output of the oscillation circuit section 6, and generates a turn-off waveform of the switching element Q when the switching element Q is turned off. improve.

A series circuit of a pair of resistors R12 and R13 is connected to the output terminal O3 of the counter 4, and both resistors R1
2, the connection point of R13 is connected to the inverting input terminal of the comparator circuit section 7. A reference voltage output from the reference voltage generation circuit section 8 is input to the non-inverting input terminal of the comparison circuit section 7 . That is, the output of the output terminal O3 of the counter 4 is connected to the resistor R1.
2. After being divided by R13, the reference voltage is input to the comparator circuit section 7, and when the output of the output terminal O3 of the counter 4 is at the L level, the output of the comparator circuit section 7 is at the H level. level, and when the output of the output terminal O3 is at the H level, the output of the comparison circuit section 7 is set to be at the L level. Since the output terminal of the comparison circuit section 7 is connected to the reset terminal RES of the timer circuit section 2, the output of the output terminal O3 of the counter 4 cannot go to H level when the timer circuit section 2 is in time-limiting operation. For example, the timer circuit section 2 is reset and the time-limiting operation is stopped. When the time limit operation of the timer circuit section 2 stops, the output of the output terminal OUT of the timer circuit section 2 becomes H level, and the power supply circuit section 1
Since the power supply from 0 to each circuit section is stopped and the output of the oscillation circuit section 6 disappears, the switching element Q is turned off and the motor M is stopped. The reset terminal RES of the timer circuit section 2 is pulled up by the resistor R14 and the capacitor C7, and is connected to the output terminal O of the counter 4.
The time-limited operation continues until the output of No. 3 becomes H level.

According to the above configuration, when the switch SW is turned on as shown in FIG. 2(a) while the motor M is stopped, power supply from the power supply circuit section 10 is started, and as shown in FIG.
A reset signal is output as shown in (d). At the same time as the counter 4 is reset by this reset signal,
The timer circuit section 2 starts a time-limiting operation. After that, when the delayed pulse output from the delay circuit section 5 is input to the counter 4, the output terminal O of the counter 4 is input as shown in FIG. 2(e).
The output of 1 becomes H level. At this time, the output of the output terminal O2 of the counter 4 is at the L level, so the output terminal O2 of the counter 4 is at the L level, so as shown in FIG. 2(c).
The oscillation circuit section 6 performs an oscillation operation, and the switching element Q is intermittently turned on. That is, FIG. 2(b)
As shown in FIG. 2, the power supplied to the motor M is relatively small.

When the timer circuit section 2 is in a time-limited operation and the switch SW is turned on as shown in FIG. 2(a), the output of the output terminal O2 of the counter 4 is turned on as shown in FIG. 2(f). Since the signal becomes H level, the oscillation circuit section 6 stops the oscillation operation and outputs the H level as shown in FIG. 2(c). As a result, the switching element Q is turned on continuously, and the power supplied to the motor M increases as shown in FIG. 2(b).

Furthermore, as shown in FIG. 2(c), the switch S
When W is turned on again, the output of the output terminal O3 of the counter 4 momentarily becomes H level, as shown in Figure 2(g).
The output of the comparison circuit section 7 becomes L level and the timer circuit section 2
The timed operation stops. As a result, the power supply circuit section 10
Since the power supply to each circuit section is stopped, the output of the oscillation circuit section 5 becomes L level as shown in FIG. 2(c), and
) Motor M stops as shown below.

As described above, each time the switch SW is turned on, the state in which the power supplied to the motor M is small → the state in which the power supplied to the motor M is large → the state in which the motor M stops is repeated in this order. It is. On the other hand, motor M
When the time limit operation of the timer circuit section 2 ends while the switch SW is turned on and the motor M is rotating while the motor M is stopped, the timer circuit section 2 is turned on as shown in the right half of FIG. The motor M automatically stops when the time-limited operation ends.

[0024]

[Effects of the Invention] As described above, the present invention counts the number of occurrences of input pulses using a counter, and sets the power supplied to the load in stages according to the counted value of the counter. Since a power supply circuit section is provided that starts power supply when an input pulse is received while the load is off, there is no unnecessary power consumption when the load is off. In addition, there is a reset circuit section that generates a reset signal to reset the counter at the start of power supply by the power supply circuit section, and a reset circuit section that outputs a delayed pulse that delays the input pulse and outputs the delayed pulse after the counter is reset by the reset signal. Since the counter is provided with a delay circuit unit that performs counting, the counter can be reset by a reset signal generated at the start of power supply by the power supply circuit unit and the output value of the counter can be guaranteed, and after the counter is reset, By using a counter to count delayed pulses obtained by delaying input pulses, counting can be started after the operation of the counter has stabilized. As a result, there is an advantage that the counter operates reliably and malfunctions do not occur.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment.

FIG. 2 is an explanatory diagram of the operation of the embodiment.

FIG. 3 is an explanatory diagram of the operation of the embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is an explanatory diagram of the operation of a conventional example.

FIG. 6 is a block circuit diagram showing another conventional example.

[Explanation of symbols]

3 Reset circuit section 4 Counter 5 Delay circuit section 10 Power supply circuit section

Claims (1)

[Claims] 1. A counter that counts the number of occurrences of input pulses, and a power supply setting section that sets the power supplied to the load in a plurality of stages according to the count value of the counter, the power supply setting section being configured to In a power control circuit that stops power supply to the load when the next input pulse occurs when the count value has reached the maximum value, power supply starts when an input pulse is received while power supply to the load is stopped. a power supply circuit section; a reset circuit section that generates a reset signal for resetting a counter when the power supply circuit section starts supplying power;
1. A power control circuit comprising: a delay circuit section that outputs a delayed pulse that is a delayed input pulse, and causes the counter to count the delayed pulse after the counter is reset by a reset signal.