KR960000826Y1 - Reset timing automatic controlled circuit - Google Patents

Abstract

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Description

Reset timing automatic adjustment circuit

Figure 1 (a) is a conventional reset circuit diagram

(b) is an equivalent circuit diagram of (a)

2 is a timing diagram of a conventional reset circuit.

3 is a reset circuit block diagram of the present invention.

4 is a circuit diagram of the present invention

* Explanation of symbols for main parts of the drawings

3,4 switch 3,6 comparator

7a: timer 7b: counter

8: latch 9: decoder

11: analog switch 12: RC circuit

13: logic OR gate I ₁ , I ₂ : inverter

The present invention relates to the provision of a timing signal of a device having a reset timing. In particular, in the reset operation of the device, the time after the power "on" is counted to the rising time and then driven by the most suitable RC circuit. This is to facilitate the irregular and inappropriate operation of the device by zooming.

In the conventional reset timing adjusting circuit, as shown in (a) of FIG. 1, the diode R and the resistor R are connected in parallel to prevent reverse current during power " off " The condenser C is connected in series and is connected to the constant voltage terminal Vcc and the reset terminal RESET of the element 1.

Here, the reset terminal RESET of the device 1 is a negative logic and should be kept longer than the time t reg required for the device 1 when the power is "on". As shown in FIG. When the constant voltage (Vcc) becomes 5V for a certain time, the logic gradually becomes positive due to the AC characteristics of the capacitor.

The conventional reset timing adjusting circuit of this configuration has a voltage V (t), an initial voltage (Vo = V (to)) and a time constant t = RC, which decrease with time as shown in FIG.

V (T) = Voe- (t-to) / RC

Becomes

So in the natural state The time taken to decrease by must be as much as RC.

At this time The time to decrease to 0.368 is roughly greater than the reset cycle of the device, causing a reset operation.

However, in the above case, the configuration is simple, but when there is a change in "power", a fatal operational error may occur.

In other words, if the "on" time of "power" is late, even though the time t reg required by the device must be greater than the t delay as shown in FIG. There is a problem that is missing.

The present invention has been made to solve the above problems, in particular to be able to selectively handle the reset timing according to the "power" of the device.

That is, start and up time of the power supply are compared by using a comparator, counted by a timer and a counter, and then the RC circuit corresponding to the count value is selected through a latch to drive the device. It is characterized by that.

Hereinafter, described in detail by the accompanying drawings as follows.

The configuration of the present invention compares the power supply start time and the UP TIME with the multi-stage RC circuit 12 and the logic-orgate 13 from which the reset timing of the device can be selected as shown in FIG. Two comparators (5) and (6), reset timing counting means for counting the reset timing of the power supply by counting the time from rising after the power-up to the rising time using the two comparator output signals, and a count value for the reset timing. A decoder 9 for decoding the signal and an analog switch 11 for receiving the decoding value and transmitting / suppressing the constant voltage Vcc to the RC circuit corresponding to the value.

In the above-described reset timing counting means, a timer 7A which operates between a power start time and an up time and outputs a constant level, a counter 7B that calculates this timer output, and a reset corresponding to a count value. A latch 8 for holding timing and an inverter I ₁ (I ₂ ).

The operation and effects of the present invention configured as described above are similar to those of the entire circuit diagram of FIG. 4, and the output of the reset terminal receives a signal from the comparators 5 and 6 so that the circuit operates.

If the switches 3 and 4 in front of the comparators 5 and 6 are open, an INTERRUPT request does not occur.

In addition, the positive logic signal from the comparator 5 operates by enabling the timer 7A, and the counter 7B starts counting for that time.

At this time, when "power" becomes positive logic, the operation of the timer 7A stops and at the same time the count value of the counter 7B is transmitted to the latch 8 for operating the module corresponding to the time in time, and almost At the same time, the timer 7A and the counter 7B are returned to the reset state by a signal passing through the inverter I ₁ (I ₂ ) from the output of the comparator 6.

The output signal from the latch 8 is applied to the multi-stage RC circuit 12 through the decoder 9 and the analog switch 11.

At this time, the analog switch 11 receives a signal applied from the decoder 9 and transmits and suppresses a constant voltage (Vcc) value to the RC circuit 12.

Thus, the conventional RC circuit has only one time constant value, and if it has a longer power "on" response, no reset is required.

However, if the present invention is applied, it is a useful design that can drive the RC circuit of the desired time constant with only one setting operation of the switch.

Claims (2)

(correction) A multi-stage RC circuit 12 and or gate 13 capable of selecting reset timing of the device; Comparator (5) (6) which compares and outputs a start power supply and UP TIME, Reset timing counting means for setting reset timing by counting from power-on to rising to time using the two comparator outputs; A decoder 9 for decoding the reset timing counting output; And an analog switch (11) configured to receive the decoding value and transmit / suppress a constant voltage (Vcc) to the RC circuit corresponding to the value. (Newly set forth in paragraph 1), The reset timing counting means is provided with a timer 7A which is operated between the start time and the operating time to produce a constant output; A counter 7B for calculating the timer output time; A reset timing automatic regulation circuit, comprising: a latch (8) for setting reset timing corresponding to a count value and an inverter (I ₁ ) (I ₂ ).