KR900009234Y1 - Input circuit for directing signal - Google Patents

Abstract

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Description

Command signal input circuit

1 is a conventional circuit diagram.

2 is a circuit diagram of the present invention.

3 is another exemplary configuration of the dotted line circuit portion of FIG.

4 is another exemplary configuration of the dotted line circuit portion of FIG.

* Explanation of symbols for main parts of the drawings

10: oscillator 11: drive circuit

12: command unit 13: operation execution output unit

OP ₁₃ : Comparator R ₂₆ -R ₃₁ : Resistance

D ₁₂ : Diode C ₁₄ : Capacitor

I: Inverter B: Buffer

F / F ₁ , F / F ₂ : JK flip flop

The present invention relates to a power input circuit that initiates an operation when a user presses a driving push button switch while the control power is input, which is in standby. In particular, a command for instructing an operation after the control power is in standby is input. Once this is done, it is applicable to all circuit schemes that initiate the desired operation.

Conventionally, as shown in FIG. 1, as shown in FIG. ₁ , the output signals of the light emitting diode flashing oscillator 10 and the oscillator 10 indicating the standby state when the control power supply VCC ₁ is inputted are provided. A chattering prevention JK flip that receives a command from a light emitting diode driving circuit 11 that has driven a light emitting diode LED ₁ and a command unit 12 and a command unit 12 instructing certain operations to prevent a chattering phenomenon After receiving the output of the flop (F / F ₂ ) and the JK flip-flop (F / F ₂ ) to perform the operation, and receives the state transition of the oscillator 10 according to the command of the command unit 12 to perform the operation JK flip-flop (F / F ₁ ) for outputting the dragon output signal, and the operation execution output unit 13 for outputting the operation execution signal.

The operation thereof is as follows.

When the control power supply (VCC ₁ ) is input, each JK flip-flop (F / F ₁ ) and (F / F ₂ ) is clear terminal (CL) during the time constant set by the resistor (R ₁ ) and the capacitor (C ₁ ). ₁ ), High signal is inputted to (CL ₂ ) and it becomes the operating state, and output terminal of flip-flop (F / F ₂ ) The high signal indicated by is applied to the terminal PR ₁ of the JK flip-flop F / F ₁ to output the high signal to the output terminal Q ₁ of the flip-flop F / F ₁ .

The reason is that the output terminal Q ₁ is lower than the time when the output terminal Q ₁ signal becomes low due to the clear terminal CL ₁ signal. And the time at which the output terminal Q ₁ signal becomes high by the terminal PR ₁ is fast.

In addition, the power supply (VCC) is supplied to each terminal J ₁ , K ₁ , J ₂ , K ₂ , and CP ₂ by the time set by the resistor R ₂ and the capacitor C ₂ . ₁ ) is applied to the output terminal (Q ₂ ) by the signal input to the clear terminal (CL ₂ ), low, output terminal The high state signal is maintained while the high state signal is maintained at the output terminal Q ₁ of the JK flip-flop F / F ₁ .

In addition, the resistance (R ₃ -R _8), a capacitor (C ₃₎ and a comparator output signal of the comparator (OP ₁₎ by the oscillator (10) consisting of (OP ₁₎ is a constant repetition period for high and low state According to the signal state, the transistor Tr ₁ is driven to flash the light emitting diode LED ₁ to indicate that it is in standby. In this state, when the push button switch PB ₁ in the command unit 12 is pressed, the power supply VCC ₁ is input to the terminal PR ₂ of the JK flip-flop F / F ₂ through the resistor R ₁₄ . Accordingly, the output terminal Since the signal is low and the terminal PR ₁ is also in a low state, the signal of the output terminal Q ₁ remains high but the output of the clock input terminal CP ₁ can be reversed.

In addition, since the non-inverting (+) input becomes higher than the inverting (-) input terminal, the output of the comparator OP ₁ makes the clock input terminal CP ₁ signal high, so the pushbutton switch PB ₁ If the clock input terminal CP ₁ signal is low before being pressed, the output signal of the output terminal Q ₁ is inverted by the state transition to detect that the push button switch PB ₁ has been pressed, and thereby the desired operation. Will be executed.

At this time, the output (Q ₂₎ of the JK flip-flop (F / F ₂₎ is high, the output Maintains a low state continues and push-button switch (PB _1), a comparator (OP ₁₎ reversal of when reverted (-) output of the input is a high level than the non-inverting (+) input comparator (OP ₁₎ is It remains low and the clock input (CP ₁ ) signal is also kept on low power, so there is no further state change.

Here, VCC ₂ is the power supplied from the push button switch PB ₁ is pressed.

However, in such a conventional circuit, when the push button switch PB ₁ is pressed while the output of the oscillator is high, the output signal of the oscillator, that is, the input signal of the clock input terminal CP ₁ is pushed to the push button switch PB ₁ . Since the signal of the output terminal Q ₁ does not change accordingly as it is not depressed, there is a problem in that it cannot perform a desired operation, and when the push button switch PB ₁ is pressed, the comparator OP ₁ Even when the output terminal signal is in the low state, the time when the push button switch PB ₁ is pressed and the output of the comparator OP ₁ changes, that is, the time when the signal of the clock input terminal CP ₁ changes is the output terminal Q ₂ signal. is changed from high to low JK flip-flop (F / F ₁₎ terminals because shorter than the time for changing the (PR ₁₎ from high to low there is a problem that is able to detect that jyeotdaneun pressed the push-button switch (PB ₁₎ of The.

The subject innovation is such when control power is applied to solve the conventional problems clock input terminal (CP ₁₎ a state the push button switch, making a preceding state transition occurs (PB ₁₎ is only pressed, a clock input terminal (CP ₁ ) Is delayed between the time when the push button switch PB ₁ is depressed and the time when the terminal PR ₁ of the JK flip-flop is released and the time when the clock input terminal CP ₁ is transferred to the state. Its purpose is to ensure reliable and accurate circuit operation.

The present invention will be described below with reference to the accompanying drawings.

As shown in FIG. 2, the present invention breaks the connection between the output terminal of the comparator OP ₁ and the clock input terminal CP ₁ in the circuit configuration of the conventional FIG. ₁ , and the non-inverting (+) of the comparator OP ₁ The diode (D ₂ ) and the connection terminal (③) connected to the input terminal are blocked, and the comparator (OP) is connected between the clock input terminal CP ₁ , the JK flip-flop F / F ₂ , and the terminal PR ₂ . ₁₃ ), a resistor (R _26- R ₃₁ ), a capacitor (C ₁₄ ) and a diode (D ₁₂ ) is connected and configured.

Referring to the effect of the present invention configured as described above are as follows.

In FIG. 2, when the control power supply VCC ₁ is input, the oscillator 10 starts oscillation, and the transistor Tr ₁ driven by receiving the output of the oscillator 10 is repeatedly turned on and off, thereby emitting light. The diode LED ₁ blinks to indicate that it is in standby.

The output terminal (Q ₂₎ of the JK flip-flop (F / F ₂₎ is low, the output terminal The "high" terminal PR ₁ remains high and the output terminal Q ₁ remains high.

In this way, the operation is the same as that of the first degree. However, in the conventional case, the signal appearing at the clock input terminal CP ₁ is repeated in a low state and a high state. However, in the present invention, after the control power supply VCC ₁ is input, the signal is output until the push button switch PB ₁ is pressed. It maintains the preceding state of state transition that reverses.

That is, when the control power supply VCC ₁ is input, the resistances R _20- R ₂₉ are adjusted such that the potential of the inverting (-) input terminal of the comparator OP ₁₃ is higher than that of the non-inverting (+) input terminal. The clock input terminal CP ₁ of the JK flip-flop F / F ₁ to maintain the preceding state of the state transition, and the terminal ③ is connected directly to one end of the resistor R ₁₄ so that the push button switch ( When PB ₁ ) is pressed, the signal at terminal PR ₂ is high and the output terminal Q ₂ is high and output terminal is To the low state and the terminal PR ₁ .

That is, after the preset state of the JK flip-flop F / F ₁ is released, the output of the comparator OP ₁₃ is output after the time constant time elapses by the resistors R ₃₀ , R ₃₁ , and the capacitor C ₁₄ . The inversion causes the clock input terminal CP ₁ to transition state, thereby inverting the signal of the output terminal Q ₁ .

3 and 4 show another configuration of the circuit portion indicated by the dotted line in FIG. 2, which is the clock input terminal CP _{1 of} the JK flip-flop F / F ₁ when the _second power supply VCC ₁ is input. ) Signal is maintained in the preceding state of the state transition, and the terminal (③) is connected to one end of the resistor (R ₁₄ ) and the push button switch PB ₁ is pressed to free the JK flip-flop (F / F ₁ ). After the set is released, the clock input terminal after a certain time has elapsed by a time delay circuit composed of an even number of inverters I as shown in FIG. 3 or one or more buffers B as shown in FIG. The output terminal Q ₁ is inverted by transferring the (CP ₁ ) signal.

In this way, the present invention operates the JK flip-flop circuit's clock input terminal signal when the control power is supplied, and makes the state of the clock input terminal signal only when the push button switch is pressed, and also push button switch. It is to provide a power input circuit capable of performing a more sure and accurate circuit operation by performing a time delay between the time of releasing the terminal (PR ₁ ) signal when is pressed and the time of state transition of the clock input terminal. .

Claims (3)

A light emitting diode flashing oscillator 10 indicating the standby state when the control power supply VCC ₁ is input, and a light emitting diode driving circuit 11 driving the light emitting diode LED _{1 in response} to an output signal of the oscillator 10; Command unit 12 for instructing a certain operation, chattering prevention JK flip-flop (F / F ₂ ) and the JK flip-flop (F / F ₂ ) to prevent chattering under the command of the command unit 12 JK flip-flop (F / F ₁ ) to receive the output of the operation to enable the operation after receiving the state transition of the oscillator 10 in accordance with the command of the command unit 12 and outputs the output signal for operation execution In a command signal input circuit connected to an operation execution output unit 13 for outputting a performance signal, the output terminal of the comparator OP _{1 in} the oscillator 10 and the clock input terminal of the JK flip-flop F / F ₁ ( the clock input terminal of the diode (D ₂₎ and connection terminals (3) connected between a CP ₁₎ block, and at the same time (CP ₁₎ Command signal composed by connecting comparator (OP ₁₃ ), resistor (R ₂₆ -R ₃₁ ), capacitor (C ₁₄ ) and diode (D ₁₂ ) between the terminal (PR ₂ ) and JK flip-flop (F / F ₂ ) Input circuit. The command signal input circuit according to claim 1, wherein an even number of inverters (I) are connected in series between the clock input terminal (CP ₁ ) and the terminal (PR ₂ ) of the JK flip-flop (F / F ₂ ). The instruction according to claim 1 or 2, wherein at least one buffer (B) is connected in series between the clock input terminal (CP ₁ ), the JK flip-flop (F / F ₂ ), and the terminal (PR ₂ ). Signal input circuit.