JPH04255034A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To normally operate an emulation CPU even when the emulation CPU is in a runaway state generated due to the OFF of a power supply for a debugged device by allowing a clock abnormality signal storing circuit to store clock abnormality data as a clock abnormality signal. CONSTITUTION:A clock abnormality detecting circuit 5 outputs a clock abnormality signal and sends the output signal to an emulator control part 2 and the clock abnormality storing circuit 4. The circuit 4 stores the clock abnormality signal as clock abnormality storing data. Even when processing other than the operation of the emulator CPU 3 is executed through the control function of the control part 2, the existence of a clock abnormality state in the debugged device (target system) 6 can be clearly stored by the storing function of the circuit 4. In addition, the processing steps of the operation of the CPU 3 is checked.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-circuit emulator, and more particularly to an in-circuit emulator used for system recovery in response to a clock abnormality in a target system.

0002

2. Description of the Related Art A block diagram of a conventional in-circuit emulator is shown in FIG. As shown in FIG. 3, the conventional in-circuit emulator 7 includes an emulator control section 8, an emulation CPU 9, and a clock abnormality detection circuit 10, which are used for controlling the entire in-circuit emulator, in correspondence with the target system 11. It is configured. Further, FIG. 4 is a flowchart corresponding to the operation of the emulator control section 8 in this conventional example.

In FIG. 3, the emulation CPU 9
However, in a state where the target system 11 is not operating according to the program (hereinafter referred to as a break state), the emulator control unit 8 controls the operation of the emulation CPU 9 as necessary, such as reading the memory of the target system 11. operated (step 20)
3) Control of the target system 11 is performed.

[0004] Furthermore, the clock of the target system 11 is input to the clock abnormality detection circuit 10 in advance and monitored, and the amplitude and period of this clock are
If it deviates from the predetermined reference value, the clock abnormality detection circuit 1
0, the clock is detected as abnormal, and a clock abnormality signal is output and sent to the emulator control section 8. Therefore, checks of the operating state of the target system 11 and the like are read into the emulator control unit 8 as necessary.

[0005] Regarding the emulation CPU operation (step 203), if the target system 11 is not operating normally, the emulation CPU
Since the operation does not work correctly, the clock abnormality signal is read out (step 201), the abnormal signal is checked (step 202), and if an abnormality is detected, avoidance processing such as abnormality reporting regarding the target system 11 (step 204) is performed. It will be done.

[0006]

Problem to be Solved by the Invention In the conventional in-circuit emulator described above, the emulation C
If the power of the target system is turned off and on in a break state where the PU 9 is not operating according to the program of the target system 11, noise will be generated in the target probe connecting the power of the target system 11 and the clock abnormality detection circuit 10. Or, an erroneous signal intervenes, causing the emulation CPU 9 to go out of control. Even if the target system 11 is in a normal operating state, the emulator control section 8 cannot control the operation of the emulation CPU 9, and the emulation CPU 9 itself The disadvantage is that it is not possible to maintain normal operation.

[0007]

[Means for Solving the Problems] An in-circuit emulator of the present invention includes a clock abnormality detection circuit that detects a clock abnormality in a debugged device and outputs a predetermined clock abnormality signal, and a clock abnormality detection circuit that receives the clock abnormality signal. , a clock abnormality signal holding circuit that holds the clock abnormality signal as clock abnormality data, an emulation CPU that controls the operation of the device to be debugged, and an operation of the clock abnormality detection circuit, the clock abnormality signal holding circuit, the emulation CPU, etc. and an emulation control section for controlling.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, the in-circuit emulator 1 of this embodiment includes an emulator control section 2 used for controlling the entire in-circuit emulator, and an emulation control section 2, which corresponds to the target system 6.
It is configured to include a PU 3, a clock abnormality signal holding circuit 4, and a clock abnormality detection circuit 5. Further, FIG. 2 is a flowchart corresponding to the operation of the emulator control section 2 in this conventional example.

As is clear from FIG. 1, in this embodiment, compared to the conventional in-circuit emulator,
A new clock abnormality signal holding circuit 4 is provided,
This is a feature of the present invention. As in the case of the conventional example, the amplitude and period of the clock of the target system 6 are constantly monitored by the clock abnormality detection circuit 5, and if the amplitude or period of the clock deviates from a predetermined reference value, a clock abnormality is detected. A clock abnormality signal is output from the detection circuit 5 and sent to the emulator control section 2 and the clock abnormality signal holding circuit 4. In the clock abnormality signal holding circuit 4, once a clock abnormality signal is inputted, the clock abnormality signal is held as clock abnormality holding data. Due to the function of holding the clock abnormal signal by the clock abnormal signal holding circuit 4, even when processing other than the operation of the emulation CPU 3 is performed through the control action of the emulator control unit 2, the clock abnormal state in the target system 6 can be maintained. The presence/absence of the emulation CPU 3 is maintained in a clear form, making it possible to check the operation of the emulation CPU 3 at the processing stage.

Next, the operation flowchart of the emulator control section 2 shown in FIG. 2 will be explained. As is clear from FIG. 2, unlike the conventional example, preprocessing for the operation of the emulation CPU 3 (step 107) is added.

First, clock abnormality holding data is read out from the clock abnormality signal holding circuit 4 (step 103).
, the presence or absence of a clock abnormality in the target system 6 is checked (step 104), and if there is an abnormality, a request to initialize the emulation CPU 3 is issued, and the emulation CPU 3 is initialized (step 10).
5). In addition, in preparation for holding the clock abnormality signal corresponding to the next clock abnormality, the clock abnormality signal holding circuit 4 transmits a signal for clearing the previous clock abnormal data already held in the clock abnormality signal holding circuit 4. to clear the voltage abnormality data in the clock abnormality signal holding circuit 4 (step 106). After completing these series of processes, the emulation CPU 3
The following operation processing is performed (step 107). Note that if there is an abnormality in step 102, avoidance processing such as reporting an abnormality regarding the target system 11 (step 108) is performed.

[0013]

As described above, the present invention enables the emulator control unit to control the operation even when the emulation CPU runs out of control due to the power cut-off of the target system, which is the device to be debugged. This has the effect of allowing the emulation CPU to operate normally.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an operation flowchart of the emulator control section of the embodiment.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is a diagram showing an operation flowchart of a conventional emulator control section.

[Explanation of symbols]

1, 7 In-circuit emulator 2, 8
Emulator control section 3, 9 Emulation CPU 4 Clock abnormality signal holding circuit 5, 10 Clock abnormality detection circuit 6, 11
target system

Claims (1)

[Claims] 1. A clock abnormality detection circuit that detects a clock abnormality of a device to be debugged and outputs a predetermined clock abnormality signal, and receives the clock abnormality signal and holds the clock abnormality signal as clock abnormality data. A clock abnormality signal holding circuit, an emulation CPU that controls the operation of the device to be debugged, and an emulation control section that controls the operations of the clock abnormality detection circuit, the clock abnormality signal holding circuit, the emulation CPU, etc. In-circuit emulator.