JPH04253359A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04253359A JPH04253359A JP3008832A JP883291A JPH04253359A JP H04253359 A JPH04253359 A JP H04253359A JP 3008832 A JP3008832 A JP 3008832A JP 883291 A JP883291 A JP 883291A JP H04253359 A JPH04253359 A JP H04253359A
- Authority
- JP
- Japan
- Prior art keywords
- adhesive tape
- adhesive
- semiconductor
- semiconductor chip
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000002390 adhesive tape Substances 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 18
- 239000000853 adhesive Substances 0.000 claims description 23
- 230000001070 adhesive effect Effects 0.000 claims description 23
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 229920001187 thermosetting polymer Polymers 0.000 claims description 6
- 239000012634 fragment Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- ZNKMCMOJCDFGFT-UHFFFAOYSA-N gold titanium Chemical compound [Ti].[Au] ZNKMCMOJCDFGFT-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 229910001258 titanium gold Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置の製造方法、
特に半導体ウェーハを個々の半導体チップに分割するダ
イシング方法に関する。[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device,
In particular, the present invention relates to a dicing method for dividing a semiconductor wafer into individual semiconductor chips.
【０００２】半導体ウェーハを個々の半導体チップに分
割する方法としては、回転するダイシングソー（ブレー
ド）により切断する方式が一般的である。当初はダイシ
ングソーでウェーハの厚さの一部が残るように切断（こ
れをハーフカットと呼ぶ）した後、クラッキングにより
チップに分割していたが、クラッキング時にウェーハの
破片を生じ易いため、最近ではダイシングソーでウェー
ハの全板厚を切断（これをフルカットと呼ぶ）する方式
が主流となっている。しかしフルカットであっても、チ
ップのエッジ部分からの微小破片の発生をなくすことは
困難である。A common method for dividing a semiconductor wafer into individual semiconductor chips is to cut the semiconductor wafer into individual semiconductor chips using a rotating dicing saw (blade). Originally, the wafer was cut with a dicing saw so that part of its thickness remained (this was called a half-cut), and then cracked to divide it into chips. The mainstream method is to use a dicing saw to cut the entire thickness of the wafer (this is called a full cut). However, even with full cutting, it is difficult to eliminate the generation of microscopic debris from the edge portion of the chip.
【０００３】近年、半導体装置の高集積化や高信頼性の
要求に伴って、この微小破片に起因する障害を防止する
ことが可能な半導体装置の製造方法が望まれている。[0003] In recent years, with the demand for higher integration and higher reliability of semiconductor devices, there has been a demand for a method of manufacturing semiconductor devices that can prevent failures caused by minute fragments.
【０００４】0004
【従来の技術】従来の製造方法の一例を図２を用いて説
明する。図２ （ａ）〜（ｃ） は従来の製造方法の一
例を工程順に示す模式断面図である。尚、図中、図１と
同じものには同一の符号を付与した。2. Description of the Related Art An example of a conventional manufacturing method will be explained with reference to FIG. FIGS. 2(a) to 2(c) are schematic cross-sectional views showing an example of a conventional manufacturing method in the order of steps. In the figure, the same parts as in FIG. 1 are given the same reference numerals.
【０００５】先ず半導体ウェーハ１の裏面に粘着テープ
１５を貼付する（図２（ａ） 参照）。次にこれをダイ
シング装置（図示は省略）上に固定し、ブレード２１に
より半導体ウェーハ１の表面側からそのスクライブライ
ンに沿ってフルカット方式で格子状に切断し、複数個の
半導体チップ２を得る。この際、半導体ウェーハ１は軟
らかい粘着テープ１５を介してダイシング装置に固定さ
れることになるからブレードが振動し、その結果、半導
体チップ２の裏面側のエッジ部分（ダイシング溝３との
交線部分）が欠けて微小破片２ａを生じる（図２（ｂ）
参照）。First, an adhesive tape 15 is attached to the back surface of the semiconductor wafer 1 (see FIG. 2(a)). Next, this is fixed on a dicing device (not shown), and the blade 21 cuts the semiconductor wafer 1 from the front side along the scribe lines into a grid pattern using a full cut method to obtain a plurality of semiconductor chips 2. . At this time, since the semiconductor wafer 1 is fixed to the dicing device via the soft adhesive tape 15, the blade vibrates, and as a result, the edge portion of the back side of the semiconductor chip 2 (the intersection line with the dicing groove 3) ) is chipped, producing minute fragments 2a (Fig. 2(b)
reference).
【０００６】このようにして得た半導体チップ２は、裏
面側から突き上げピン２３で突き上げてコレット（図示
は省略）によりピックアップして、チップトレイ又はダ
イボンダに搬送する。この際、微小破片２ａが飛散して
他の半導体チップ２の表面等に付着することがある（図
２（ｃ） 参照）。The semiconductor chip 2 thus obtained is pushed up from the back surface side with a push-up pin 23, picked up by a collet (not shown), and transported to a chip tray or die bonder. At this time, the minute fragments 2a may be scattered and adhere to the surfaces of other semiconductor chips 2 (see FIG. 2(c)).
【０００７】尚、粘着テープ１５として、その粘着材が
熱硬化性樹脂又は紫外線硬化樹脂であるものを使用し、
半導体ウェーハ２を切断した後にこれを加熱又は紫外線
照射する工程を追加する場合がある。この方法によれば
、加熱又は紫外線照射によって粘着材の粘着力が弱まり
、半導体チップ２のピックアップが容易になる。[0007] As the adhesive tape 15, one whose adhesive material is a thermosetting resin or an ultraviolet curing resin is used.
After cutting the semiconductor wafer 2, a step of heating or irradiating it with ultraviolet rays may be added. According to this method, the adhesive force of the adhesive material is weakened by heating or ultraviolet irradiation, making it easier to pick up the semiconductor chip 2.
【０００８】[0008]
【発明が解決しようとする課題】半導体チップに上記の
ような微小破片が付着していると、後の工程で傷や短絡
等の障害の原因となる。特に半導体ウェーハの裏面側に
金属膜が被着されている場合に、ウェーハの微小破片と
共にその金属のバリを生じるから、このような障害が多
発していた。[Problems to be Solved by the Invention] If the above-mentioned minute fragments are attached to a semiconductor chip, they cause problems such as scratches and short circuits in subsequent steps. In particular, when a metal film is deposited on the back side of a semiconductor wafer, burrs of the metal are generated together with minute fragments of the wafer, and such failures frequently occur.
【０００９】本発明はこのような問題を解決して、ダイ
シングによって得られる半導体チップにダイシングによ
って生じる微小破片が付着することを防止して半導体装
置製造の歩留りを向上させることを目的とする。It is an object of the present invention to solve these problems and to improve the yield of semiconductor device manufacturing by preventing minute fragments generated by dicing from adhering to semiconductor chips obtained by dicing.
【００１０】0010
【課題を解決するための手段】この目的は、本発明によ
れば、半導体ウェーハ１の裏面に第一の粘着テープ１１
を貼付した後、半導体ウェーハ１の表面から第一の粘着
テープ１１まで達するダイシング溝３を形成して半導体
ウェーハ１を個々の半導体チップ２に分割する工程と、
半導体チップ２の表面に第一の粘着テープ１１より粘着
力が大である第二の粘着テープ１２を貼付した後、第一
の粘着テープ１１を半導体チップ２の裏面から剥離する
工程と、半導体チップ２の裏面側エッジ部分を除去する
工程と、半導体チップ２の裏面に第二の粘着テープ１２
より粘着力が大である第三の粘着テープ１３を貼付した
後、第二の粘着テープ１２を半導体チップ２の表面から
剥離する工程と、を有することを特徴とする半導体装置
の製造方法とすることで、達成される。[Means for Solving the Problem] According to the present invention, the first adhesive tape 11 is attached to the back side of the semiconductor wafer 1.
a step of forming dicing grooves 3 reaching from the surface of the semiconductor wafer 1 to the first adhesive tape 11 to divide the semiconductor wafer 1 into individual semiconductor chips 2;
A step of attaching a second adhesive tape 12 having a higher adhesive strength than the first adhesive tape 11 to the surface of the semiconductor chip 2, and then peeling off the first adhesive tape 11 from the back surface of the semiconductor chip 2; A step of removing the edge portion on the back side of the semiconductor chip 2, and applying a second adhesive tape 12 to the back side of the semiconductor chip 2.
A method for manufacturing a semiconductor device, comprising the steps of pasting a third adhesive tape 13 with higher adhesive strength and then peeling off the second adhesive tape 12 from the surface of the semiconductor chip 2. This will be achieved.
【００１１】[0011]
【作用】本発明の製造方法によれば、半導体チップ裏面
のエッジ部分をブレードにより削り取るから、半導体チ
ップ裏面に金属膜が被着されていても、脱落せずに残っ
ている微小破片は除去される。従って、ダイシングによ
って得られる半導体チップにダイシングによって生じる
微小破片が付着することを防止することが出来る。[Operation] According to the manufacturing method of the present invention, the edge portion of the back surface of the semiconductor chip is scraped off with a blade, so even if a metal film is adhered to the back surface of the semiconductor chip, any remaining minute fragments that do not fall off are removed. Ru. Therefore, it is possible to prevent minute fragments generated by dicing from adhering to semiconductor chips obtained by dicing.
【００１２】半導体チップ裏面のエッジ部分を加工する
ために、三枚の粘着テープを使用し、これらを半導体ウ
ェーハ（又は半導体チップ）の裏面、表面、裏面に逐次
貼付することになるが、貼り替えに際しては剥離する粘
着テープの粘着力が剥離しない粘着テープのそれより弱
くなければならない。粘着テープとして熱硬化性樹脂又
は紫外線硬化性樹脂の粘着材を用いたものも使用し、剥
離する粘着テープのみに加熱処理又は紫外線照射処理を
施すことにより、この条件が満たされる。[0012] In order to process the edge portion of the back side of the semiconductor chip, three pieces of adhesive tape are used and these are sequentially pasted to the back, front, and back sides of the semiconductor wafer (or semiconductor chip), but there is no need to replace the tape. In this case, the adhesive force of the adhesive tape that can be peeled off must be weaker than that of the adhesive tape that cannot be peeled off. This condition can be met by using an adhesive tape made of a thermosetting resin or an ultraviolet curable resin, and by subjecting only the adhesive tape to be peeled off to heat treatment or ultraviolet irradiation treatment.
【００１３】[0013]
【実施例】本発明に基づく半導体装置の製造方法の一例
を図１を参照しながら説明する。図１ （ａ）〜（ｆ）
は本発明の実施例を工程順に示す模式断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG. Figure 1 (a) to (f)
1A and 1B are schematic cross-sectional views showing an example of the present invention in the order of steps.
【００１４】先ず半導体ウェーハ１の裏面側（素子が形
成されていない側）に、粘着材が紫外線硬化性樹脂であ
る第一の粘着テープ１１を貼付する（図１（ａ） 参照
）。次にこれらをダイシング装置（図示は省略）上に固
定し、ブレード２１により半導体ウェーハ１の表面側か
らそのスクライブラインに沿ってフルカット方式で格子
状に切断し、複数個の半導体チップ２を得る。この切断
により半導体チップ２の裏面側のエッジ部分（ダイシン
グ溝３との交線部分）が欠けて微小破片２ａを生じてい
る（図１（ｂ） 参照）。First, a first adhesive tape 11 whose adhesive material is an ultraviolet curable resin is attached to the back side (the side on which no elements are formed) of the semiconductor wafer 1 (see FIG. 1(a)). Next, these are fixed on a dicing device (not shown), and the blade 21 cuts the semiconductor wafer 1 from the front side along the scribe lines in a grid pattern using a full cut method to obtain a plurality of semiconductor chips 2. . As a result of this cutting, the edge portion (intersecting line with the dicing groove 3) on the back side of the semiconductor chip 2 is chipped, resulting in minute fragments 2a (see FIG. 1(b)).
【００１５】次にこれらをダイシング装置から外し、第
一の粘着テープ１１に紫外線を照射してその粘着力を弱
める。その後半導体チップ２の表面側に、粘着材が紫外
線硬化性樹脂である第二の粘着テープ１２を貼付する（
図１（ｃ） 参照）。更に半導体チップ２の裏面側から
第一の粘着テープ１１を剥離する。Next, these are removed from the dicing device, and the first adhesive tape 11 is irradiated with ultraviolet rays to weaken its adhesive strength. After that, a second adhesive tape 12 whose adhesive material is an ultraviolet curable resin is attached to the front side of the semiconductor chip 2 (
(See Figure 1(c)). Furthermore, the first adhesive tape 11 is peeled off from the back side of the semiconductor chip 2.
【００１６】その後、半導体チップ２の裏面側を上にし
て再びダイシング装置に固定し、ブレード２１より幅広
のブレード２２により、ダイシング溝３に合わせて切り
込み、脱落せずに残っている微小破片２ａを削り取る（
図１（ｄ） 参照）。After that, the semiconductor chip 2 is again fixed to the dicing machine with the back side facing up, and cut into the dicing groove 3 using the blade 22, which is wider than the blade 21, to remove the remaining minute pieces 2a. scrape off (
(See Figure 1(d)).
【００１７】次にこれらをダイシング装置から外し、第
二の粘着テープ１２に紫外線を照射してその粘着力を弱
める。その後半導体チップ２の裏面側に、粘着材が紫外
線硬化性樹脂である第三の粘着テープ１３を貼付する（
図１（ｅ） 参照）。次に半導体チップ２の表面側から
第二の粘着テープ１２を剥離する。更に第三の粘着テー
プ１３に紫外線を照射してその粘着力を弱める。Next, these are removed from the dicing device, and the second adhesive tape 12 is irradiated with ultraviolet rays to weaken its adhesive strength. After that, a third adhesive tape 13 whose adhesive material is an ultraviolet curable resin is attached to the back side of the semiconductor chip 2 (
(See Figure 1(e)). Next, the second adhesive tape 12 is peeled off from the front side of the semiconductor chip 2. Furthermore, the third adhesive tape 13 is irradiated with ultraviolet rays to weaken its adhesive strength.
【００１８】その後、個々の半導体チップ２を、裏面側
から突き上げピン２３で突き上げてコレット（図示は省
略）によりピックアップして、チップトレイ（図示は省
略）又はダイボンダ（図示は省略）に搬送する（図１（
ｆ） 参照）。Thereafter, the individual semiconductor chips 2 are pushed up from the back side with the push-up pins 23, picked up by a collet (not shown), and transported to a chip tray (not shown) or a die bonder (not shown). Figure 1 (
f) see).
【００１９】尚、上記の製造方法において、ブレード２
１による半導体ウェーハ１切断の後、及びブレード２２
による半導体チップ２裏面エッジ部分削り取りの後に、
洗浄工程を追加することが好ましい。In the above manufacturing method, the blade 2
After cutting the semiconductor wafer 1 by 1 and the blade 22
After scraping off the back edge of the semiconductor chip 2,
It is preferable to add a washing step.
【００２０】本発明者は裏面に金属膜（チタン金等）が
被着された半導体ウェーハ１をこの方法でダイシングし
（但し、ブレード２１の幅を６０μｍ、ブレード２２の
幅を ２００μｍ、その切り込み量を３０μｍとした）
、チップトレイに搬送した結果、半導体チップ２への微
小破片２ａの付着が認められなかった。The present inventor diced a semiconductor wafer 1 having a metal film (titanium gold, etc.) adhered to the back surface using this method (however, the width of the blade 21 was 60 μm, the width of the blade 22 was 200 μm, and the cutting depth was was set to 30 μm)
As a result of transporting the semiconductor chip 2 to a chip tray, no fine particles 2a were found to be attached to the semiconductor chip 2.
【００２１】本発明は以上の実施例に限定されることな
く、更に種々変形して実施出来る。例えば、第一、第二
及び第三の粘着テープ（１１， １２， １３）の一乃
至全部を、粘着材が熱硬化性樹脂であるものに置き換え
ても、或いは紫外線硬化性も熱硬化性もないものに置き
換えても、本発明は有効である。但し後者の場合には粘
着力に差を持たせる必要がある。The present invention is not limited to the above embodiments, but can be implemented with various modifications. For example, one or all of the first, second, and third adhesive tapes (11, 12, 13) may be replaced with one in which the adhesive material is a thermosetting resin, or one in which the adhesive material is neither ultraviolet curable nor thermosetting. The present invention is still effective even if it is replaced with something that does not exist. However, in the latter case, it is necessary to provide a difference in adhesive strength.
【００２２】[0022]
【発明の効果】以上説明したように、本発明によれば、
ダイシングによって得られる半導体チップにダイシング
によって生じる微小破片が付着することを防止すること
が出来、半導体装置製造の歩留り向上と半導体装置の信
頼性向上に寄与する。[Effects of the Invention] As explained above, according to the present invention,
It is possible to prevent minute fragments generated by dicing from adhering to semiconductor chips obtained by dicing, contributing to improved yields in semiconductor device manufacturing and improved reliability of semiconductor devices.
【図１】 本発明の実施例を工程順に示す模式断面図
である。FIG. 1 is a schematic cross-sectional view showing an example of the present invention in the order of steps.
【図２】 従来の製造方法の一例を工程順に示す模式
断面図である。FIG. 2 is a schematic cross-sectional view showing an example of a conventional manufacturing method in the order of steps.
１ 半導体ウェーハ ２ 半導体チップ ２ａ 微小破片 ３ ダイシング溝 １１ 第一の粘着テープ １２ 第二の粘着テープ １３ 第三の粘着テープ １５ 粘着テープ ２１， ２２ ブレード ２３ 突き上げピン 1 Semiconductor wafer 2 Semiconductor chip 2a Microscopic fragments 3 Dicing groove 11 First adhesive tape 12 Second adhesive tape 13 Third adhesive tape 15 Adhesive tape 21, 22 blade 23 Push-up pin
Claims (3)
の粘着テープ（１１）を貼付した後、該半導体ウェーハ
（１） の表面から該第一の粘着テープ（１１）まで達
するダイシング溝（３） を形成して該半導体ウェーハ
（１） を個々の半導体チップ（２） に分割する工程
と、該半導体チップ（２） の表面に該第一の粘着テー
プ（１１）より粘着力が大である第二の粘着テープ（１
２）を貼付した後、該第一の粘着テープ（１１）を該半
導体チップ（２） の裏面から剥離する工程と、該半導
体チップ（２） の裏面側エッジ部分を除去する工程と
、該半導体チップ（２） の裏面に該第二の粘着テープ
（１２）より粘着力が大である第三の粘着テープ（１３
）を貼付した後、該第二の粘着テープ（１２）を該半導
体チップ（２） の表面から剥離する工程と、を有する
ことを特徴とする半導体装置の製造方法。1. After pasting a first adhesive tape (11) on the back side of a semiconductor wafer (1), a dicing groove (3) is formed that reaches from the front surface of the semiconductor wafer (1) to the first adhesive tape (11). ) to divide the semiconductor wafer (1) into individual semiconductor chips (2), and applying adhesive tape (11) to the surface of the semiconductor chips (2) with greater adhesive strength than the first adhesive tape (11). Second adhesive tape (1
2), a step of peeling off the first adhesive tape (11) from the back side of the semiconductor chip (2), a step of removing the back side edge portion of the semiconductor chip (2), and a step of removing the first adhesive tape (11) from the back side of the semiconductor chip (2); A third adhesive tape (13) having higher adhesive strength than the second adhesive tape (12) is placed on the back side of the chip (2).
), and then peeling off the second adhesive tape (12) from the surface of the semiconductor chip (2).
， １２）の内の少なくとも一方は粘着材が熱硬化性樹
脂であり、該粘着材が熱硬化性樹脂である粘着テープの
剥離工程に先立って該粘着テープを加熱して粘着力を低
下させることを特徴とする請求項１記載の半導体装置の
製造方法。Claim 2: The first and second adhesive tapes (11
, 12), the adhesive material is a thermosetting resin, and the adhesive tape is heated to reduce the adhesive force prior to the peeling process of the adhesive tape where the adhesive material is a thermosetting resin. The method for manufacturing a semiconductor device according to claim 1, characterized in that:
， １２）の内の少なくとも一方は粘着材が紫外線硬化
性樹脂であり、該粘着材が紫外線硬化性樹脂である粘着
テープの剥離工程に先立って該粘着テープに紫外線を照
射して粘着力を低下させることを特徴とする請求項１記
載の半導体装置の製造方法。Claim 3: The first and second adhesive tapes (11
, 12), the adhesive material is an ultraviolet curable resin, and the adhesive tape is irradiated with ultraviolet rays to reduce the adhesive force prior to the peeling process of the adhesive tape where the adhesive material is an ultraviolet curable resin. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP883291A JP2890851B2 (en) | 1991-01-29 | 1991-01-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP883291A JP2890851B2 (en) | 1991-01-29 | 1991-01-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04253359A true JPH04253359A (en) | 1992-09-09 |
| JP2890851B2 JP2890851B2 (en) | 1999-05-17 |
Family
ID=11703762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP883291A Expired - Lifetime JP2890851B2 (en) | 1991-01-29 | 1991-01-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2890851B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462274B1 (en) | 1998-10-31 | 2002-10-08 | Amkor Technology, Inc. | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
| US6731012B1 (en) | 1999-12-23 | 2004-05-04 | International Business Machines Corporation | Non-planar surface for semiconductor chips |
-
1991
- 1991-01-29 JP JP883291A patent/JP2890851B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462274B1 (en) | 1998-10-31 | 2002-10-08 | Amkor Technology, Inc. | Chip-scale semiconductor package of the fan-out type and method of manufacturing such packages |
| US6731012B1 (en) | 1999-12-23 | 2004-05-04 | International Business Machines Corporation | Non-planar surface for semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2890851B2 (en) | 1999-05-17 |
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