JPH04247654A - Input/output protection circuit - Google Patents

Abstract

PURPOSE:To ensure quick response for rise of resistance value of a pinch resistor and certainly protect input/output of the circuit to be protected from a surge input by forming the pinch resistor with a second conductivity type semiconductor region sandwiched by a pair of first conductivity type semiconductor regions. CONSTITUTION:An N type substrate 1 is connected with a power supply 13 through an N<+> substrate contact region 2 formed on the main surface of the substrate and a P type well 3 is formed on the main surface of the N type substrate 1. Moreover, P<+> well contact regions 4, 5 are formed in both sides of the surface of P type well 3, a high concentration N<+> region 6 is formed in the intermediate area of both P<+> well contact regions 4, 5, the N<+> region 6 is connected to the power supply 13 and the pinch resistor 10 is formed by the P type well 3 sandwiched by thus N<+> region 6 and N type substrate 1.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is applicable to, for example, CMOSIC.
The present invention relates to input/output protection circuits such as those described above, and particularly relates to input/output protection circuits having high-speed signal response and excellent protection characteristics against surges.

0002

2. Description of the Related Art A first conventional example of an input/output protection circuit is shown in FIG. This conventional example shows an input/output protection circuit in an N-type substrate, P-type well type CMOS. In FIG. 6, 31 and 32 are input terminals and output terminals of an input/output protection circuit, and the output terminal 32 is connected to an input gate terminal in a CMOS (not shown). A P-type well is formed on the surface of the N-type substrate connected to the power supply 30, and this P-type well is grounded. 33 is a pull-up diode composed of an N-type substrate and a high concentration P-type region formed on the surface of this N-type substrate; 34;
is a pull-down diode composed of a P-type well and a highly doped N-type region formed on the surface of the P-type well. Reference numeral 35 denotes a resistor, which is formed of a thin film resistor in order to increase the resistance value and ensure voltage clamping of both diodes 33 and 34 against electrostatic surges and the like.

[0003] During normal operation, the input terminal 31
The signal input from the CMOS is transmitted to the CMOS via the resistor 35. At this time, both the pull-up diode 33 and the pull-down diode 34 are reverse biased and are in a non-conductive state. Further, when a positive surge enters from the input terminal 31, the voltage is dropped by the resistor 35, and then the surge current is bypassed to the power supply 30 through the pull-up diode 33. Conversely, when a negative surge enters from the input terminal 31, the surge commutation flows from the ground through the pull-down diode 34 and the resistor 35 to the input terminal 31, and the CM
Destruction of the OS input gate is prevented. At this time as well, the voltage of the surge is reduced by the resistor 35.

However, in such conventional input protection circuits, the resistor 35 has a large resistance value, which causes a delay in the input signal during normal operation, impairing high-speed operation. There was a problem. In addition, when protecting the output side, that is, protecting the gate and drain junctions of the CMOS output MOSFET, it is necessary to reduce the voltage drop at the output driver, so a large value resistor cannot be inserted, and the output protection becomes impossible. There was a problem of having enough.

On the other hand, there is a second conventional example in which a pinch resistor as shown in FIGS. 7 and 8 is inserted in series with the input terminal (Japanese Unexamined Patent Publication No. 60-91661). Figures 7 and 8
, 36 is an N-type substrate, 37 is a P-type element isolation layer, 3
8 is a P-type diffusion layer, 39 and 40 are P+ contact diffusion layers, and the P-type diffusion layer 38 having a PN junction formed with the N-type substrate 36 on the lower surface constitutes a pinch resistance. During normal operation, the value of the pinch resistance is small and high-speed signal transfer is possible. In addition, if a negative surge whose absolute value is larger than the power supply voltage enters from the input terminal 31, the PN junction on the bottom surface is reverse biased, a depletion layer extends in the P-type diffusion layer 38, and the value of the pinch resistance becomes large. This increases resistance to surge input.

[0006]

[Problem to be Solved by the Invention] In a conventional input/output protection circuit using a pinch resistor, when a negative surge whose absolute value is larger than the power supply voltage occurs, a depletion layer extends from only one side of the P-type diffusion layer. As a result, the responsiveness of resistance change to surge input is insufficient, and it is difficult to reliably protect the input/output of CMOS and the like from surge input.

[0007] The present invention was made by focusing on such conventional problems, and the response of the resistance value increase of the pinch resistor to the surge input is fast, and the input/output of the protected circuit is reliably controlled from the surge input. The purpose of the present invention is to provide an input/output protection circuit that can provide protection.

[0008]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides an input/output protection circuit having a pinch resistor connected in series to at least either the input terminal or the output terminal of a protected circuit. , the pinch resistor is formed by a second conductivity type semiconductor region sandwiched between two first conductivity type semiconductor regions.

[0009]

[Operation] The pinch resistor is constituted by a second conductivity type semiconductor region in which a PN junction is formed on both opposing sides of the first conductivity type semiconductor region.

During normal operation, the resistance value of the pinch resistor is sufficiently small, and high-speed response is possible with almost no signal delay.

When a surge with a polarity that forward biases the PN junction enters from the input section or the output section, the surge current flows forward through the PN junction and is pulled up or down, and the input and output terminals of the protected circuit are Input/output protection is achieved by keeping the voltage rise low.

Contrary to the above, if a polarity surge that reverse biases the PN junction comes from the input section or output section, the second
A depletion layer spreads from both sides within the conductive semiconductor region. As a result, the resistance value of the pinch resistor increases instantaneously, and the surge drops significantly at the pinch resistor, causing the surge to enter the protected circuit.
The voltage rise at the output terminal is suppressed to a low level, and input/output is protected.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIGS. 1 and 2 are diagrams showing a first embodiment of the present invention.

First, to explain the configuration of the input/output protection circuit, in FIG. 1, 1 is an N-type board;
It is connected to a power source 13 via an N+ substrate contact region 2 formed on its main surface. On the main surface of the N-type substrate 1,
A P-type well 3 is formed. P+ well contact regions 4 and 5 are formed on both sides of the surface of the P type well 3, and a heavily doped N+ region 6 is formed in the middle of both the P+ well contact regions 4 and 5. N+ area 6 is power supply 1
A pinch resistor 10 is formed by the P-type well 3 sandwiched between the N+ region 6 and the N-type substrate 1. 7 is a field oxide film, and 8 is an interlayer insulating film.

As shown in the equivalent circuit of FIG.
and the N-type substrate 1, respectively, with a pull-up diode 1
4 and 15 are configured. Both pull-up diodes 1
The cathodes 4 and 15 are connected to the power supply 13. The P+ well contact region 4, that is, the anode of the pull-up diode 14 is connected to the input terminal 11, and the other P+
Well contact region 5, i.e. pull-up diode 1
The anode of 5 is connected to the output terminal 12. The output terminal 12 is connected to an input gate terminal of a CMOS (not shown) formed in another part of the N-type substrate 1. 16 is a pull-up diode formed by a PN junction between the P-type well 3 and the N+ region 6, and 17 is a pull-up diode formed by a PN junction between the P-type well 3 and the N-type substrate 1. .

Next, the operation of the input/output protection circuit configured as described above will be explained.

During normal operation, the resistance value of the pinch resistor 10 is sufficiently small, and a high-speed signal response is possible with almost no signal delay.

When a positive surge enters the power supply 13 from the input terminal 11, the surge current flows through the pull-up diode 14, approximately half of the pinch resistor 10, the pull-up diodes 16, 17, and the entire pinch resistor 10. They are bypassed to the power supply 13 through pull-up diodes 15, respectively. That is, each pull-up diode 14, 15, 16
, 17 flows in the forward direction, suppressing the rise in gate voltage of the CMOS, and ensuring reliable input protection.

Conversely, if a negative surge enters the power supply 13 from the input terminal 11, the P-type well 3 and the N+ region 6
Both the PN junction between the P-type well 3 and the N-type substrate 1 are reverse biased. As a result, the depletion layer 18 spreads inside the P-type well 3 from both the upper and lower surfaces, and the value of the pinch resistor 10 increases instantly, suppressing the rise in CMOS gate voltage and ensuring reliable input protection.

As described above, in the input protection circuit of this embodiment, when a negative surge is input to the power supply, the value of the pinch resistor 10 increases in a short time depending on the magnitude of the voltage.
It has characteristics that are significantly superior to conventional examples in that it reliably protects protected circuits such as CMOS, the value of the pinch resistance is small during normal signal input, and high-speed signal response is excellent. ing.

Next, FIGS. 3 and 4 show a second embodiment of the present invention.

In this embodiment, a low concentration N-type well 21 is formed within the P-type well 3. P-type well 3 is P
+ grounded via the well contact region 4. N
N+ well contact regions 22 and 23 are formed on both sides of the surface of the shaped well 21, and a heavily doped P+ region 24 is formed in the middle of both the N+ well contact regions 22 and 23. P+ region 24 is grounded, and this P+ region 2
A pinch resistor 20 is formed by an N-type well 21 sandwiched between the P-type well 3 and the P-type well 3 .

As shown in the equivalent circuit of FIG. 4, a P-type well 3, an N-type well 21 and an N+ well contact region 22
and between P-type well 3 and N-type well 21 and N+
Pull-down diodes 25 and 26 are formed between the well contact 23 and the well contact 23, respectively. The anodes of both pull-down diodes 25 and 26 are grounded. N+ well contact region 22, i.e. pull-down diode 2
5 is connected to the input terminal 11 and connected to the other N+ well contact region 23, i.e. the pull-down diode 26
The cathode of is connected to the output terminal 12. 27 is P
A pull-down diode 28 is formed by a PN junction between the type well 3 and the N-type well 21, and a pull-down diode 28 is formed by a PN junction between the P+ region 24 and the N-type well 21.

Next, the operation of the input/output protection circuit configured as described above will be explained.

During normal operation, as in the first embodiment, the resistance value of the pinch resistor 20 is sufficiently small to enable high-speed signal response.

When a positive surge from the input terminal 11 with respect to ground occurs, the PN junction between the P+ region 24 and the N-type well 21 and the PN junction between the P-type well 3 and the N-type well 21 are are both reverse biased. As a result, a depletion layer spreads in the N-type well 21 from both the upper and lower sides, and the value of the pinch resistor 20 increases instantly, suppressing the rise in CMOS gate voltage and ensuring reliable input protection.

Conversely, when a negative surge enters from the input terminal 11 with respect to the ground, the surge current flows from the ground to the pull-down diode 25, approximately half of the pinch resistor 20, the pull-down diodes 27 and 28, and the pinch resistor 20. and the pull-down diode 26 to the input terminal 11. That is, each pull-down diode 25, 2
A surge current flows in the forward direction of 6, 27, and 28, and the CMOS
gate voltage rise is suppressed, ensuring reliable input protection.

FIG. 5 shows a third embodiment of the invention.

The input/output protection circuit of this embodiment has the first
This corresponds to a combination circuit of the embodiment and the second embodiment. Therefore, in this embodiment, each pull-up diode is 14, 15, 16, 17 or the respective pull-down diodes 25, 26, 27, 28 as well as the instantaneous resistance value increasing action of the pinch resistor 10 or 20, thereby providing more reliable input protection for CMOS and the like.

In each of the above embodiments, a case has been described in which an input/output protection circuit is connected in front of the input gate terminal of the CMOS, which is the circuit to be protected, to protect the input gate of the CMOS from surges. The input terminal 11 of the input/output protection circuit in FIG. 4 is connected to a CMOS output N-channel MOS.
It is also possible to protect the gate and drain junction of the output MOSFET against positive and negative surges that enter from the output terminal 12 by connecting it to the drain terminal of the FET. and,
In the case of this kind of output protection, it is necessary to reduce the voltage drop at the output driver, so a large value resistor cannot be inserted.In this respect, the input/output protection circuit of this example has the following points:
Since the resistance value of the pinch resistor is sufficiently small during normal operation, it has the advantage of being able to fully meet this requirement and of ensuring output protection.

Furthermore, in each of the above embodiments, the N type substrate, the P
Although we have described cases of type well type, N-type substrate, P-type well, and N-type well type, it can also be applied to P-type substrate, N-type well type, or P-type substrate, N-type well, and P-type well type. Can be applied.

Further, in each of the above-described embodiments, the structure of the surface of the substrate with a low concentration was described, but the present invention can also be applied to a so-called epitaxial substrate structure in which the substrate is highly doped and the element region is lightly doped.

Furthermore, when a CMOS is applied as the circuit to be protected, even if a surge is input, the voltage rise at the input/output section of the CMOS is suppressed to a low level, so that no problem with latch-up occurs.

[0035]

As explained above, according to the present invention, since the pinch resistor is formed by the second conductivity type semiconductor region sandwiched between the two first conductivity type semiconductor regions, during normal operation, the pinch resistor The resistance value of is sufficiently small to enable high-speed response with almost no signal delay. If a surge with a polarity that forward biases the PN junction formed on both sides of the second conductivity type semiconductor region enters from the input section or the output section, the surge current flows forward through the PN junction, so the input of the protected circuit The voltage rise at the terminal or output terminal can be suppressed to a low level, and the input and output of the circuit to be protected can be reliably protected. Furthermore, if a polarity surge that reverse biases the PN junction enters from the input section or the output section, a depletion layer will spread from both sides within the second conductivity type semiconductor region.
The resistance value of the pinch resistor increases instantly and the voltage rise at the input terminal or output terminal of the protected circuit can be suppressed to a low level.
The input and output of the protected circuit can be reliably protected.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing a first embodiment of an input/output protection circuit according to the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit of FIG. 1;

FIG. 3 is a longitudinal sectional view showing a second embodiment of the invention.

FIG. 4 is a circuit diagram showing an equivalent circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a third embodiment of the invention.

FIG. 6 is a circuit diagram showing a conventional input/output protection circuit.

FIG. 7 is a plan view showing another conventional example.

8 is a cross-sectional view taken along line AA in FIG. 7. FIG.

[Explanation of symbols]

1 N-type substrate 3 P-type well (region that serves as a pinch resistance in the first embodiment) 6 N+ region 18 Depletion layer 21 N-type well (region that serves as a pinch resistance in the second embodiment) 24 P+ region

Claims (1)

[Claims] 1. An input/output protection circuit having a pinch resistor connected in series to at least one of an input terminal and an output terminal of a circuit to be protected, wherein the pinch resistor includes two first conductivity type semiconductor regions. An input/output protection circuit characterized in that it is formed by a second conductivity type semiconductor region sandwiched between.