JPH04247506A - Transiten power inhibitor - Google Patents

Abstract

PURPOSE: To suppress the transient power of a computer system by electrically controlling the ramp-up and ramp-down voltage and current of a power line in a system bus for connecting a power source to a peripheral device. CONSTITUTION: A bus insulating switch 80 is connected between a system bus 10 and a peripheral device so that the peripheral device is surely driven at the time of inserting/detaching the peripheral device into/from the system bus 10. A transient switch is connected between the power line of the bus 10 and a peripheral interface 24 to minimize the current load transition of the power line in the bus 10. The transient switch is connected to an ON/OFF timing generating circuit 90 for generating plural reference signals to automatically execute power up and power down when the peripheral device is inserted or ejected into/from the computer system. When the power up of a driving circuit is executed without integrating the peripheral device, an audible alarm signal is generated.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates to an apparatus for suppressing transient power on a system bus, and more particularly, to an apparatus for suppressing transient power on power lines and signal lines of an input and output (I/O) bus. .

0002

BACKGROUND OF THE INVENTION When a computer system to which multiple peripheral devices are connected goes through power-up and power-down transitions, system level signals such as VCC or VPP are valid. is not guaranteed. In the present invention, the moment when a user starts up a computer system is referred to as a power-up transition.
On the other hand, the moment when a user turns off a computer system is called a power-down transition. Traditionally, power-up and power-down sequences allow users to
The stability and validity of system level signals such as CC or VPP were obtained. Power-up and power-down sequences are defined as "turning off all peripheral devices before turning off the system, or turning on the computer system before turning on any peripherals connected to the computer system." This step is recommended by the computer system manufacturer.

If such power up and power down sequences are not followed, the computer system may be subject to erroneous system level signals or power transients. Power transients are variations in voltage and current from steady state during switching operations, such as power up or power down sequences. Such power transients can physically damage peripheral devices and often render their data unreliable. In a computer system that connects multiple peripherals through a system bus, transient power can cause any peripherals to Most likely to occur on a system bus when devices are inserted into or removed from the same system bus.

[0004] A system including a microprocessor and
A computer system with multiple peripherals connected to a bus requires that (1) the central processing unit (CPU) powers up and down when peripherals are inserted or removed from the computer system; (2) when a peripheral device connected to the system bus goes through a power-up and power-down sequence; (3) when a peripheral device is inserted into a power socket. Cheap.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a computer・It is to suppress the transient power of the system. Another object of the invention is that by regulating the voltage supplied to peripheral devices,
The goal is to minimize current transients on the system bus power lines. Another object of the present invention is to generate a reference signal for power up and power down sequences when peripheral devices are inserted into and removed from a computer system. Another object of the invention is to alert the user when a drive socket for a peripheral device is powered up even though the peripheral device is not installed.

[0006]

SUMMARY OF THE INVENTION The present invention provides a hardware solution to the transient power problem in computer systems having a small computer system interface (SCSI). SCSI is a parallel multi-master I/O bus that provides a standard interface between computers and peripheral devices. It is a disk,
Tape drive, CD ROM, optical disk, (W
ORM, M. O. ) drives, communication devices, and even bar code readers to any type of computer. In addition, November 1984
Published by American National Standards Institute, New York, New York, Val. E. Lohmeyer, Jay.
B. “Small Computer System Interface (SCSI), X3P9.2/82-2, Rev. 14B
” and Glass, L.B., “SCSI Bus” in Byte Magazine, February-March 1990. Computer systems with SCSI buses easily perform complex parallel I/O operations. You can, but
It is very sensitive to power transients. For example, if a removable disk drive is connected to a SCSI bus while a CPU connected to the bus is performing a read/write operation,
power transients generated by inserting a removable disk drive may cause the system bus to become corrupted or cause erroneous reads/
Write operations often result in significant data corruption. The present invention provides reliable operation when peripheral devices are inserted into and removed from the system bus.
A bus isolation switch is connected between the system bus and peripheral devices. A transient switch is provided between the system bus power line and the peripheral interface to ramp the voltage applied to the peripheral to a final value of approximately 5-10 milliseconds rather than sub-microsecond transients. this is,
Minimize current load transients on the system bus power lines. A transient switch is also an on/off switch that generates multiple reference signals to automatically power up and power down the system when a peripheral device is inserted into or removed from the computer system. Connected to off timing circuit.

Finally, an interlock is provided which generates an audible warning signal to the user if the drive circuit is powered up without any peripherals installed therein.
An alarm circuit is connected to this on/off timing circuit. This alerts the user to a potential data damage situation.

[0008] The present invention provides a compact computer system.
This invention provides a hardware solution to the problem of transient power in computer systems having an interface (SCSI) bus. SCSI is a parallel multi-master interface that provides a standard interface between computers and peripheral devices.
/O bus. A computer with a SCSI bus
Although the system can easily perform complex parallel I/O operations, it is very sensitive to power transients. For example, if you insert a removable disk drive into a SCSI bus while a CPU connected to the bus is performing a read/write operation, the transient power generated by inserting the removable disk drive will cause Frequently, the system bus crashes or performs erroneous read/write operations, resulting in significant data corruption. The present invention includes a bus isolation switch connected between the system bus and the peripheral device to ensure operation when the peripheral device is inserted into or removed from the system bus. A transient switch is provided between the system bus power line and the peripheral interface to ramp the voltage applied to the peripheral to a final value of approximately 5-10 milliseconds rather than sub-microsecond transients. There is. This minimizes transient current loads on the system bus power lines. A transient switch is an on/off switch that generates multiple reference signals that automatically power up and power down the system when peripheral devices are inserted into or removed from the computer system. Connected to timing circuit. Finally, an interlock alarm circuit provides an audible warning signal to the user if the drive circuit is powered up without any peripherals installed on it.
Connected to off timing circuit. This alerts the user to a potential data loss situation.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention discloses a circuit for suppressing power transients in a computer system during power up and power down transitions when peripheral devices are inserted into or removed from the computer system. In the following description, various details, such as specific circuit elements, are provided to aid in understanding the present invention.
For well-known devices such as resistors and transistors,
A detailed description is omitted so as not to obscure the invention. It will be apparent to those skilled in the art that a computer system refers to at least one CPU connected to a system bus and having a plurality of peripheral devices connected to the system bus.

FIG. 1 shows a general purpose computer system having a system bus 10. As shown in FIG. As shown,
Bus 10 includes a power line 12 and a plurality of signal lines 14 . Power line 12 connects to a power source 16 that provides power to devices connected to bus 10. Signal lines 14 include signal lines such as those found on most system buses, such as address lines, control lines, and data lines. The bus 10 includes a plurality of central processing units (
CPU) 18 to N. CPU 18 is connected to the bus via a system bus interface 22 that receives power from power line 12 and sends control signals to peripheral devices attached to bus 10. As shown in FIG. 1, a plurality of peripheral devices 20-N receive data address commands and control signals from the CPU 18, and
It is connected to bus 10 via a peripheral interface 24 which optionally receives power from 6. It will be apparent to those skilled in the art that the peripheral device 20 may have a power source independent of the power source 16 as shown in FIG. In embodiments of the invention, peripheral devices 20-N and system bus 10 share the same power supply 16.

When a computer system such as that described in FIG. 1 goes through power up and power down transitions, system level signals such as VCC or VPP are not necessarily valid. Traditionally, users have obtained stability and validity of system level signals such as VCC or VPP through power up and power down sequences. Power-up and power-down sequences are steps recommended by the computer system manufacturer to minimize transient power shocks so as not to affect the data on the data bus as well as the integrity of the computer system. It is. If such power up and power down sequences are not followed, the computer system will experience erroneous system level signals and/or power transients. Transient power is the variation in voltage and current from steady state during switching operations, such as power up or power down sequences. Such power transients can physically damage peripheral devices and often render their data unreliable. In a computer system that connects multiple peripherals through a system bus, transient power can cause any peripherals to Most likely to occur on a system bus when devices are inserted into or removed from the same system bus.

In an embodiment of the invention, CPU 18 and peripheral devices 20-N are connected to a small computer system interface (SCSI) bus. SCSI
is a parallel multi-master I/O bus that provides a standard interface between computers and peripheral devices. In addition,
Published by American National Standards Institute, New York, New York, November 5, 1984, Val d'Abrew. E. Lohmeyer, Jay. B. "Small Computer System Interface (SCSI), X3P9.2/82-
2, Revised 14B” and Glass, L. in Byte Magazine, February-March 1990. B. Please refer to "SCSI bus". Although computer systems with SCSI buses can easily perform complex parallel I/O operations, they are very sensitive to power transients. For example, if you insert a removable disk drive into a SCSI bus while a CPU connected to the bus is performing a read/write operation, the transient power generated by inserting the removable disk drive will cause Often the system bus crashes or performs erroneous read/write operations that alter the data being read or written to disk. It will be apparent to those skilled in the art that the present invention is not limited to SCSI system buses. Also,
The apparatus and method disclosed in the present invention may also be modified and modified with respect to computer systems having a system bus including at least one power line and multiple signal lines.

FIG. 2 is a circuit diagram of a power lamp circuit using an embodiment of the present invention. Power ramp circuit 30 limits the input current at the peripheral voltage input to eliminate power supply transients caused by step changes in load. Step changes in load are most noticeable when peripheral devices, such as removable disk drives, are inserted into or removed from the power supply of an expandable computer system, such as a multi-drive external expansion unit. appear. The power supply responds to such a step change in load by attempting to return to providing a normal output supply voltage. During that time, the voltage output experiences power supply transients. Power supply transients cause the power supply to respond outside of its normal output range. If other peripheral devices were connected to the same power source and operating at the same time to transfer data, system data integrity would be compromised. In an embodiment of the invention, 386i
You are inserting a removable disk drive into your computer system's external multi-drive external expansion unit. Current and voltage transients were measured for the +5 and +12 volt outputs, and the transient current into the +5 volt terminal reached a peak of about 13 amps, while the transient voltage dropped to about 2.5 volts. Similarly, the current transient into the +12 volt terminal reached a peak of about 25 amps, and the transient voltage dropped to about 8 volts. Transient currents and voltages should be maintained for 25 to 3 hours until the power supply returns to normal rate of regulation.
Lasts 0 microseconds.

When the power supply drives a peripheral device, power ramp circuit 30 has an input connected to the system bus power line via VCC terminal 32 and VDD terminal 34. Power lamp circuit 30 has outputs connected to peripheral device power line interfaces at +5 volt drive terminal 38, +5 volt solenoid terminal 42, and +12 volt drive terminal 40. The power lamp circuit 30 includes two NPN transistors 50 and 6.
0 and PNP transistors 44, 46, 48, 68, 70
have. Transistor 60 and transistor 58 form a Miller integrator, while transistor 50 and transistor 48 form another Miller integrator. Capacitors 56 and 62 operate as integrating capacitors, and resistors 64 and 76 form an integrating resistor. Upon receiving a PSEN (power supply enable) signal 98 from an on/off timing circuit 90 (described below) and latched by transistor 70, a DC step is detected by transistor 50.
, 60 and output drive transistor 44.
, 46, 48, 68, 58. In this specification, the part surrounded by <<> means an inverted signal, that is, what is represented by an upper bar in conventional literature. The timing ramp is done approximately with respect to time RC. Eventually, drive transistors 50, 60 become saturated and transistors 44, 46, 48, 58, 68 are turned on until the <<PSEN>> signal turns off and the output signal ramps down. The driving condition is set by the maximum current flowing through the series of transistors. This current flows through the resistor 52
, 54, 74, 79. The estimated minimum beta gain for saturation is PNP transistor 44,
It is estimated to be 20 for 46, 48, 68, and 70. The actual gain of the output transistor stage is relatively close to unity. The ramp produced at each base produces a similar ramp at the output. The actual timing in circuit 30 is not very important since the ramp is very slow compared to the power supply fluctuation rate and bandwidth. In embodiments of the invention, PNP power transistors 44, 46, 48, 68
, 70 is TIP36. Preferably, NPN power transistor 60 is a TIP 120. Finally, in an embodiment of the invention, NPN transistor 50 is 2N2
222 transistor.

FIG. 3 is a circuit diagram of a system bus isolation switch used in an embodiment of the invention. Bus isolation switch 80 connects to each of the plurality of signal lines connecting system bus 10 and peripheral interface 24. Bus isolation switch 80 is further connected to an on/off timing circuit 90 as shown in detail in FIG. Bus isolation switch 80 prevents random system failures while a peripheral device is removed from or inserted into the system device while other peripheral devices connected to the system bus are performing read/write operations simultaneously. . Bus isolation switch 80 consists of a plurality of switches 82, 84, and 86.

FIG. 4 is a partial diagram of a bus isolation switch 80 used for only one signal channel. Gate drive 82 is connected in parallel between all gates of the remaining channels. Gate drive 82 is preferably a VQ1001J type high speed FET transistor. One of the inputs of gate drive 82 is connected to a signal line of system bus 10. gate drive 8
The other inputs of 2 are connected to transistors 84 and 86. Transistor 84 is connected to the -5 volt power line of the system bus. On the other hand, transistor 86 is set on/off as detailed in FIG.
Connected to off timing circuit. In an embodiment of the invention, transistor 84 is a general-purpose NPN transistor 2
It is N2222A. Further, the transistor 86 has two
Preferably it is a general purpose PNP transistor of the N2907A type. Transistor 86 is connected to on/off timing circuit 90
Receives a <<SCSI_EN>> (SCSI enable) signal (described later) from. The output of gate drive 82 is connected to a corresponding signal line of peripheral interface 24. In the embodiment of the invention, the SCSI bus is 18
It has several signal lines. Therefore, 18 gate drives 82 are required to isolate voltage transients from the SCSI bus caused by removing or inserting a peripheral device onto the bus.

Bus isolation switch 80 ensures that the insertion/removal of a peripheral device on a SCSI bus does not assert a logic TRUE (low) signal on the same bus. The input characteristics of a powered down bus driver are similar to a forward biased Schottky diode. The bias voltage for such devices is nominally 0.2 to 1
．． It is 1 volt. A SCSI TRUE state is 0.
Logic low at 0-0.8 volts DC. SCSI F
The ALSE state is a logic high between 2.0 and 5.25 volts DC. When a powered down peripheral connects to a SCSI bus, the TRUE signal is assumed to be asserted on that bus. A false TRUE state asserted on the SCSI bus causes the SCSI initiator (not shown, typically located with the bus controller) to interpret either a valid or non-valid state on the bus. Since false TRUE insertions are unknown, SCSI initiators tend to ignore SCSI data or, in some cases, intermittently cause system failures or "hangs." Thus, when the peripheral device is in a powered down state, the bus isolation switch 80 operates to prevent random system failures on insertion/removal of the peripheral device. In FIG. 4, gate resistors 25, 27 are provided to drive or interrupt the on/off current, giving the bus isolation switch turn-on and turn-off times on the order of 100 milliseconds. Also, when the switch is turned on or off, the system bus isolation switch effectively suppresses any disturbance to the system bus, in this case the SCSI bus.

FIG. 5 illustrates an on/off timing circuit using an embodiment of the present invention. The input of the on/off timing circuit 90 is +1 of the system bus 10.
Connected to a 2 volt DC power line. On/Off
The timing circuit 90 has four outputs, a switch enable SW-EN96, and a power enable (PSEN)9.
8, generates <<RESET>> 100 and SCSI enable <<SCSI_EN>> 102. An on/off timing circuit 90 connects to a bus isolation switch 80, as shown in FIG. 4, to automatically bring newly asserted peripherals onto the system bus into a known state. Further, on/off timing circuit 90 includes toggle switch 92, transistors 106, 110, 114, inverters 104, 108, 112, 118, gate 116
and diodes 105 and 111. Switch enable SW_EN96 is a master enable/disable line that indicates whether a peripheral device's connection to the system bus is on or off. When toggle switch 92 is turned on, system bus 12
The volt power line connects to on/off timing circuit 90 through resistor 101 to ground level, immediately changing the logic state of inverter 104 from low to high and enabling SW_EN. 《PSEN》
Signal 98 allows the power on/off circuit to change state in a controlled manner. This signal line connects to the lamp circuit as shown in FIG. 2 and is generated only when SW_EN is turned on at the gate of transistor 106. When SW_EN is turned off, 《PSEN》 is 1.
It is deasserted after a delay of 0.00 msec, allowing a ramp down to occur. 《RESET》signal 10
0 is used to reset the peripheral to a known state before a connection is made. Initially, this signal is assumed to be in the reset state and forces the peripheral into the reset state until a stable state is reached after 100 milliseconds. In normal I/O operation, the <RESET> signal 100 is
Controlled by the <<RESET>> signal line of the system bus. Finally, the <<SCSI_EN>> signal 102 is initially high. This gives the peripheral device time to stabilize without having to connect to the system bus 10. This creates a false system error when peripherals power up.
Prevent bus state from being asserted. therefore,"
SCSI_EN> signal 102 is the <RESET> signal 1
Occurs after a predetermined amount of delay associated with the assertion of 00. In this manner, the system bus 10 power line is connected to the resistor 10 inverter 112 and the inverter pair 118.
When asserted via the ``SCSI_EN'' signal, the <<SCSI_EN>> signal is reliably asserted after assertion of the <<RESET>> signal 100.

FIG. 6 is a timing diagram of the assertion/deassertion of the four timing signals generated by the on/off timing circuit shown in FIG. In an embodiment of the invention, the peripheral device that is connected to or removed from the system bus is a removable disk drive. Using this as an example, when a drive is inserted into the system bus, the SW_EN signal 96 is initially off. User can turn on/off
Turning on the timing circuit toggle switch 92 creates a step load. At the same time, 《PSEN signal》
98 is asserted to ensure that power is being provided to the removable disk drive. 1
After 00 milliseconds, the power-on circuit is in a stable state and 《R
The <<ESET>> signal 100 is deasserted after another millisecond propagation delay and the <<SCSI_EN>> signal 102 goes from high to low, enabling the signal switch. Through this series of processes, the drive is known (RESET).
state and the drive is electrically connected to the SCSI bus.

In FIG. 6, on/off timing circuit 90 goes through the reverse process when a peripheral device is removed from the system bus. At the beginning of removal, it is assumed that no transactions are occurring between the peripheral and other devices on the system bus. Additionally, the SW_EN signal 96 is high, meaning the system is enabled. Next, <<PSEN>> signal 9
8 is low, meaning that power is not yet being applied to the peripheral terminals. Meanwhile, the <RESET> signal 100 is high, indicating that the peripheral is in a non-reset state and turns off the on/off timing circuit. Finally, the <<SCSI_EN>> signal 102 is low, indicating that the bus isolation switch is closed. At some point thereafter, the user toggles the SW_EN signal 96 from a high state to a low state. This indicates to the computer system that a request has been made to disconnect the peripheral. The subsequent sequence is as follows. The RESET signal 100 immediately goes from high to low and the peripheral immediately tri-states all of its drivers and goes into reset. After a short predetermined delay: The <<SCSI_EN>> signal 102 goes from a low state to a high state, and settling of the <<RESET>> and <<PSEN>> signals can occur. At this point, the peripheral's power control circuitry powers down the peripheral by ramping it to a power off state. Finally, the user can safely disconnect this peripheral from the system.

FIG. 7 is a circuit diagram of an interlock alarm switch used in an embodiment of the invention. The bus isolation switch 80 shown in FIG.
When W_EN signal 96 is active, the system
It may be overridden by connecting or disconnecting a peripheral device to or from the bus. To prevent this, interlock alarm circuit 120 operates when drive power is enabled and an attempt is made to insert a previously removed drive. In FIG. 7, the interlock alarm circuit includes transistor 122
, buzzer/alarm device 124, gate drive 12
6. It consists of two diodes 125 and 127. The interlock/alarm circuit 120 is
N》Driven by signal 102. transistor 122
is turned on, the system bus 10 power line is
If gate drive 126 is activated, an alarm is activated. The only condition for activating gate drive 126 is the SCSI ground connection from the peripheral interface via line 24, which only occurs when the peripheral is firmly connected and locked. The interlock alarm circuit has an automatic +5 volt DC solenoid driver that engages a solenoid that prevents the peripheral from being removed if +5 volt DC power is applied to the peripheral. . In an embodiment of the invention, output device 124 is a speaker that generates an audible alarm at appropriate times. In addition, speaker 1
It will be apparent to those skilled in the art that LEDs or other suitable display devices may be used in place of 24. S.C.
If the SI enable signal is active, i.e. (bus isolation is closed), no peripheral is connected, and the user attempts to connect or remove a peripheral from the bus, an alarm will occur. warns the user.

Although the invention has been described with emphasis on certain system buses and peripherals with reference to FIGS. 1-7, it will be apparent to those skilled in the art that the invention is not limited to these figures. Furthermore, the method and apparatus of the present invention can be used in any application where transient power suppression is required in a system having a computer bus and multiple peripheral devices. Furthermore, it will be obvious to those skilled in the art that the present invention can be variously modified based on the idea of the present invention.

[0023]

Effects of the Invention As described above, the present invention provides a power line for connecting a power source to a peripheral device.
Suppresses computer system power transients by electrically controlling up and ramp down voltages and currents, and suppresses current transients in system bus power lines by regulating voltages supplied to peripheral devices. can be minimized to obtain stability and validity of system level signals.

[Brief explanation of the drawing]

FIG. 1 is a computer system having a multiprocessor connected to a system bus and having multiple peripheral devices connected thereto.

FIG. 2 is a circuit diagram of a power lamp switch used in an embodiment of the invention.

FIG. 3 shows a circuit diagram of a system bus isolation switch connected to a system bus and a peripheral interface used in an embodiment of the invention; connected to the on/off timing circuit.

FIG. 4 is a circuit diagram of a bus isolation switch used in an embodiment of the invention.

FIG. 5 On/off used in embodiments of the present invention
FIG. 2 is a circuit diagram of an off-timing circuit.

FIG. 6 On/off used in embodiments of the present invention
FIG. 3 is a timing diagram illustrating a power on and power off sequence generated by an off timing signal reference signal.

FIG. 7 is a circuit diagram of an interlock alarm circuit used in an embodiment of the invention.

[Explanation of symbols]

10 System Bus 12 Power Lines 14 Signal Lines 18 CPU 20 Peripherals 22 System Bus Interface 24 Peripheral Interface 30 Power Lamp Circuit 80 Bus Isolation Switch 90 On/Off Timing Circuit 92 Toggle Switch 120 Interlock Alarm Circuit 124 Speaker 126 Gate drive

Claims (1)

[Claims] 1. A central processing unit comprising at least one central processing unit to which a first peripheral device is connected via an input and output (I/O) bus, the I/O bus including at least one second peripheral device. In an expandable computer system in which a peripheral device, a first power source, and a second power source are connected, the above I
connected between each of the signal lines of the I/O bus and the second peripheral device to isolate power transients caused by inserting or removing the second peripheral device from the I/O bus. a bus isolator connected to the bus isolator and the second peripheral device for switching to minimize impedance mismatching caused by insertion and removal of the second peripheral device; generating a plurality of timing signals to minimize the effect of power transients generated by the second peripheral device on normal read/write operations of the I/O bus during power up and power down sequences; an on/off timing device connected to the second voltage source and receiving a reference voltage; and an on/off timing device connected to the timing device and the second peripheral device, the computer system being connected to the second peripheral device when the first peripheral device is turned on. a lamp device isolated from transient currents from the first peripheral device and further connected to the first voltage source and the second voltage source; alerts the user to an implausible situation such as attempting to insert the second peripheral device into the I/O bus;
a warning device connected to the timing device, wherein the first peripheral device remains in communication with the processor via the I/O bus and the second peripheral device connects to the I/O bus. A transient power suppression device that minimizes transient conditions in a computer system when inserted or removed from the bus.