JPH06161907A - Memory controller - Google Patents

Abstract

PURPOSE:To reduce the power consumption and the heating value of a memory device. CONSTITUTION:This memory controller consists of the memory devices 14 and 15 which store the data, a CPU 11 which makes access to the devices 14 and 15, a +Vm terminal which receives the supply of the comparatively large electric power necessary for the access control of the devices 14 and 15 from a main power supply, a +Vb terminal which receives the supply of the comparatively small electric power necessary for holding the data of the devices 14 and 15 from a backup power supply, the memory control circuits 16 and 17 which detect the non-access time of both device 14 and 15 to the CPU 11, output the power switching signals when the detected non-access time lasts for the prescribed time, and stop the output of the power switching signal when the CPU 11 starts the accesses to the devices 14 and 15, and the transistors 18 and 19 which switch the power supplied to both devices 14 and 15 to the +Vb terminal from the +Vm terminal in response to the power switching signals received from the circuits 16 and 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device in which a relatively large amount of power required for access control is supplied from a main power source and a relatively small amount of power required for holding data is supplied from a backup power source.

[0002]

2. Description of the Related Art Conventionally, as this type of memory control device, the one shown in FIG. 3 has been known. This is the CPU
(Central processing unit) 1 inputs address data for accessing a memory via an address bus 2a to a decoder 3, and the decoder 3 selects the memory devices 4, 5 based on the address data. And C
The PU 1 stores data in the selected memory device via the data bus 2b.

+ Vm of the main power source for the memory devices 4 and 5
A relatively large amount of power required for access control is supplied from the terminal, and a relatively small amount of power required for holding data in the memory devices 4 and 5 is supplied from the + Vb terminal of the backup power supply.

Usually, a relatively large amount of power is supplied from the main power source to the memory devices 4 and 5, and the CPU 1 controls the access to the memory devices. Further, when the CPU 1 enters a power saving mode such as a power down mode due to some cause such as a power failure, the main power supply is switched to the backup power supply for memory backup.

[0005]

However, in this way CP
If the main power supply is not switched to the backup power supply unless the U is in the power-saving mode or other power-saving mode, even if the CPU is in the non-access state to the memory device, the power supply from the main power supply to the memory device is large. There is a problem that power is supplied and power consumption increases. In particular, in recent years, since the number of memory devices used has increased due to the increase in storage capacity, there has been a problem that the increase in power consumption becomes remarkable, and therefore the amount of heat generated increases.

Therefore, the present invention is intended to provide a memory control device capable of suppressing the power consumption in the memory device as much as possible, and thus reducing the amount of heat generation.

[0007]

According to the present invention, a memory device for storing data, a control means for accessing the memory device, and a relatively large electric power required for access control of the memory device are supplied from a main power supply. In a memory control device provided with a first input section and a second input section to which a relatively small amount of electric power necessary for holding data in a memory device is supplied from a backup power source, the non-access time of the control means with respect to the memory device is set. A power supply switching signal output means for detecting and outputting a power supply switching signal when the non-access time continues for a predetermined time, and stopping the output of the power supply switching signal when the control means starts access to the memory device; The input unit of the power supplied to the memory device in response to the power source switching signal from the output unit is changed from the first input unit to the second input unit. It is provided with a a power source switching means for switching.

[0008]

In the present invention having such a structure, when the non-access time of the control means with respect to the memory device continues for a predetermined time, the power supply switching signal output means outputs the power supply switching signal, whereby the power input section is the first. Is switched to the second input section, and the power supplied to the memory device is switched from the main power supply to the backup power supply. Therefore, after that, the power supply to the memory device becomes a small power from the backup power supply. When access to the memory device by the control means is started in this state, the power input unit is switched from the second input unit to the first input unit, and the power supplied to the memory device is supplied from the backup power source to the main power source. Is switched to.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 11 designates C which constitutes a control means.
PU, 14 and 15 are memory devices, respectively. When accessing the memory device 14 or 15, the CPU 11 uses the decoder 13 via the address bus 12a.
Is supplied with address data for selecting a memory device, whereby the decoder 13 outputs a selection signal for selecting one of the memory devices.
That is, the decoder 13 supplies the L level selection signal from the output terminal D1 to the memory control circuit 16 as the power source switching signal output means when selecting the memory device 14, and the output terminal D2 to L when selecting the memory device 15. A level selection signal is supplied to the memory control circuit 17 as a power supply switching signal output means.

In the memory device 14, relatively large electric power required for access control is supplied from the main power source to the + Vm terminal which is the first input section, and from this + Vm terminal, the PNP transistor 18 and the diode as the power source switching means. 20 is supplied via the backup power supply to the + Vb terminal, which is the second input section, and is supplied via the diode 22 from the + Vb terminal. ing.

The memory device 15 is supplied with a relatively large amount of power required for access control from the + Vm terminal via the PNP type transistor 19 and the diode 21 as a power source switching means, and a relatively small amount required for holding data. Electric power is supplied from the + Vb terminal through the diode 23.

When the L-level selection signal is input from the output terminal D1 of the decoder 13, the memory control circuit 16 outputs the L-level signal from the output terminal P1 to the base of the transistor 18, and also the selection signal. Is input for a predetermined period of time, an H level signal is output to the base of the transistor 18 as a power supply switching signal. In addition, the memory control circuit 17
When the L-level selection signal is input from the output terminal D2 of the decoder 13, the L-level signal is output from the output terminal P2 to the base of the transistor 19, and the selection signal is continuously input for a predetermined time. When not performed, an H level signal is output to the base of the transistor 19 as a power source switching signal.

The memory control circuits 16 and 17 are
Signals from the output terminals C1, C2, CS1 and CS2 are supplied to the memory devices 14 and 15, and signals from the wait terminals WAIT1 and WAIT2 are supplied to the CPU 11 via an OR gate 24.

As shown in FIG. 2, each of the memory control circuits 16 and 17 is provided with counters 31 and 32 and a latch circuit 33, and a selection signal from the decoder 13 is applied to a clear terminal CL of the counter 31. The power is supplied to the clear terminal CL of the counter 32 via the inverter 34. Also, the selection signal from the decoder 13 is supplied to one input terminal of a 2-input ant gate 36 via an inverter 35. The counters 31,
A clock signal CK is supplied to 32.

The counter 31 is cleared by the selection signal from the decoder 13, and in that state, the output terminal C
An L level signal is output from C to the transistors 18 and 19 through the buffer 37, and when the selection signal input is stopped, the clock signal CK is counted, and when the selection signal input stopped state continues for a predetermined time. The H level carry signal from the output terminal CC is used as a power supply switching signal in the buffer 37.
Is output to the transistors 18 and 19 via the.

Further, the signal from the output terminal CC of the counter 31 is supplied to the latch circuit 33 and is also supplied to the memory devices 14 and 15 via the inverter 38 as a signal from the output terminal C (C1, C2). There is.

The latch circuit 33 includes the counter 31.
The signal from the output terminal CC of the AND gate 36 is latched, and the latch output is supplied from the output terminal Q to the other input terminal of the AND gate 36. The AND gate 36 supplies the output H level signal to the enable terminal EN of the counter 32, and sends a wait signal WAIT to the CPU 11.
Is supplied as.

The counter 32 has an enable terminal EN.
When a signal of H level is input to, the clock signal CK is counted, and when a predetermined value is counted, H is output from the output terminal CC.
A carry signal of level is output, and the carry signal is supplied to the clear terminal CL of the latch circuit 33 through the inverter 37. It should be noted that during the time when the counter 32 counts a predetermined value, the CPU 11 operates in the memory device 1
It is set to the time required to access 4 and 15.

In the present embodiment having such a configuration, for example, when the CPU 11 accesses the memory device 14, the CPU 11 transfers the memory device 1 to the decoder 13.
4 address data is output. As a result, the decoder 13 outputs an L level selection signal from the output terminal D1 to the memory control circuit 16.

The memory control circuit 16 clears the counter 31 by inputting a selection signal. Then counter 31
The signal from the output terminal CC of the
8 is turned on, and power is supplied to the memory device 14 from the main power supply. The counter 31 thereafter counts the clock signal CL from the initial state, but the next access is performed before a predetermined time elapses, and the decoder 13 outputs the output terminal D.
When an L-level selection signal is input from 1, the counter 31
Is cleared again, and the ON state of the transistor 18 is continued.

Thus, when the access control of the memory device 14 by the CPU 11 is repeatedly performed within a predetermined time, the transistor 18 continues to be turned on, and the power is continuously supplied to the memory device 14 from the main power source. In this way, the CPU 11 accesses the memory device 14 and writes or reads data.

When a state in which the access control of the memory device 14 by the CPU 11 is not continued for a predetermined time or longer occurs, an H level carry signal is generated from the counter 31 of the memory control circuit 16 at this time. The switching signal is supplied and the transistor 18 is turned off. This cuts off the main power supply, so the power supply from the backup power supply is + Vb instead.
From the terminal through the diode 22.
The electric power at this time is smaller than that of the main power supply, and is such that the data of the memory device 14 can be held.

The latch circuit 33 latches the carry signal from the counter 31, and the latch circuit 33 outputs the output terminal Q.
To output an H level signal.

In this way, when the access control of the memory device 14 by the CPU 11 is not continuously performed for a predetermined time or longer, the power supplied to the memory device 14 becomes small and the power consumption is suppressed as much as possible.

Thereafter, the CPU 11 causes the memory device 1
4 is restarted, the counter 3 is activated by the L-level selection signal from the output terminal D1 of the decoder 13.
1 is cleared. As a result, the signal from the output terminal CC of the counter 31 becomes L level, the transistor 18 is turned on, and the power supply to the memory device 14 is switched from the backup power supply to the main power supply.

Further, L from the output terminal CC of the counter 31
The level signal passes through the inverter 35 and the AND gate 36.
The AND gate 36 outputs an H level signal, which is supplied to the CPU 11 as a wait signal WAIT and to the counter 32 as an enable signal. Thus, the counter 32 counts the clock signal CK. When the count value of the counter 32 reaches a predetermined value, the counter 32
The carry signal is output from the output terminal CC of the latch circuit 33 and the latch circuit 33 is cleared. In this way, the wait state for the CPU 11 is released, and the CPU 11 makes the memory device 1
4 will be access controlled.

Even if the access by the CPU 11 is restarted in this way, the CPU 11 is put in a wait state, and during this period, for example, preparations for operation of peripheral devices are prepared. Then, when the wait state is released and access control to the memory device 14 becomes possible, the peripheral device is ready to operate.

The above is the memory device 1 by the CPU 11.
The case of the access control of No. 4 has been described.
The same applies to the case of access control of the memory device 15 by.

As described above, even if the CPU 11 does not enter the power saving mode such as the power-down mode, if the access control to the memory device by the CPU 11 is not performed for a predetermined time or longer, the power supply to the memory device is supplied from the main power source. Since the backup power source is switched to a low power consumption, the power consumption by the memory device can be suppressed as much as possible, and the heat generation amount from the memory device can also be suppressed.

Therefore, when the number of memory devices is large, a great amount of labor can be saved, and in this way, when the number of memory devices is large, power is simultaneously supplied from the main power source to all the memory devices. There is almost no supply, so the power supply capacity can be reduced.

In the above embodiment, the case where two memory devices are used has been described, but the present invention is not limited to this, and it may be one case or three or more cases.

[0033]

As described in detail above, according to the present invention, it is possible to provide a memory control device capable of suppressing the power consumption of a memory device as much as possible and thus reducing the amount of heat generation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit configuration of a memory control circuit in the embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 11 ... CPU 14, 15 ... Memory device 16, 17 ... Memory control circuit 18, 19 ... Transistor

Claims (1)

[Claims] 1. A memory device for storing data, a control means for accessing the memory device, and a first input section to which a relatively large power required for access control of the memory device is supplied from a main power supply. In a memory control device provided with a second input section to which a relatively small electric power required for holding data of the memory device is supplied from a backup power source, a non-access time of the control means with respect to the memory device is detected, A power supply switching signal output means for outputting a power supply switching signal when the non-access time has continued for a predetermined time, and for stopping the output of the power supply switching signal when the control means starts accessing the memory device; An input part of power supplied to the memory device in response to a power source switching signal from the first input part, A memory control device comprising: a power source switching means for switching to a second input section.