JPH04246884A - Plating method of circuit board - Google Patents

Plating method of circuit board

Info

Publication number
JPH04246884A
JPH04246884A JP3012212A JP1221291A JPH04246884A JP H04246884 A JPH04246884 A JP H04246884A JP 3012212 A JP3012212 A JP 3012212A JP 1221291 A JP1221291 A JP 1221291A JP H04246884 A JPH04246884 A JP H04246884A
Authority
JP
Japan
Prior art keywords
circuit board
wiring patterns
holes
board
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3012212A
Other languages
Japanese (ja)
Inventor
Yuji Kato
雄二 加藤
Osamu Kotani
修 小谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Priority to JP3012212A priority Critical patent/JPH04246884A/en
Publication of JPH04246884A publication Critical patent/JPH04246884A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To enable a large number of wiring patterns to be connected at a single joint so as to enhance a circuit board in density by a method wherein the wiring patterns provided to both the front and rear of the circuit board are connected through through-holes. CONSTITUTION:Through-holes 14 are provided to a copper plated board 11 of glass epoxy resin or phenolic resin, the disused part of copper is removed through etching, and then wiring patterns 13 are formed on the front and rear of the board 11, resist is made to cover all the surface of the board excluding connection parts such as lands 12 or the like, and then gold plating is executed. All the wiring patterns 13 provided onto both the sides of the circuit board 11 are electrically connected together through the through-holes 14, and the lands located on both the sides of the board 11 are plated with gold. After a gold plating process is finished, a hole 15 larger than the through-hole 14 in diameter is punched with a press or bored with a drill so as to prevent a short circuit from occurring between the wiring patterns to shut off unneeded electrical conduction.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は電子機器の回路基板の
メッキ方法に関するものであり、特に、高密度両面回路
基板へメッキを行う方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of plating circuit boards for electronic equipment, and more particularly to a method of plating high-density double-sided circuit boards.

【0002】0002

【従来の技術】近時、電子機器の高性能化に伴い、回路
基板のランドに金メッキを行って高導電性及び防錆を図
ることが多くなっている。又、ベアチップIC等を金ワ
イヤでワイヤボンディングする場合、これを受けるラン
ドは金メッキされることにより、金ワイヤとの接合を良
好にしている。
BACKGROUND OF THE INVENTION Recently, as electronic devices become more sophisticated, the lands of circuit boards are often plated with gold to improve conductivity and prevent rust. Furthermore, when bare chip ICs and the like are wire-bonded with gold wires, the lands that receive the bare chips are plated with gold to improve bonding with the gold wires.

【0003】金メッキを行うに当り配線パターンを全て
導通しなければならず、図5に示すように、回路基板1
に設けられた各ランド2,2…の配線パターン3,3…
を連結部4で接続する。そして、各ランド2,2…へ金
メッキを行った後、鎖線で示すように前記連結部4より
大径の孔5をプレス又はドリルで孔明けし、相互の導通
を遮断する。
When performing gold plating, all wiring patterns must be electrically conductive, and as shown in FIG.
Wiring patterns 3, 3... of each land 2, 2... provided in
are connected at the connecting part 4. After each land 2, 2, . . . is plated with gold, a hole 5 having a larger diameter than the connecting portion 4 is bored by a press or drill, as shown by the chain line, to cut off mutual conduction.

【0004】0004

【発明が解決しようとする課題】従来の回路基板のメッ
キ方法は、前述したように配線パターン3,3…を連結
部4で接続してメッキ時の導通を行っているが、高密度
の回路基板では配線パターン3,3…が微細になり、一
個所の連結部4で接続する配線パターン3,3…の数が
増加してくる。然し、一個所の連結部4での配線パター
ン3,3…の接続数には限界があり、特に高密度両面回
路基板に於いては連結部4,4…の数が急増する。従っ
て、金メッキ後に行う孔5,5…の開穿作業も増加し、
作業工程が多くなると共に回路基板1に不要の孔5,5
…が多数残存することになる。
[Problems to be Solved by the Invention] In the conventional circuit board plating method, as mentioned above, the wiring patterns 3, 3... are connected at the connection part 4 to achieve continuity during plating. On the board, the wiring patterns 3, 3, . . . become finer, and the number of wiring patterns 3, 3, . . . connected at one connection portion 4 increases. However, there is a limit to the number of connections of the wiring patterns 3, 3, . Therefore, the drilling work for holes 5, 5, etc. to be performed after gold plating increases,
As the number of work steps increases, unnecessary holes 5, 5 are formed on the circuit board 1.
...will remain in large numbers.

【0005】そこで、高密度両面回路基板に於けるメッ
キ用の連結部の数を減少し、メッキ後の孔明け作業を軽
減するために解決されるべき技術的課題が生じてくるの
であり、本発明はこの課題を解決することを目的とする
[0005] Therefore, a technical problem has arisen that must be solved in order to reduce the number of connecting parts for plating in a high-density double-sided circuit board and to reduce the work of drilling holes after plating. The invention aims to solve this problem.

【0006】[0006]

【課題を解決するための手段】この発明は上記目的を達
成するために提案されたものであり、回路基板の両面に
設けた配線パターンをスルーホールにて導通し、該回路
基板の両面にメッキを行った後、所定のスルーホールへ
大径の孔を開穿して配線パターンの導通を遮断すること
を特徴とする回路基板のメッキ方法を提供するものであ
る。
[Means for Solving the Problems] The present invention has been proposed to achieve the above object, and involves connecting wiring patterns provided on both sides of a circuit board through through holes, and plating both sides of the circuit board. The present invention provides a method for plating a circuit board, which is characterized in that, after performing the above steps, a large diameter hole is drilled into a predetermined through hole to interrupt conduction of the wiring pattern.

【0007】[0007]

【作用】この発明はスルーホールにて回路基板の配線パ
ターンを接続している。スルーホールは回路基板の表裏
両面の配線パターンを導通させるので、一個所のスルー
ホールで回路基板両面の配線パターンを多数接続でき、
メッキのための接続個所を減少できる。
[Operation] This invention connects the wiring patterns of the circuit board using through holes. Through-holes provide electrical continuity between the wiring patterns on both sides of the circuit board, so multiple wiring patterns on both sides of the circuit board can be connected with one through-hole.
The number of connection points for plating can be reduced.

【0008】[0008]

【実施例】以下、この発明の一実施例を図1乃至図4に
従って詳述する。図1は電子機器の回路基板11の表面
を示し、各ランド12,12…を配線パターン13,1
3…にて接続してある。図示はしないが、前記回路基板
11の裏面にも配線パターンを設けてあり、ランドが形
成されている。そして、表面の配線パターン13,13
…と裏面の配線パターンとはスルーホール14により導
通してある。従って、回路基板11の表裏のランド12
,12…及び配線パターン13,13…は全て導通して
いる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. 1 to 4. FIG. 1 shows the surface of a circuit board 11 of an electronic device, and each land 12, 12... is connected to a wiring pattern 13, 1.
3. It is connected at... Although not shown, a wiring pattern is also provided on the back surface of the circuit board 11 to form a land. Then, the wiring patterns 13, 13 on the surface
... and the wiring pattern on the back surface are electrically connected to each other through a through hole 14. Therefore, the lands 12 on the front and back sides of the circuit board 11
, 12... and the wiring patterns 13, 13... are all electrically conductive.

【0009】図2は前記回路基板11の形成手順を示し
、先ずガラスエポキシ樹脂やフェノール樹脂等の銅被覆
基板にスルーホールを形成し、エッチング処理により銅
の不要部分を除去して、基板の表裏両面に配線パターン
を形成する。次に、ランド等の接続部分を除きレジスト
を被覆し、金メッキ処理する。回路基板の両面に設けた
配線パターンはスルーホールにより全て導通しているの
で、回路基板両面の各ランドに金メッキが行われる。 金メッキ後は、配線パターン相互の短絡を防止するため
に前記スルーホールより大径の孔をプレス打ち抜き又は
ドリル孔明けし、不要な導通を遮断する。
FIG. 2 shows the procedure for forming the circuit board 11. First, through-holes are formed in a copper-coated board made of glass epoxy resin, phenol resin, etc., and unnecessary parts of the copper are removed by etching. Form wiring patterns on both sides. Next, resist is coated except for connection parts such as lands, and gold plating is performed. Since the wiring patterns provided on both sides of the circuit board are all electrically conductive through the through holes, each land on both sides of the circuit board is plated with gold. After gold plating, in order to prevent short circuits between the wiring patterns, a hole with a larger diameter than the through hole is punched or drilled to interrupt unnecessary conduction.

【0010】図3及び図4に示すように、スルーホール
14にて回路基板11の表裏の配線パターン13,13
…を接続するので、一個所のスルーホールで多数の配線
パターンを接続できる。従って、高密度両面回路基板に
於ける金メッキ用の接続個所が減少し、金メッキ後に所
定のスルーホール14へ大径の孔15を開穿する作業が
軽減できる。
As shown in FIG. 3 and FIG.
Because it connects..., many wiring patterns can be connected with one through hole. Therefore, the number of connection points for gold plating on the high-density double-sided circuit board is reduced, and the work of drilling large diameter holes 15 into predetermined through holes 14 after gold plating can be reduced.

【0011】尚、この発明は、この発明の精神を逸脱し
ない限り種々の改変を為すことができ、そして、この発
明が該改変されたものに及ぶことは当然である。
[0011] This invention can be modified in various ways without departing from the spirit of the invention, and it goes without saying that the invention extends to such modifications.

【0012】0012

【発明の効果】この発明は上記一実施例に詳述したよう
に、メッキを行う回路基板の表裏両面の配線パターンを
スルーホールにより接続するので、一個所の連結部で多
数の配線パターンを接続できる。このため、回路基板の
高密度化が図れると共に、メッキ用の連結部の数を減少
でき、メッキ後の孔明け作業工程が短縮される。
Effects of the Invention As described in detail in the above-mentioned embodiment, this invention connects the wiring patterns on both the front and back sides of the circuit board to be plated using through holes, so that a large number of wiring patterns can be connected at one connection point. can. Therefore, it is possible to increase the density of the circuit board, reduce the number of connecting parts for plating, and shorten the hole-drilling process after plating.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】回路基板の要部平面図。FIG. 1 is a plan view of essential parts of a circuit board.

【図2】メッキ方法の手順を示すブロック図。FIG. 2 is a block diagram showing the steps of a plating method.

【図3】スルーホールの要部平面図。FIG. 3 is a plan view of essential parts of a through hole.

【図4】図3のA−A線断面図。FIG. 4 is a sectional view taken along line AA in FIG. 3;

【図5】従来型の回路基板の要部平面図。FIG. 5 is a plan view of main parts of a conventional circuit board.

【符号の説明】[Explanation of symbols]

11    回路基板 12    ランド 13    配線パターン 14    スルーホール 15    孔 11 Circuit board 12 Land 13 Wiring pattern 14 Through hole 15 Hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  回路基板の両面に設けた配線パターン
をスルーホールにて導通し、該回路基板の両面にメッキ
を行った後、所定のスルーホールへ大径の孔を開穿して
配線パターンの導通を遮断することを特徴とする回路基
板のメッキ方法。
1. Wiring patterns provided on both sides of a circuit board are electrically connected through through holes, plating is applied to both sides of the circuit board, and then large diameter holes are drilled into predetermined through holes to form wiring patterns. A method for plating a circuit board, characterized by cutting off conduction.
JP3012212A 1991-02-01 1991-02-01 Plating method of circuit board Pending JPH04246884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3012212A JPH04246884A (en) 1991-02-01 1991-02-01 Plating method of circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3012212A JPH04246884A (en) 1991-02-01 1991-02-01 Plating method of circuit board

Publications (1)

Publication Number Publication Date
JPH04246884A true JPH04246884A (en) 1992-09-02

Family

ID=11799080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3012212A Pending JPH04246884A (en) 1991-02-01 1991-02-01 Plating method of circuit board

Country Status (1)

Country Link
JP (1) JPH04246884A (en)

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