JPH04245745A - Service speed setting circuit - Google Patents

Abstract

PURPOSE:To prevent the size of this service speed setting circuit from being influenced by the number of set service speeds by applying a carry output from a counter to a data string as a mask pulse. CONSTITUTION:The service speed setting circuit has a counter circuit 1 for starting the counting of clock signals in accordance with a load input inputted at the head of a serial data input and applying its carry output to a data extracting circuit 4 as a mask signal and a service speed setting part 3 for applying a count value setting signal to be changed and set up in accordance with a service speed to the circuit 1. A new clock extracting circuit 2 for applying a clock signal extracted from a clock signal synchronous with the serial data input to the circuit 1 as a clock signal is also included.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention is utilized as means for setting service speeds contracted with users in digital transmission networks. In particular, the present invention relates to a setting means that is effective in setting user service speeds in detail.

0002

2. Description of the Related Art In digital signal transmission services, the transmission speed (hereinafter referred to as service speed) for each user is set. This is because charges differ depending on the service speed, and data that exceeds the service speed is not transmitted. That is, the communication carrier transmits data to the user at a certain fixed speed, and the communication carrier masks the data string according to the predetermined service speed.

FIG. 2 shows a circuit configuration of a conventional service speed setting section. A counter load input L whose timing is aligned with the beginning of the transmitted data string and a clock CLKI synchronized with the data string are input to the address counter circuit 5. Address counter circuit 5 counts clock CLKI according to counter load input L. The result is output as an N-bit (N: any positive integer) parallel signal. This parallel signal is input to the address input of the memory circuit 6. From this, the HL signal previously written in the memory circuit 6 is output as a serial mask pulse for each output port by the address output of the address counter circuit 5. M pieces output from the memory circuit 6 (
The mask pulse signal, which is a serial signal (M: any positive integer), is input to the selection circuit 7, and the service speed setting section 8
An appropriate one is selected from among the M mask pulse signals based on the signal output from the mask pulse signal, and is output as the signal PULSE. This signal PULSE is inputted together with the transmission data to the data sampling circuit 4, where only the data suitable for the service speed is extracted by the signal PULSE, so that an appropriate service speed can be set.

0004

[Problem to be Solved by the Invention] In such a conventional service speed setting circuit, it is necessary to prepare mask pulses for setting the service speed for the required number of service speeds, so the number of service speed settings is large. In this case, the number of memory circuits simply increases and the control of the selection circuit becomes complicated.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a service speed setting circuit in which the service speed setting does not affect the circuit configuration.

[0006]

[Means for Solving the Problems] The present invention provides a service speed setting circuit equipped with a data extraction circuit that masks serial data input by applying a mask signal to a load input input at the beginning of serial data input. a counter circuit that starts counting clock signals in accordance with the service speed and provides the carry output as a mask signal to the data extraction circuit; and a service speed setting section that provides the counter circuit with a count value setting signal that is changed and set in accordance with the service speed. and a new clock extracting circuit that provides, as a clock signal to the counter circuit, a clock signal extracted from a clock signal with which the serial data input is synchronized with the carry output of the counter circuit as a reference.

[0007]

[Operation] The count value of a general counter circuit that counts clocks is changed and set according to the service speed. The carry output of this counter circuit is given to the data extraction circuit as a mask signal. On the other hand, this carry output is given to a clock extraction circuit, and the clock given to the counter circuit is fixed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1(A) is a block configuration diagram showing the configuration of an embodiment of the present invention.

That is, as shown in FIG. 1(A), this embodiment includes a data extracting circuit 4 that applies a mask signal to mask serial data input, and furthermore, as a feature of the present invention, , a counter circuit 1 that starts counting clock signals in response to a load input input at the beginning of serial data input, and supplies the carry output as a mask signal to the data extraction circuit 4, and is changed and set according to the service speed. a service speed setting section 3 that provides a count value setting signal to this counter circuit 1;
The counter circuit 1 is provided with a new clock extracting circuit 2 which supplies a clock signal extracted from a clock signal with which serial data input is synchronized with the carry output of the counter circuit 1 as a clock signal.

Next, the operation of this embodiment will be explained. Figure 1 (
B) is its operation timing diagram. As shown in Figure 1(B), the serial data signal SI is connected to the clock CL.
It is input in synchronization with KI. In addition, the counter circuit 1 has an N-bit (N: any positive integer) count value setting input, performs counting by a clock input, and receives data set to the N-bit count value setting input by a counter load input. It has a carry output that goes high when it is loaded and counted up. data signal SI
A counter load input L corresponding to the timing of the first data to be extracted is input to the counter circuit 1. Further, the carry output of the counter circuit 1 is input to the clock extracting circuit 2 along with the clock, and only the clock necessary for setting the service speed is input to the counter circuit 1. As a result, the value set by the service speed setting unit 3 is input to the count value setting input of the counter circuit 1, and the counter circuit 1 starts counting by the clock output of the clock extraction circuit 2 and the count load input L, and counts up. At that point, the carry output goes high. Further, when the carry output becomes high, the output CLK0 of the clock sampling circuit 2 is fixed at high, the counter circuit 1 does not perform counting, and the carry output remains fixed at high. The result of this carry output is shown as the output PULSE in FIG. 1(B), which becomes the mask pulse for setting the service speed. The width at which the output PULSE becomes low can be freely set in units of one clock width by changing the count value setting input of the counter circuit 1. Next, the output PULSE of the counter circuit 1 is input to the data extraction circuit 4 together with the serial data signal SI, and data is extracted only where the output PULSE is low, and only the data corresponding to the service speed setting is sent to the data extraction circuit as S0. Output from 4.

[0011]

[Effects of the Invention] As explained above, the present invention uses a general counter having a count value setting input and a carry output, and by changing the count value setting, it is possible to freely clock by clock with a small circuit configuration. It is possible to output a mask pulse for data extraction, and when the data extraction portion is long, this effect can be realized by cascading a plurality of counter circuits. Further, by frequency-dividing the clock and inputting it to the counter circuit 1, data can be easily sampled in units of multiple bits.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram (A) showing the configuration of an embodiment of the present invention and a timing diagram (B) showing its operation.

FIG. 2 is a block configuration diagram showing the configuration of a conventional example.

[Explanation of symbols]

1 Counter circuit 2 Clock sampling circuit 3 Service speed setting section 4 Data extraction circuit 5 Address counter circuit 6 Memory circuit 7 Selection circuit 8 Service speed setting section

Claims (1)

[Claims] Claim 1: In a service speed setting circuit equipped with a data extraction circuit that masks serial data input by applying a mask signal, counting of clock signals is started in response to a load input input at the beginning of serial data input. a counter circuit that supplies the carry output as a mask signal to the data extraction circuit; a service speed setting section that supplies the counter circuit with a count value setting signal that is changed and set according to the service speed; and a carry output of the counter circuit. A service speed setting circuit comprising: a new clock extracting circuit which provides a clock signal extracted from a clock signal with which the serial data input is synchronized based on the clock signal as a clock signal to the counter circuit.