JPH04243459A - Double buffer control system - Google Patents

Abstract

PURPOSE:To improve the processing speed of a CPU and peripheral devices and to improve the operation efficiency of a buffer. CONSTITUTION:This double buffer control system is provided with double buffers 5a and 5b equipped with two stages of buffers for storing data, a retry response signal sending means 7 for returning a retry response signal of requesting for rewriting to a double buffer when a request for data writing is issued to the relevant double buffer with two states of double buffers 5a and 5b in buffer busy, a rewrite request means 1 for executing a request for writing again after releasing a bus once again when this retry response signal sending means 7 returns a retry response signal, and a means of treating, when a data read request is issued with the buffer at the first stage of double buffers 5a and 5b being in buffer busy and the other buffer being vacant, the other buffer for buffering 5a, 5b of the read request and executing, when the buffer busy state of the first stage buffer is terminated, the read request treated for the relevant buffering.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double buffer control method used in data processing devices such as bus conversion adapters and communication devices, and particularly to a double buffer control method for improving the processing speed of a CPU and peripheral devices.

0003

2. Description of the Related Art The data processing apparatus described above consists of a CPU, etc., which executes processing at high speed, and memory or I/O, which executes processing at low speed.
A data buffer is provided between the device and the device in order to prevent delays in processing by the CPU, etc. Above CPU
If the difference in processing speed between etc. and memory is even larger, use 2.
A stage or two or more stage data buffer (hereinafter referred to as a double buffer) was sometimes provided. Even when the above-mentioned double buffer is provided, the buffer may become busy because the processing speed of the CPU, etc. is faster than the processing speed of the memory, etc. When the buffer is busy, the CPU etc.
The process waits until the buffer becomes free, and
Processing by the CPU, etc. is delayed. In addition, since the bus connected to the CPU also stops while the CPU is in the waiting state, peripheral devices such as DMA devices cannot use the bus connected to the CPU and wait, even when not accessing the double buffer. become a state. Therefore, it is not easy to prevent the processing speed of the CPU and peripheral devices from decreasing when the buffer becomes busy.

In addition, in the case of a read access, etc., when the first stage buffer is in a buffer busy state, the first stage continues to wait for the read access until the buffer becomes empty, and the first stage buffer When it becomes free, a read request is made, and after the data is read, the CPU
operation starts. Therefore, the bus connected to the CPU cannot be used until the CPU resumes operation, making it difficult to improve buffer usage efficiency.

[0005]

[Problems to be Solved by the Invention] However, in the conventional double buffer control system, when the double buffer is busy, the CPU goes into a waiting state and peripheral devices such as DMA devices cannot use the bus. There has been a problem in that the processing speed of peripheral devices is slowed down and a time-over error occurs due to processing delays.

[0006] Furthermore, during read access, the second and subsequent stages of the double buffer cannot be used, resulting in a problem of reduced buffer usage efficiency.

The present invention has been made to solve the above-mentioned conventional problems, and its purpose is to prevent the processing speed of the CPU and peripheral devices from decreasing when the buffer is busy. Another object of the present invention is to provide a double buffer control method that improves the performance of the device by improving the buffer usage efficiency during read requests.

[Configuration of the invention]

[0009]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a double buffer having two stages of buffers for storing data, and a method for storing data when the two stages of the double buffer are busy. a retry response signal transmitter that returns a retry response signal indicating that a write request is to be made again when there is a data write request; and a rewrite request means for executing a data read request when the first stage buffer of the double buffer is busy and the other buffers are free, buffering the read request in the other buffer. and means for executing the buffered read request at the end of the buffer busy state of the first stage buffer.

0010

[Operation] With the configuration as described above, when a data write request is made to the double buffer when the two stages of the double buffer are busy and the buffer is busy, an instruction is issued to issue a write request again. Returns a retry response signal. When this retry response signal is returned, the write request is executed again after the bus is released, so that the bus can be occupied and the processing speed of other peripheral devices can be prevented from decreasing.

[0011] When a read request is received when the first stage buffer in the double buffer is busy and the other buffers are empty, the read request is buffered in the other buffer, and the first stage buffer is Since the buffered read request is executed when the buffer busy state ends, buffer usage efficiency can be improved.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing control of an embodiment of the double buffer control system of the present invention.

[0014] The double buffer control method described above is based on the CPU1
, a system bus 3, double buffers 5a and 5b, and a double buffer control circuit 7.

The CPU 1 has double buffers 5a, 5
When outputting to the system bus 3 a read request to read the data stored in the memory buffer 5a or a write request to write data to the double buffers 5a and 5b, the STROG (STB) is set to low level and the address and data of the read or write request are output. Specify. Further, when a retry response (RTY) signal is returned from the buffer control circuit 7 at the time of a read request or a write request, the CPU 1 temporarily releases the system bus 3 (Bus Busy becomes high level) and performs the bus acquisition operation again. Let's do it.

The system bus 3 is a multi-bus that connects the CPU 1, double buffers 5a and 5b, double buffer control circuit 7, main memory 11, and peripheral devices 9 and 13. The system bus 3 includes an address (Addr) signal, a data (Data) signal, a read/write (R/W▲active state at low level▼) request signal, a ready response (RDY) signal, a retry response (RTY) signal, and Transmit a bus busy signal.

The double buffers 5a and 5b can buffer addresses in two stages, write data in two stages, and read data in one stage, with the double buffer 5a being the first stage buffer, and the double buffer 5b being the second stage buffer. Points to the buffer.

The double buffer control circuit 7 controls the double buffers 5a and 5b, and when there is a read request or a write request from the CPU 1, it outputs a ready response (RDY) signal if the double buffers 5a and 5b can be used. Output. On the other hand, when there is a read request or a write request from the CPU 1 and the double buffers 5a and 5b are unavailable (buffer busy), the double buffer control circuit 7 outputs a retry response (RTY) signal to the CPU 1.

Further, the double buffer control system has a configuration including a peripheral device 9, a main memory 11, and a peripheral device 13.

The peripheral device 9 is, for example, a DMA mechanism, and can directly transfer data without going through the CPU 1 when accessing the double buffers 5a, 5b and the main memory 11.

The main memory 11 stores data at a predetermined address and is capable of reading or writing data to the double buffers 5a and 5b.

The peripheral device 13 is, for example, a bus conversion adapter, and when a write request is made by the CPU 1, the double buffer 5
Read the data stored in the predetermined addresses of a and 5b,
Double buffers 5a, 5 at the time of a read request from the CPU 1
This is to write data to a predetermined address of b.

Next, the operation of this embodiment will be explained using the time chart of FIG.

First, after the system is started, at T1,
The CPU 1 sets the strobe (STB) signal to low level and outputs the Addr signal of the address A1 and the Data of the data D1.
A signal write request is output to the system bus 3. When the above write request is input to the double buffers 5a, 5b and the double buffer control circuit 7 at T2, the peripheral device 1
3 writes data D1 to address A1 of the first stage double buffer 5a between T2 and T5. After the above-mentioned write request, the double buffer control circuit 7 outputs RDY at T2.
Returns the signal to CPU1.

When the RDY signal is returned, the CPU 1 sets the STB signal to low level at T3 and outputs a write request for address A2 and data D2. Although data D1 is being written to the double buffer 5a, since the second stage double buffer 5b is empty, the double buffer control circuit 7 takes in the write request at T4 and returns the RDY signal.

At T4, the double buffers 5a and 5b are in use with data D1 written to the first stage buffer and data D2 written to the second stage buffer, and at T5, the CPU 1 writes address A3 and data D3. Output the request. Since the double buffers 5a and 5b are in use at T5, the write request does not enter the double buffers 5a and 5b, and the double buffer control circuit 7 sends a retry response (RT
Y) Return the signal to CPU1. CP when receiving RTY signal
U1 sets Bus Busy to high level at T7, temporarily releases the system bus 3, and executes the bus acquisition operation again. If system bus 3 can be acquired, CPU1
At step 8, a write request for data D3 is output again to address A3. When the above-mentioned write request is output, the double buffer control circuit 7 outputs the RD at T9 because the first stage buffer 5a among the double buffers 5a and 5b is in an empty state.
Returns Y signal.

When a read request for address A4 is output from the CPU 1 at T10, the read request is buffered in the double buffer 5b since writing of data D2 by the peripheral device 13 is completed at T9. however,
The double buffer control circuit 7 returns the RTY signal at T11. After the peripheral device 13 finishes writing the data D3 at T10 to T13, the read request for address A4 is stored in the double buffer 5b, so the peripheral device 13
At step 17, data D4 at address A4 is read. T19
When the CPU 1 executes the read of the address A4 again, the double buffer control circuit 7 reads the data D4 from the peripheral device 13 until T17.
At step 17, the RTY signal is returned to the CPU1. At T19 again, C
When the PU1 outputs a read request, the double buffer control circuit 7 returns an RDY signal to the CPU1 at T20 since the reading of the peripheral device 13 is completed and the data D4 is stored in the double buffer.

As a result, even when the double buffers 5a and 5b are busy, the system bus 3 can be accessed, so the peripheral devices 9 and 13 can access the system bus 3, and the CPU 1 and the peripheral devices 13 can access the system bus 3. Processing speed can be improved.

Further, since the read request can be buffered at the time of a read request and the read request can be executed at the end of preprocessing, the efficiency of use of the double buffer can be improved.

The present invention is applicable to devices with a data buffering function such as low-speed peripheral devices with low processing speeds, bus conversion adapters, and shared memory devices, and is also applicable to single buffers.

[0031]

As explained above, in the present invention, when the buffer is busy, a retry response signal is returned and the bus is temporarily released.
Prevents the processing speed of U and peripheral devices from decreasing. Also,
By improving the buffer usage efficiency during read requests, it is possible to improve the performance of the device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing control of an embodiment of the double buffer control method of the present invention.

FIG. 2 is a time chart showing the operation of the present invention.

[Explanation of symbols]

1 CPU 3 System bus 5a, 5b Double buffer 7 Double buffer control circuit 9,13 Peripheral devices 11 Main memory

Claims (1)

[Claims] Claim 1: A double buffer having two stages of buffers for storing data, and a retry request that when a data write request is made to the double buffer when the two stages of the double buffer are busy, a write request is made again. retry response signal transmitting means for returning a response signal; rewrite request means for once releasing the bus and then executing the write request again when the retry response signal is returned by the retry response signal transmitting means; and one of the double buffers.
When a data read request is made when the buffer in the first stage is busy and other buffers are free, the read request is buffered in the other buffer, and when the buffer busy state of the first stage buffer ends. A double buffer control method comprising: means for executing the buffered read request.