JPH04241536A - Line controller - Google Patents

Abstract

PURPOSE:To execute stable transfer by holding the data transfer velocity of each line in a common control means and executing arbitration by starting the allocation of the high priority order of a bus request from a serial/parallel data converting means in the order of the high transfer velocity. CONSTITUTION:When no transmitting data are held in serial/parallel data conversion parts 2-1-2-N, those parts turn bus request signal lines 3-1-3-N to logic '1' and execute bus requests. When the plural bus requests are simultaneously executed, based on the contents of a transfer velocity holding part 11, a bus request arbitration part 12 accepts the bus request at the highest data transfer velocity through the signal line 3-1, for example. Then, a bus acknowledge signal line 4-1 is turned to logic '1' and the permission of bus use is applied. The conversion part 2-1 transfers parallel data with a memory under DMA. Thus, under run/over run is hardly generated, stable data transfer is enabled and the data transfer velocity can be set with arbitrary combination.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to line control equipment, especially DM
The present invention relates to a line control device that commonly controls a plurality of serial/parallel data conversion means operating in A mode.

0002

2. Description of the Related Art In a conventional line control device of this kind, a common control means grants bus request signals from each serial-to-parallel converter according to a fixed priority order to use the bus.

0003

[Problems to be Solved by the Invention] In the above-mentioned conventional line control device, when arbitrating bus requests from serial-to-parallel data conversion means, priority is given to bus requests from serial-to-parallel data conversion means having a faster data transfer rate. The priority is higher than bus requests for serial/parallel data conversion means with slower data transfer speeds, but since the priority was fixed in advance by hardware or firmware depending on the mounting position, requests of various data transfer speeds can be freely selected. There were disadvantages in that it could not be combined with other devices and the mounting position could not be chosen arbitrarily.

0004

[Means for Solving the Problems] The device of the present invention has a DMA
In a line control device that commonly controls a plurality of serial/parallel data conversion means that operate in a mode, the common control means includes a transfer rate holding means that holds the data transfer rate of each line, and a transfer rate holding means that holds the data transfer rate of each line. Based on the transfer speed, the bus requests from the serial/parallel data converting means are assigned higher priorities in descending order of transfer speed.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The line control device of this embodiment includes N serial/parallel data converters 2-1...2-N that mutually convert serial data on the line and parallel data on the data bus 5, and It has request signal lines 3-1...3-N, bus acknowledge signal lines 4-1...4-N, transfer rate holding means 11 in common control section 1, and bus request arbitration section 12.

The operation of the present invention will be explained based on FIG.

First, a host processor (not shown) controls each serial/parallel data converter 2-1...2-N for the common control unit 1.
Indicates the data transfer rate. The common control unit 1 instructs each serial/parallel data conversion unit 2-1 . . . 2-N via the data bus 5 and stores this instruction in the transfer rate holding unit 11.

When the serial/parallel data conversion units 2-1...2-N do not hold the transmission data, the bus request signal lines 3-1...3-N are set to logic "1" and the bus request is processed. I do. In addition, when received data accumulates for the number of bits set at the initial setting and can be output to the data bus 5, the bus request signal lines 3-1...3-N
A bus request is made with the logic "1". Of course, bus request signal lines for transmission processing and reception processing may be provided separately.

[0011] In general, the number of bits of transmitted and received parallel data is 8 bits or less, and in the case of high-speed data transfer, the cycle in which bus requests occur becomes shorter, so that the transmitted and received parallel data is transferred within one cycle. If not, an underrun/overrun will occur. For this reason, underruns/overruns are less likely to occur and stable data transfer can be achieved by preferentially accepting bus requests from lines with faster transfer speeds and performing DMA transfer of parallel data.

Now, when a plurality of bus requests are made at the same time, the bus request arbitration section 12 selects the bus request request with the fastest data transfer speed, for example, the bus request signal line 3--, based on the contents of the transfer speed holding section 11. 1, and the bus acknowledge signal line 4-1 is set to logic "1" to grant permission to use the bus. The serial/parallel data converter 2-1 transfers parallel data to and from a memory (not shown) using DMA.

[0013]

Effects of the Invention As explained above, the present invention maintains the data transfer rate of each line in the common control means, and refers to it when arbitrating bus requests from the serial-to-parallel data conversion means to achieve the fastest transfer rate. By accepting bus requests from serial/parallel data conversion means having data transfer speeds, data transfer speeds can be set in any combination, and there are no restrictions on the mounting location.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention.

[Explanation of symbols]

1 Common control section 2-1...2-N Serial/parallel data conversion section 3-1...
3-N Bus request signal line 4-1...4-N
Bus acknowledge signal line 11 Transfer rate holding unit 12 Bus request arbitration unit

Claims (1)

[Claims] 1. A line control device that commonly controls a plurality of serial/parallel data conversion means operating in a DMA mode, comprising: transfer rate holding means for holding the data transfer rate of each line within the common control means; 1. A line control device comprising: arbitration means for allocating and arbitrating bus requests from serial/parallel data converting means with higher priorities in descending order of transfer speed based on the contents of the transfer speed holding means.