JPH04239748A - Method of forming multilayer interconnection of semiconductor device - Google Patents

Abstract

PURPOSE: To improve a step coverage by forming a spacer made of an insulation substance on the side wall of a via hole and then a second layer electrode. CONSTITUTION: Anisotropic etching is made to an insulation layer 200, a spacer 200a is formed on the side wall of a via hole, and then a conductive substance is deposited on the entire surface of a semiconductor substrate and a second layer electrode 28 is formed. The spacer 200a is formed on the side wall of a via hole 50, thus preventing the insulation substance 10 from being exposed to air and absorbing water, and hence preventing the insulation substance 100 from being inflated because of the absorption of water. Also, it is the same as a first dielectric layer 22 and a second dielectric layer 26 of a substance constituent for constituting the spacer 200a, thus preventing a lamination structure between substance layers from being damaged by another thermal coefficient of expansion generated by a conventional via hole by a superb adhesion force with a multilayer film, and hence forming a reliable multilayer wiring structure.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device, in which a spacer made of an insulating material is formed on the side wall of a via hole, and then a second layer electrode is formed. Regarding the forming method.

0002

[Background Art] With the progress of miniaturization of LSI, various problems that can be called physical limits have become visible, but among them, especially regarding contacts,
Various problems have been pointed out, such as electrical mass transfer of conductive materials caused by disconnection of metal interconnects due to increased geometric steps, high resistance metal interconnects due to miniaturization, and mass transfer due to stress.

Multilayer wiring technology has been proposed to solve various problems of metal wiring due to miniaturization and to manufacture highly reliable and highly integrated semiconductor devices, but this is the first
After forming an interlayer insulating layer by forming an insulating material on the semiconductor substrate on which the electrode is formed, a via hole is formed by partially removing the interlayer insulating layer on the first electrode, and a conductive layer is formed in the via hole. It consists of a step of forming a third layer electrode by filling a substance.

[0004] Normally, in multilayer wiring technology, the second layer electrode is formed on an interlayer insulating layer that repeats the surface bending formed by the first layer electrode. The second layer electrode is formed after a planarization process is performed on the interlayer insulating film to overcome the step, since this is the most serious problem and causes various problems due to the surface step.

A conventional method for planarizing an interlayer insulating layer and a method for forming a second layer electrode by burying a via hole will be described with reference to FIGS. 1A and 1B.

The above drawing shows that after two transistors sharing one drain region 16 are formed on a semiconductor substrate 10 limited to one active region, a conductive material is applied to the source region 14 and drain region 16 of the transistors. It is based on a semiconductor element with a first layer electrode formed by vapor deposition. At this time, the multilayer wiring process includes the source region 1 of each transistor.
This is done to connect the first layer electrode 20 formed on the interlayer insulating layer 4 and the second layer electrode formed on the interlayer insulating film to electrically connect the source region 14 of each transistor.

First, a first dielectric layer 22 is formed on the semiconductor substrate 10 on which the first layer electrode 20 is formed, and an insulating material such as SOG (Spin-O) is coated on the entire surface of the first dielectric layer.
After forming a thick n-Glass layer 24 and hardening the SOG film by heat treatment at 150 to 450° C., etching back is performed by anisotropic etching, so that the recessed portion is filled with the first layer electrode. At this time, the etching process is performed until the surface of the first dielectric layer is exposed (FIG. 1A). Next, a second dielectric layer is formed on the entire surface of the semiconductor substrate in which the recessed portion is filled with the SOG film, and the interlayer insulating layer is formed by forming the first dielectric layer,
A second dielectric layer is formed on the first dielectric layer whose recess is filled with the SOG layer and is planarized. The via hole is formed by partially removing the interlayer insulating layer stacked on the first layer electrode using a photolithography process, and depositing a conductive material on the entire surface of the semiconductor substrate while filling the via hole. The second layer electrode 2 is formed by patterning the deposited conductive material to form wiring.
Complete 8.

[0008] The method for forming a multilayer wiring in which a second electrode is formed after planarizing an interlayer insulating film includes filling the recessed portion with an SOG layer and planarizing the interlayer insulating layer. To overcome low reliability of multilayer wiring due to surface bending by forming a second layer electrode formed on an interlayer insulating layer while overcoming the influence of a step caused by the first layer electrode. was completed. However, in the planarization process using the SOG layer, various problems arose due to the uneven etching ratio between the SOG layer and the dielectric layer. Explain.

FIG. 2 shows that when the SOG layer formed thickly on the first dielectric layer 22 is etched back by anisotropic etching,
etching ratios between the first dielectric layer and the SOG layer are different;
FIG. 5 is a diagram illustrating a case where the SOG layer is excessively etched; FIG. Usually, after applying a thick SOG layer to the entire surface of the first dielectric layer, the SOG layer is cured by heat treatment at, for example, 150 to 450°C. This is because it can be removed and subsequent steps can be easily performed. At this time, the content in which the curing process is performed is varied, and the etching ratio of the SOG layer is also varied according to the carbon content. Generally, the higher the temperature, the smaller the carbon content of the SOG layer, and the higher the temperature, the lower the carbon content of the SOG layer. The smaller the value, the slower the etching speed of the first dielectric layer.

In order to equalize the etching ratio of the SOG layer and the first dielectric layer, the curing process should be performed by appropriately adjusting the heat treatment temperature, but the adjustment conditions are complicated.
As shown in FIG. 2, the over-etched SOG layer 24a may leave the recesses unfilled. If the second dielectric layer is formed without filling the recessed portion with the excessively etched SOG layer and the interlayer insulating layer is completed, the desired flattening effect of the interlayer insulating layer by the SOG layer will be lost. A void (v
(oid) occurs, causing problems such as electrically opening the wiring.

FIG. 3 shows the SOG layer 2 on the first layer electrode where the SOG layer is under-etched to form a via hole.
This is a drawing in which 4b remains thinly. In a conventional method of planarizing an interlayer insulating layer by filling a recess, the material filling the recess is thickly formed over the entire surface of the first dielectric layer, and then the material is deposited on the top of the first dielectric layer. However, the remaining unetched material on the first dielectric layer may cause various problems when forming via holes, resulting in a high reliability of the second layer electrode. This is to prevent inhibition of formation.
The SOG layer used in the semiconductor device shown in FIG. 2 as a material that fills the recess has a strong property of absorbing moisture, and if exposed to the air, it will absorb moisture contained in the air. However, when the SOG layer absorbs water, its volume increases, and vice versa, its volume decreases.As shown in Figure 3, the SOG layer absorbs air on the side wall of the via hole. If the SOG is exposed inside the air, the volume expands due to the absorption of moisture contained in the air, which weakens the adhesive force with the first dielectric layer and the second dielectric layer and may destroy the laminated structure. When a second layer electrode is formed by depositing a conductive material into the exposed via hole of the layer, the SOG
Moisture contained in the layer moves to the conductive material made up of the second layer electrode, causing failures such as corrosion of metal wiring, thereby reducing the reliability of the semiconductor device.

0012

[Problems to be Solved by the Invention] It is an object of the present invention to solve various problems that have arisen in conventional multilayer wiring formation methods.
In order to form highly reliable multilayer wiring, after forming a spacer made of an insulating material on the sidewall of the via hole, a second
A method for forming multilayer wiring in a semiconductor device in which layer electrodes are formed is provided.

[0013]

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a multilayer wiring process in which a via hole is formed on a first layer electrode and then a second layer electrode is formed.
forming a first dielectric layer over the entire surface of the semiconductor substrate on which the first layer electrode is formed; forming an insulating material on the dielectric layer to fill the recess; Second
a step of laminating a dielectric layer; a step of performing a photolithography process to form a via hole on the second dielectric layer formed on the first layer electrode; and a semiconductor substrate in which the via hole is formed. forming an insulating layer on the entire surface; anisotropically etching the insulating layer to leave a spacer on the sidewall of the via hole; and forming a second dielectric layer inside the via hole and a second dielectric layer whose sidewalls are surrounded by the spacer. It is characterized by comprising a step of depositing a conductive material on the entire surface, and a step of patterning the conductive material in a desired wiring shape.

[0014]

[Function] The present invention allows the etching process of etching back for planarization to be inserted or removed at will after hardening the SOG layer on the first dielectric layer.
The physical properties of the layer itself or the SOG layer and the first and second
Various problems caused by physical property differences between dielectric layers can be solved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings.

FIGS. 4A to 5D are cross-sectional views showing a method for forming multilayer wiring in a semiconductor device according to the present invention.

The multilayer interconnection forming method used a semiconductor substrate with a pattern similar to that formed to explain the conventional multilayer interconnection forming method, but two transistors sharing one drain region 16 are connected to one active layer. A first layer electrode 20 is formed on the source region 14 and drain region 16 of each transistor.

First, referring to FIG. 4A, a first dielectric layer 2 is formed on the entire surface of the semiconductor substrate on which the first layer electrode 20 is formed.
2. This shows the process of laminating the insulating material 100 and the second dielectric layer 26 to form a planarized interlayer insulating layer,
A first dielectric layer 22 is formed on the entire surface of the semiconductor substrate on which the first layer electrode 20 is formed, for example, by plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition).
l Vapor Deposition) method
iO2 or TEOS (Tetraethyl Or
thosilicate) is deposited to a thickness of about 2,000 to 6,000 Å, and an insulating material is deposited on the entire surface of the first dielectric layer 22.
After the SOG layer is deposited to a thickness of about 0 to 4000 Å, a curing process is performed to evaporate water contained in the SOG layer and adjust the carbon content.

At this time, the insulating material, the nested SOG layer, is formed by at least one deposition and curing process, but this is because the SOG layer is thickly deposited in just one step by multiple depositions and curing processes. This is to prevent a crack phenomenon that may occur during curing, and the SOG layer deposited by the deposition and curing process is not completely removed on the upper surface of the first dielectric layer as in the conventional method. Since the S remaining on the upper surface of the first dielectric layer
No special etch-back process is required to remove the OG layer.

[0020] Next, PSG (Phosphorous
A second dielectric layer 26 made of Silicate Class (Silicate Class) or TEOS is deposited to a thickness of about 2000 to 6000 Å by a vapor deposition method such as PECVD, thereby completing the planarized interlayer insulating layer. At this time, the thickness of the first layer electrode is approximately 5,000 to 9,000 Å.

Referring to FIG. 4B, a photoresist pattern 60 for forming a via hole is formed on the interlayer insulating layer, and then a photolithography process is performed to form the via hole. After forming a photoresist to a predetermined thickness on the entire surface of the second dielectric layer 26, a photoresist pattern 60 for forming a via hole is formed.

Next, the second dielectric layer 26 exposed by the photoresist pattern 60 is subjected to isotropic etching to etch the second dielectric layer to a thickness of, for example, 1000 to 5000 Å, and then anisotropic etching is performed. The via hole 50 is completed by removing the first dielectric layer, the insulating material, and the second dielectric layer stacked on the first layer electrode. At this time, the via hole forming process is performed by widening the entrance of the via hole by an isotropic etching process, thereby achieving step coverage of the conductive material that is filled in the via hole and becomes the second layer electrode.
erage) can be improved.

Referring to FIG. 5C, a thin insulating layer 200 is formed on the entire surface of the second dielectric layer 26 in which the via hole is formed.
The insulating layer 200 is formed by depositing an insulating material such as SiO2 or TEOS to a thickness of about 500 to 1500 Å using, for example, PECVD.

Referring to FIG. 5D, the insulating layer 200 is anisotropically etched to form a spacer 20 on the sidewall of the via hole.
0a is formed, and then a conductive material is deposited on the entire surface of the semiconductor substrate to form a second layer electrode. The spacer 200a is a via hole formed when the insulating layer 200 is anisotropically etched. If a certain material is etched by anisotropic etching on the part of the insulating layer that remains on the sidewall of the insulating layer, the material applied perpendicular to the etching direction is often removed, but the material applied in the horizontal direction is often removed. The material applied in the direction is not removed well and remains on the sidewall portions of the step, forming spacers.

In the present invention, the role of the spacer 200a is to prevent the insulating material 100 formed on the side wall of the via hole from being exposed to the air and absorbing moisture. In addition to preventing the volume expansion of the spacer 200a, since the material components constituting the spacer 200a are the same as the first dielectric layer 22 and the second dielectric layer, it has excellent adhesion with the various films, making it possible to form a conventional via hole. A highly reliable multilayer wiring structure can be formed by preventing damage to the laminated structure between material layers due to other coefficients of thermal expansion caused by the spacer 200a, and the spacer 200a reduces the slope of the via hole. Advantageously, increasing the step coverage of the conductive material deposited in the via hole can also solve problems such as voids that can be formed in narrow via holes. Usually, the spacer has a sharp end and a wide bottom, so it is obvious that the step coverage compensation effect is possible.

It should be noted that the present invention is not limited to the embodiments described above, and various modifications can be made as necessary.

[0027]

[Effects of the Invention] As described above, SOG, which has been a problem in the conventional planarization process of interlayer insulating layers for forming multilayer wiring, has been solved.
It was possible to form a convenient and highly reliable multilayer wiring by reducing damage to the electrical characteristics of the device due to excessive or under-etched layers, but this is due to the SOG layer laminated on the first dielectric layer.
After curing the layer, an etching process for planarization can be inserted or removed at will. It can solve various problems caused by the physical characteristics of the dielectric layer, and it reduces the slope of the via hole and improves step coverage. It is possible to alleviate problems such as

[Brief explanation of the drawing]

FIGS. 1A and 1B are cross-sectional views showing a conventional method for forming multilayer wiring in a semiconductor device.

FIG. 2 is a cross-sectional view illustrating that an interlayer insulating material is excessively etched in a conventional method for forming multilayer interconnections of a semiconductor device.

FIG. 3 is a cross-sectional view illustrating that an interlayer insulating material is under-etched in a conventional method for forming multi-layer wiring in a semiconductor device.

FIGS. 4A and 4B are cross-sectional views showing a method for forming multilayer wiring in a semiconductor device according to the present invention.

FIGS. 5C and 5D are cross-sectional views showing a method for forming multilayer wiring in a semiconductor device according to the present invention.

[Explanation of symbols]

20 first layer electrode, 22 first dielectric layer, 26
second dielectric layer, 28 second layer electrode, 40 recessed part,
50 via hole, 100 insulating material, 200
Insulating layer, 200a spacer

Claims (23)

[Claims] Claim 1: After forming a via hole on a first layer electrode, in a multilayer wiring process in which a second layer electrode is formed, a first dielectric layer is formed on the entire surface of the semiconductor substrate on which the first layer electrode is formed. forming an insulating material on the first dielectric layer to fill the recess; laminating a second dielectric layer on the first dielectric layer and the insulator; forming a via hole by performing a photolithography process on the second dielectric layer formed on the electrode; forming an insulating layer over the entire surface of the semiconductor substrate where the via hole is formed; a step of anisotropically etching the layer to leave a spacer on the sidewall of the via hole; a step of depositing a conductive material inside the via hole whose sidewall is surrounded by the spacer and on the entire surface of the second dielectric layer; 1. A method for forming multilayer lines in a semiconductor device, comprising the step of patterning a material into a desired wiring shape. 2. The thickness of the first layer electrode is 0.5-0.
2. The method for forming a multilayer wiring for a semiconductor device according to claim 1, wherein the thickness is 9 μm. 3. The first dielectric layer is made of SiO2,
2. The method for forming multilayer interconnections in a semiconductor device according to claim 1, wherein the interconnection layer is one of TEO and PSG. 4. The first dielectric layer is formed by plasma accelerated chemical vapor deposition.
The method for forming multilayer wiring in a semiconductor device as described above. 5. The first dielectric layer has a thickness of 0.2 to 0.6
4. The method of forming multilayer wiring for a semiconductor device according to claim 3, wherein the multilayer wiring is deposited to a thickness of μm. 6. The method of forming multilayer wiring in a semiconductor device according to claim 1, wherein the insulating material is an SOG layer. 7. The method of forming multilayer wiring in a semiconductor device according to claim 6, wherein the insulating material is applied in at least one coating process. 8. The insulating material has a thickness of 0.05 to 0.4 μm.
7. The method of forming multilayer wiring for a semiconductor device according to claim 6, wherein the multilayer wiring is formed to have a certain thickness. 9. After the insulating material is formed, the second dielectric layer is self-planarized by filling the recess through an etch-back process. 6. The method for forming multilayer wiring in a semiconductor device according to 6. 10. The etch-back step includes the first
10. The method of forming multilayer wiring for a semiconductor device according to claim 9, wherein the step of forming a multilayer wiring for a semiconductor device is performed until the surface of the dielectric layer is exposed. 11. The etch-back step includes the first
10. The method of forming multilayer wiring for a semiconductor device according to claim 9, wherein the method is performed so that an insulating material remains on the dielectric layer. 12. The method of forming multilayer wiring in a semiconductor device according to claim 9, wherein the insulating material is deposited as is without an etch-back process. 13. The semiconductor device according to claim 6, wherein the second dielectric layer is self-planarized by repeatedly applying and curing the insulating material. Multilayer wiring formation method. 14. The method of forming multilayer wiring in a semiconductor device according to claim 1, wherein the second dielectric layer is made of the same material as the first dielectric layer. 15. The second dielectric layer has a thickness of 0.2 to 0.
15. The method of forming multilayer wiring for a semiconductor device according to claim 14, wherein the vapor deposition is performed to a thickness of 6 μm. 16. The method of forming multilayer wiring in a semiconductor device according to claim 1, wherein the etching step for forming the via hole includes isotropic etching followed by anisotropic etching. 17. The isotropic etching is performed until the edge of the second dielectric layer in contact with the via hole is etched by about 0.1 to 0.5 μm. A method for forming multilayer wiring for semiconductor devices. 18. The method for forming multilayer wiring in a semiconductor device according to claim 1, wherein the via hole has a size on the submicron level. 19. The size of the via hole is 0.
19. The method of forming multilayer wiring for a semiconductor device according to claim 18, wherein the thickness is 6 to 1.5 μm. 20. The insulating layer includes a first dielectric layer and a second dielectric layer.
Claim 1 characterized in that the material is the same as that of the dielectric layer.
The method for forming multilayer wiring in a semiconductor device as described above. 21. The insulating layer has a thickness of 0.05 to 0.15μ.
21. The method of forming multilayer wiring for a semiconductor device according to claim 20, wherein the multilayer wiring is deposited to a thickness of m. 22. The method of forming multilayer wiring for a semiconductor device according to claim 1, wherein the conductive material for forming the first layer electrode and the second layer electrode is a low resistance conductive material. 23. The method of forming multilayer wiring for a semiconductor device according to claim 1, wherein the conductive material for forming the first layer electrode and the second layer electrode is a high melting point metal.