JPH04237131A - Wiring formation method of semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the diffusion control of impurities in the connection part while connecting a bit wire to element formation region in high reliability without deteriorating the integration of element in the element formation region in order to electrically connect the element formation region to the bit wire by the connection part comprising polycrystal silicon layer, etc. CONSTITUTION:When a bit wire is buried in the part below an element formation region 6 of an SOT substrate formed by affixing a silicon substrate 12 through the intermediary of an insulating layer 5 and then the region 6 and the bit wire 9 are electrically connected by a polycrystal silicon layer 8, after affixing said silicon substrate 12, N type impurities, e.g. phosphorus (P) are led in said polycrystal silicon layer 8 by a high energy ion-implantation step.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring for semiconductor devices, and is particularly suitable for forming wiring for DRAMs and the like.

0002

[Prior Art] Recently, with the increasing integration of semiconductor devices such as DRAMs, stacked capacitors, which have a stacked structure for storing information, have begun to be used in order to secure their capacity. .

A conventional DRAM having a stacked capacitor has a field insulating layer 41 as shown in FIG.
The impurity diffusion region of the switching element Tr is formed facing the surface of the silicon substrate 42 on which the source/drain region 4 of one of the impurity diffusion regions is formed.
A bit line 45 made of, for example, an AL wiring layer is connected to 3a through an opening 44, and a capacitor lower electrode 46 of a stacked capacitor C is connected to the other source/drain region 43b.

The capacitor lower electrode 46 is formed by patterning a second polycrystalline silicon layer, and is connected to each gate electrode (word line) of the switching element Tr, which is a first polycrystalline silicon layer. It is formed up to the upper part of 47 with an interlayer insulating layer 48 interposed therebetween. This capacitor lower electrode 46 has a capacitor upper electrode 49 serving as a common electrode on its upper part with a dielectric film 50 interposed therebetween. The structure forms a stacked capacitor C. Note that 51 is a shunt (backing) metal wiring for reducing the resistance of the word line, and 52 is an interlayer insulating layer made of SiO2 or the like.

[0005] In the DRAM, necessary charges are accumulated in the stacked capacitor C, and reading and writing are performed via the bit line 45 while being controlled by the switching element Tr.

[0006]

[Problems to be Solved by the Invention] However, since the conventional DRAM described above has a structure in which many layers of polycrystalline silicon are stacked on the silicon substrate 42, the contact portion of the memory cell MC is There is a disadvantage that the step becomes large, causing deterioration of step coverage at the opening 44, etc., and making patterning of the upper layer, for example, patterning of the bit line 45, etc. difficult. Moreover, in order to increase the capacitance of the stacked capacitor C for future high integration, it is necessary to utilize the side wall of the capacitor lower electrode 46, which will serve as a storage node.
In this case, the step difference in the capacitor lower electrode 46 becomes even larger, and accordingly, the step difference in the contact portion increases, causing a problem such as disconnection of the bit line 45.

Furthermore, when the level difference in the memory cell MC increases, the patterning of the wiring at the connection part with peripheral circuits (for example, address decoders, etc.) where the level difference is relatively small may cause differences in depth of focus during exposure, etc. There is an inconvenience that it becomes difficult.

[0008] Therefore, in order to solve the above-mentioned inconvenience, for example, SOI (Silicon on insulin) is currently being used.
ator) For example, an SOI substrate in which a thin silicon layer is formed on an insulating layer is prepared using a technique for bonding silicon substrates together and a selective polishing technique for silicon substrates, and A technique has been proposed in which a part of the wiring, for example, a bit line, is buried under the silicon layer of the semiconductor device. This technology seems to be a promising method for increasing the integration density of DRAMs and the like in the future.

As shown in FIG. 8, in a DRAM based on this technology, a bit line 63 is formed under a silicon layer 61 constituting an element formation region with an insulating layer 62 interposed therebetween. source/drain region 64
are electrically connected by a polycrystalline silicon layer 65 using, for example, poly plug technology, and a contact portion 66 for a bit line is formed under the silicon layer 61. In this figure, 67 is a word line;
8 is a capacitor lower electrode, 69 is a dielectric film, 70 is a capacitor upper electrode, 71 is a shunt (backing) metal wiring for reducing the resistance of the word line 67, and 72 to 74 are interlayer insulating layers. Further, 75 is a polycrystalline silicon layer for planarization, and 76 is a silicon substrate.

Next, the DRAM bit line forming method according to the proposed example will be explained based on FIGS. 9 to 11. First, as shown in FIG. After selectively etching and removing the silicon surface in the portions to form recesses 78, an insulating layer 62 made of SiO2 is formed over the entire surface.

Thereafter, as shown in FIG. 9B, an opening 79 passing through the insulating layer 62 is formed in the center of the silicon substrate 77 that will become the element formation region 61. Thereafter, a polycrystalline silicon layer 65 is formed over the entire surface so as to fill the opening 79.
is formed by a CVD method or the like, and then etched back to bury a polycrystalline silicon layer 65 in the opening 79.
ly plug technology). After that, arsenic (As) was applied to the entire surface.
The above arsenic (As) is introduced into the upper part of the polycrystalline silicon layer 65 by ion implantation.

Next, as shown in FIG. 10A, a polycide layer is formed on the entire surface including the polycrystalline silicon layer 65, and then the polycide layer is patterned to form bit lines 63.
form. After that, Si is applied to the entire surface including the bit line 63.
After forming an insulating layer 74 made of O2, a polycrystalline silicon layer 75 is formed on the entire surface, and the surface of the polycrystalline silicon layer 75 is planarized by a known planarization technique (for example, polishing, etc.). Thereafter, another silicon substrate 76 is bonded to the end face of the planarized polycrystalline silicon layer 75.

Next, as shown in FIG. 10B, selective polishing is performed from the back surface of the other silicon substrate 77. This selective polishing is performed until the insulating layer 62 is exposed. By this selective polishing, an island-shaped silicon layer surrounded by the insulating layer 62, that is, an element formation region 61 is formed, and an element isolation region 80 is formed by the insulating layer 62.

After that, as shown in FIG.
7 and source/drain regions 64, an interlayer insulating layer 72, a capacitor lower electrode 68, a dielectric film 69,
The capacitor upper electrode 70, the interlayer insulating layer 73, and the metal wiring 71 are sequentially laminated to obtain the DRAM according to the proposed example.

However, the DRAM according to the above proposed example
The bit line forming method starts with opening 7 in FIG. 9B.
Arsenic (
After introducing As), the silicon substrates 77 and 76 are bonded together in FIG. 10A, which causes the following problem.

That is, the silicon substrate 7 shown in FIG. 10A above
When bonding 7 and 76 together, a high temperature of about 1100° C. is applied, so arsenic (As) introduced into the polycrystalline silicon layer 65 diffuses at high speed through the polycrystalline silicon layer 65 and disintegrates into the upper silicon layer 61. The phenomenon of diffusion in the silicon layer 61 in the lateral direction occurs (see FIG. 1).
1A). In this way, arsenic (As) is added to the silicon layer 6.
If the word line 67 is diffused into the word line 67 in order to secure a channel area in the subsequent process of forming the word line 67,
needs to be formed avoiding the arsenic (As) diffusion region, which increases the area of the silicon layer 61 and reduces the degree of integration of the DRAM built into the silicon layer.

[0017] As a countermeasure to this, the heat treatment time is shortened.
Alternatively, it is possible to increase the length L of the polycrystalline silicon layer 65, but in this case, there is a possibility that the diffusion of arsenic (As) in the polycrystalline silicon layer 65 becomes insufficient. That is, if arsenic (As) does not reach the interface b between the polycrystalline silicon layer 65 and the silicon layer 61, a large parasitic resistance will occur in the electrical connection between the bit line 63 and the silicon layer 65.
A new problem arises in that the characteristics of DRAM are significantly deteriorated. Therefore, in order to solve the above problem, arsenic (
As) reaches the interface b, and the silicon layer 6
It is necessary to control the diffusion of arsenic (As) so that it does not spread laterally through the material. However, as mentioned above, 1100
Since the diffusion rate is extremely fast at a high temperature of .degree. C., the above control is extremely difficult.

The present invention has been made in view of the above-mentioned problems, and its purpose is to bury bit lines under a silicon layer on an SOI substrate, and to further connect the silicon layer and bit lines with polycrystalline silicon. In the case of electrical connection using a connection part made of a silicon layer, etc., it is possible to easily control impurity diffusion in the connection part, and to connect the bit line and the silicon layer with high reliability without reducing the degree of integration of the device. An object of the present invention is to provide a wiring formation method for a semiconductor device that can perform the following connections.

[0019]

[Means for Solving the Problems] The present invention provides a wiring layer (bit line) 9 on a substrate 12 formed by bonding, an insulating layer 5 interposed therebetween, a wiring layer (bit line) 9 on the lower layer, and a semiconductor layer (element forming area) on the upper layer. ) 6 and in which a connecting semiconductor layer (polycrystalline silicon layer) 8 is embedded in an opening 7 provided in the insulating layer 5, after the bonding, the connecting layer is Impurities are introduced into the semiconductor layer 8 in a self-aligned manner to electrically connect the semiconductor layer 6 and the wiring layer 9.

[0020]

[Function] According to the above-described forming method of the present invention, impurities are introduced into the connecting semiconductor layer 8 by, for example, high-energy ion implantation after the substrates 12 are bonded together. Diffusion of impurities can be performed at temperatures below high temperatures. As a result, it becomes easier to control the diffusion of impurities introduced into the semiconductor layer, which makes it possible to prevent abnormal wide-area diffusion and poor diffusion of impurities, thereby increasing reliability without reducing the degree of integration of the device. A high electrical connection between the wiring layer 9 and the semiconductor layer 6 can be achieved.

[0021]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6. FIG. 1 is a process diagram showing a method for forming wiring of a DRAM according to a first embodiment along the manufacturing process of the DRAM. The steps will be explained in order below.

First, as shown in FIG. 1A, a predetermined portion of the silicon substrate 1, in this example, a portion of the silicon surface that will be an element isolation region, is selectively etched away to form a recess 2 of about 1000 Å, and then the entire surface is etched away. By applying thermal oxidation to
A thermal oxide film 3 (corresponding to the thickness from the silicon surface to the dotted line in the drawing) is formed on the entire surface. Then, for example, CVD
An insulating layer 4 made of SiO2 is formed by a method. Hereinafter, the thermal oxide film 3 and the insulating layer 4 will be simply referred to as an insulating layer 5.

Next, as shown in FIG. 1B, an opening 7 passing through the insulating layer 5 is provided in the center of the silicon substrate 1 that will become the element formation region 6. Thereafter, a polycrystalline silicon layer 8 is formed on the entire surface by CVD method or the like so as to fill this opening 7, and then etched back to bury the polycrystalline silicon layer 8 in the opening 7.
g technology). After that, the entire surface was covered with tungsten (
W) After forming the polycide layer 9, the tungsten (
W) Patterning the polycide layer 9 to form bit lines 9. After that, the entire surface including the bit line 9 is covered with SiO2.
An insulating layer 10 is formed by, for example, a CVD method.

Next, as shown in FIG. 2A, after depositing a polycrystalline silicon layer 11 on the entire surface, the polycrystalline silicon layer 1
1 by known planarization techniques (e.g. polishing, etc.)
flattened by

Thereafter, as shown in FIG. 2B, another silicon substrate 12 is bonded to the end surface of the planarized polycrystalline silicon layer 11, and then heat treatment is performed at a high temperature of approximately 1100° C. to form a bonded interface a. firmly adhere. After that, selective polishing is performed from the back surface of the other silicon substrate 1. This selective polishing is performed until the insulating layer 5 is exposed. By this selective polishing, an island-shaped silicon thin layer surrounded by the insulating layer 5, that is, an element forming region 6 having a thickness of about 1000 Å is formed, and an element isolation region 13 is formed by the insulating layer 5.

Next, as shown in FIG. 3A, an N-type impurity, for example, phosphorus (P) is ion-implanted into the entire surface (implantation energy: 150 to 200 KeV, implantation amount: about 1×10 16 cm).
-2). At this time, phosphorus (P) penetrates through the element formation region 6 and enters the insulating layer 5 and the polycrystalline silicon layer 8, so it hardly affects the impurity concentration in the element formation region 6. Moreover, enough phosphorus (P) is introduced into the polycrystalline silicon layer 8 for electrical connection. The concentration distribution of phosphorus (P) due to the above ion implantation has a peak value depth Rp of approximately 25
00 Å, and the standard deviation ΔRp is about 750 Å.

Next, as shown in FIG. 3B, heat treatment is performed to diffuse the phosphorus (P) introduced into the polycrystalline silicon layer 8. The heat treatment in this case is performed at a temperature lower than that used in the heat treatment during bonding, so phosphorus (
The diffusion rate of P) can be easily controlled. Therefore, the diffusion of phosphorus (P) can be stopped at the interface b between the element formation region 6 and the polycrystalline silicon layer 8. The illustrated example shows a state in which phosphorus (P) is diffused to the above-mentioned interface b portion of the element formation region 6, and the diffusion is stopped before it is diffused laterally in the element formation region 6.

Next, as shown in FIG.
A word line 14 made of a polycrystalline silicon layer or the like is formed thereon by patterning with a gate insulating film interposed therebetween. Thereafter, using the word line 14 as a mask, for example, N-type impurity ions are implanted into the source/drain region 15a in the element formation region 6.
, 15b and 15c, respectively. At this point, the switching element Tr consisting of the word line 14 and the source/drain region 15 is formed. Furthermore, SiO is applied to the entire surface.
After forming the interlayer insulating layer 16 made of 2, etc., openings penetrating the interlayer insulating layer 16 are formed at locations corresponding to the source/drain regions 15a and 15b. Thereafter, a second polycrystalline silicon layer is formed over the entire surface and patterned to form the capacitor lower electrode 17. At this time, the capacitor lower electrodes 17 are formed relatively wide so that the distance therebetween is the same as or slightly wider than the opening width of the bit line contact portion 18. Next, a thin dielectric film 19 is formed on the entire surface including the capacitor lower electrode 17 by, for example, a low pressure CVD method, and then a common capacitor upper electrode 20 made of a polycrystalline silicon layer is formed on the dielectric film 19. do. After forming an interlayer insulating layer 21 made of SiO2 or the like on the entire surface, a shunt metal wiring 22 for lowering the resistance of the word line 14 is formed by patterning to obtain a DRAM according to this example.

According to this first embodiment, as shown in FIG. 2B, the bit line 9 is connected under the element formation region 6 via the insulating layer 5.
After bonding another silicon substrate 12 to the silicon substrate 1 on which a polycrystalline silicon layer 13 is formed, with a polycrystalline silicon layer 13 having a flat surface interposed therebetween, an element formation region 6 is formed as shown in FIG. 3A.
Phosphorus (
Since phosphorus (P) is introduced from above the element formation region 6 by high-energy ion implantation, when this introduced phosphorus (P) is diffused into the polycrystalline silicon layer 8, it is used in the heat treatment during bonding. The heat treatment can be performed at a temperature lower than the temperature (high temperature of about 1100° C.). From this, the diffusion rate of phosphorus (P) can be easily controlled, and the diffusion of phosphorus (P) can be controlled, for example, in the element formation region 6.
It becomes possible to stop at the interface b between the polycrystalline silicon layer 8 and the polycrystalline silicon layer 8. Therefore, if the above wiring formation method is used, the DRA
Highly reliable electrical connection between the polycrystalline silicon layer 8 and the element formation region 6 can be achieved without reducing the degree of integration of M.

Next, the wiring forming method according to the second embodiment is shown in FIG.
The explanation will be based on. In this second embodiment, after the selective polishing shown in FIG. 2B, the entire surface is thermally oxidized to form a gate insulating film 23 on the element formation region 6, as shown in FIG. Form. After that, after forming a resist film 24 on the word line 14,
By high-energy ion implantation of phosphorus (P) from above,
It is introduced into the insulating film 5 and the polycrystalline silicon layer 8 under the element formation region 6. Since the remaining steps are similar to those in the first embodiment, their explanation will be omitted.

According to this second embodiment, when ion-implanting phosphorus (P), the channel region in the element formation region 6 is protected by the word line 14 and the resist film 24, so that the channel region is protected by the ion implantation. No damage from injection. Therefore, the operating characteristics of the DRAM formed on the element formation region 6 can be further improved.

Next, FIG. 6 shows a wiring forming method according to the third embodiment.
The explanation will be based on. This third embodiment shows wiring formation in the case where the length L of the polycrystalline silicon layer 8 connecting the element formation region 6 and the bit line 9 is long, for example, about 1 μm.

First, in FIGS. 1A and 1B, after forming an insulating layer 5 on a silicon substrate 1, an opening 7 passing through the insulating layer 5 was formed, and a polycrystalline silicon layer 8 was embedded in this opening 7. Thereafter, as shown in FIG. 6A, arsenic (As) is introduced into the upper part of the polycrystalline silicon layer 8 by, for example, ion implantation. After that, through the same steps as in FIGS. 2A and 2B, the element formation region 6 and the bit line 9 under the element formation region 6 were connected by the polycrystalline silicon layer 8 on the bonded silicon substrate 12. Form a wiring structure. When bonding the silicon substrates 12 together, heat treatment at high temperatures is performed, but the length L of the polycrystalline silicon layer 8 is approximately 1
Because of the length of μm, diffusion of arsenic (As) ends halfway within this polycrystalline silicon layer (insufficient diffusion). In this example, after this bonding process, as shown in FIG. 6B, phosphorus (P) is ion-implanted into the entire surface with high energy to form the insulating layer 5 and polycrystalline silicon layer 8 under the element forming region 6.
The above phosphorus (P) is introduced into. Thereafter, as in the first embodiment, heat treatment is performed to diffuse the phosphorus (P) introduced into the polycrystalline silicon layer 8. At this time, arsenic (As) introduced in advance before the bonding process is diffused again, and the electrical connection between the element forming region 6 and the bit line 9 is completed by the diffusion of these impurities from both sides.

According to the third embodiment, as in the first embodiment, phosphorus (P) introduced into the polycrystalline silicon layer 8 is
During the diffusion treatment, the heat treatment can be performed at a temperature lower than the temperature used for the heat treatment during bonding (high temperature of about 1100°C), so the diffusion rate of phosphorus (P) can be easily controlled, and the device formation Good electrical connection between region 6 and bit line 9 can be achieved. Furthermore, before bonding the silicon substrate 12, arsenic (As) is applied to the polycrystalline silicon layer 8 in advance.
Since the polycrystalline silicon layer 8 is introduced in a relatively long length, for example, 1 μm, it is possible to easily make the polycrystalline silicon layer 8 conductive.

As described above, according to this example, after bonding the silicon substrates 1 and 12, impurities are implanted into the polycrystalline silicon layer 8 connecting the element forming region 6 and the bit line 9 by high-energy ion implantation. Since the impurity is introduced, the impurity can be diffused at a temperature lower than the high temperature applied during bonding, and the diffusion of the impurity introduced into the polycrystalline silicon layer 8 can be easily controlled. As a result, abnormal wide-area diffusion of impurities and defective diffusion can be prevented, and higher integration of the DRAM and higher reliability of the electrical connection between the bit line 9 and the element forming region 6 can be achieved.

[0036]

Effects of the Invention According to the wiring forming method for a semiconductor device according to the present invention, a bit line is buried under an element formation area of an SOI substrate formed by bonding silicon substrates together, and furthermore, a bit line is buried between the element formation area and the bit line. When electrically connecting wires to wires using a connecting portion made of a polycrystalline silicon layer, etc., impurities are introduced into the connecting portion in a self-aligned manner after the silicon substrates are bonded together. In addition, it is possible to easily control impurity diffusion in the semiconductor device, and to achieve highly reliable connection between the bit line and the device formation region without reducing the degree of device integration.

[Brief explanation of the drawing]

[Fig. 1] Process diagram (Part 1) showing a method for forming wiring of a DRAM according to the first embodiment.

[Fig. 2] Process diagram (part 2) showing the DRAM wiring forming method according to the first embodiment.

[Fig. 3] Process diagram (part 3) showing the DRAM wiring forming method according to the first embodiment.

FIG. 4 is a process diagram (part 4) showing the DRAM wiring formation method according to the first embodiment.

FIG. 5 is a progress diagram showing a DRAM wiring formation method according to the second embodiment.

FIG. 6 is a progress diagram showing a DRAM wiring formation method according to the third embodiment.

[Fig. 7] A configuration diagram showing a DRAM according to a conventional example.

[Fig. 8] Configuration diagram showing a DRAM according to a proposed example

[Fig. 9] Process diagram showing the DRAM wiring formation method according to the proposed example (Part 1)

[Fig. 10] Process diagram (Part 2) showing the DRAM wiring formation method according to the proposed example

[Fig. 11] Explanatory diagram showing the diffusion state of impurities according to the proposed example

[Explanation of symbols]

5 Insulating layer 6 Element formation area 8 Polycrystalline silicon layer 9 Bit line 12 Silicon substrate 14 Word line 15 Source/drain region 17 Capacitor lower electrode 18 Bit line contact part 19 Dielectric film 20 Capacitor upper electrode

Claims (1)

[Claims] 1. A substrate formed by bonding, a wiring layer below and a semiconductor layer above through an insulating layer, and a semiconductor layer for connection in an opening provided in the insulating layer. 1. A method for forming wiring in a semiconductor device embedded therein, which comprises introducing impurities into the connecting semiconductor layer in a self-aligned manner after the bonding.