JPH0423522A - Encoding circuit and decoding circuit - Google Patents

Abstract

PURPOSE:To display high error detecting and correcting function by a comparatively miniaturized circuit by coding a binary code consisting of the simple parities of respective symbols by a block coding part. CONSTITUTION:The 1st simple parity computing part 10 computes the simple parity of plural bits constituting each symbol. The block coding part 12 encodes at least a part of the simple parity corresponding to one block which is computed by the computing part 10 into a binary block code. A code combining part 14 combines the inspection code part of the binary block code generated from the coding part 12 and the multi-digit code of one block as one code word. Consequently, high error detecting and correction function for a multi-digit code can be displayed by the comparatively miniaturized circuit.

Description

[Detailed Description of the Invention] [Summary] Encoding circuits and decoding circuits introduced for the purpose of increasing the reliability of information in communication equipment, computer equipment, AV equipment, etc., especially multi-dimensional coding circuits composed of multiple bits. Regarding encoding circuits and decoding circuits that target code sequences, the purpose of this invention is to provide encoding circuits and decoding circuits that exhibit high error detection and correction capabilities in relatively small-scale circuits. is a first simple parity calculation unit that calculates simple parity of a plurality of bits constituting each symbol, and binary BCH encodes at least a part of one block of the simple parity calculated by the first simple parity calculation unit. A decoding device comprising: a BCH encoding unit; and a code synthesis unit that combines a check code portion of a BCH code generated by the BCH encoding unit and one block of multi-dimensional code to form one code word; The circuit includes a code separation unit that separates a check code part of the BCH code and the one block of multi-dimensional code from the one code word, and calculates simple parity of a plurality of bits constituting each symbol of the one block of multi-dimensional code. out of the simple parity calculated by the second simple parity calculation unit, a portion corresponding to the simple parity to be encoded by the BCH encoding unit, and the code separation unit; Combines the check code part of the BCH code separated by
A BCH decoding unit that identifies error positions by calculating syndromes;
and an error symbol removal unit that removes the symbol corresponding to the error position identified by the BCH decoding unit as an error symbol.

[Industrial application field]

The present invention is directed to encoding circuits and decoding circuits introduced for the purpose of increasing the reliability of information in communication equipment, computer equipment, AV equipment, etc., and particularly to multi-element code sequences composed of multiple bits. This invention relates to encoding circuits and decoding circuits.

[Conventional technology]

As an error correction encoding method for multi-component codes,
Reed-Solomon codes are the most common and are widely used in computer equipment and AV equipment. The 5bEC code used for error detection and correction of storage elements is also one of this type.

[Problem to be solved by the invention]

Reed-Solomon codes are highly efficient codes, and
Encoding with high error correction capability is possible. but,
As the error correction capability increases, the scale of the decoding circuit increases significantly and the operating time also increases.

Therefore, an object of the present invention is to provide an encoding circuit and a decoding circuit that are designed for multi-component codes and exhibit high error detection and correction capabilities with a relatively small circuit.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

The encoding circuit of the present invention is an encoding circuit that blocks-encodes a sequence of multi-dimensional codes in which one symbol is composed of a plurality of bits, and includes a first simple parity calculation unit 10, a block encoding unit 12, The synthesis section 14 is configured to include a synthesis section 14.

The first simple parity calculation unit 10 calculates simple parity of a plurality of bits constituting each symbol.

The BCH encoding unit 12 includes the first simple parity calculation unit 1
At least a part of one block of simple parity calculated with 0 is binary block encoded. The code synthesis unit 14 synthesizes the check code portion of the binary block code generated by the block encoding unit 12 and one block of multi-dimensional code to form one code word.

The decoding circuit of the present invention is a decoding circuit that decodes a code word encoded by the aforementioned encoding circuit, and includes a code separation unit 5
6, a second simple parity calculation section 50, a block decoding section 52, and a symbol removal section 54.

The code separation unit 56 separates the check code portion of the binary block code and the multi-dimensional code of the one block from the one code word. The second simple parity calculation unit 50 calculates simple parity of a plurality of bits constituting each symbol of the one block of multi-dimensional code. The block decoding unit 52
Of the simple parity calculated by the simple parity calculation unit 50, the part corresponding to the simple parity that was encoded by the block encoding unit 12 and the check code of the binary block code separated by the code separation unit 56. The error position is identified by combining the parts with the above and calculating the syndrome. The error symbol removing unit 54 removes the symbol corresponding to the error position identified by the block decoding unit 52 from among the multiple codes of the one block as an error symbol.

Preferably, the aforementioned encoding circuit further includes an RS encoding section 20 that performs Reed-Solomon encoding on the multi-component code sequence and supplies the encoded code to the code synthesis section 14 and the simple parity calculation section 10.

Further, the above-described decoding circuit further includes the code separation unit 56
It is preferable to include an RS decoding section 60 that performs Reed-Solomon decoding processing on one block of multi-component codes separated by , and supplies the result to the error symbol removal section 54 .

[For production]

Since binary codes consisting of simple parity of each symbol are encoded in the block encoder 12 and decoded in the block decoder 52 to detect error symbols, the configuration of the block decoder 52 is extremely simple. Become.

Furthermore, by using the RS encoding section 20 and the RS decoding section 60 together, error symbols can also be corrected.

〔Example〕

FIG. 2 is a diagram for explaining an example of the encoding process in the encoding circuit of the present invention. In order to simplify the explanation and illustration, an example will be described in which information is encoded in units of four symbols, each of which consists of three bits. a is the element 0.1.of the Galois field GF(23).
α...It is expressed as α6.

First, gr(x) = (x-α)(X-α2)=x2+α4
Data b is subjected to Reed-Solomon encoding using a generator polynomial g, (x) expressed by x+α3, and parity d is added (column (A)→column (b)). Next, calculate simple parity for each symbol to obtain 4-bit simple parity e (
(B)@→(C) column).

g, (x) -x3+x+1 Using the generator polynomial represented by (2), a 4-bit simple Palomon code is added to d (column (D) → column (E)) to generate a code word g with a code length of 7 symbols. (Column (F)) Figure 3 is the second
FIG. 3 is a diagram for explaining a process of decoding a code word that is generated by the encoding circuit described in the figure and that may contain an error, using the decoding circuit according to the present invention.

The code word g' (column (A)) is the symbol f generated from parts b' and d' of the Reed-Solomon code and simple parity.
((Column B). Simple parity is calculated for each symbol of information symbol b' to obtain 4-bit parity e', which together with the 3 bits of symbol f' makes 7-bit BCH code e'. f' (column (C)). Reed-Solomon code b'd' and BCH codes e/, f/ are each decoded, and if there is a bit in which an error is detected by BCH decoding, the corresponding symbol is is removed as an error symbol.

FIG. 4 is a diagram showing the configuration of an example of an encoding circuit that implements the encoding according to the present invention explained in FIG. 2.

The simple parity calculation circuit 100 has two E
It consists of an OR gate and calculates and outputs simple parity by performing mode 2 addition of each bit of the 3-bit data from the data generating section 700. BCH
The encoding circuit 120 converts BC every 4 bits according to equation (2).
H encode and output 3 check bits. The RS encoding circuit 200 encodes RS every 4 symbols according to equation (1).
It encodes and outputs a 6-symbol RS code. The code synthesis unit 142 adds 3 check bits of the BCH code generated by the BCH encoding circuit 120 to the 6-symbol code from the R8 encoding circuit 200 as one symbol, and generates a 7-bit code word. Output. The timing control section 140 includes a BCH encoding circuit 120 and an RS encoding circuit 20.
0 and the code synthesis unit 140, a control signal is output to them for giving appropriate operation timing.

FIG. 5 is a diagram showing the configuration of an example of a decoding circuit that implements the decoding process explained in FIG. 3.

Similar to the simple parity calculation circuit 100, the simple parity calculation circuit 500 has two E
It consists of an OR gate and calculates and outputs the simple parity of received data. Among the outputs of the simple parity calculation circuit 500, the BCH decoding circuit 520 uses the 4 parity bits corresponding to the information symbol as information bits, and the 3 bits constituting one symbol added at the end in the encoding process as check bits. The BCH code is decoded, and if there is an error, the error position is detected. The RS decoding circuit 600 decodes six symbols excluding the last symbol added during the encoding process, and detects and corrects error symbols. The discrimination circuit 540 combines the error detection results of the BCH decoding circuit 520 and the RS decoding circuit 600, and for errors which cannot be corrected but whose position of the erroneous symbol can be detected, a signal is sent to remove the symbol at that position. is output, and an alarm is output if the error is detected but the position of the symbol cannot be detected. For example, in the case of an audio signal, the removed symbol can be interpolated from its surrounding values. The timing control section 560 includes a BCH decoding circuit 520 and an RS decoding circuit 6.
00, and a control signal for giving appropriate operation timing to the discrimination circuit 540.

In the examples described so far, we have described a method that uses RS codes in combination to enable correction of minor correctable errors, but if it is sufficient to detect the position of the error symbol, Only the BCH code is sufficient, and in that case, the RS encoding circuit 200 in FIG. 4 and the RS decoding circuit 600 in FIG. 5 are unnecessary.

The number of bits in one symbol is not limited to 3 bits, but can be 8 bits or more. Regarding error correction ability, it is possible to use BCH codes and RS codes that have even higher error correction ability. In addition, in the above example, the unit parity is BCH encoded only for information symbols, but it is also possible to target parity symbols of RS codes, and in that case, the probability of error correction caused by the RS code is reduced. be able to.

〔Effect of the invention〕

As described above, the present invention provides an encoding circuit and a decoding circuit that can exhibit high error detection and correction capabilities with a relatively small circuit.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention. Fig. 2 is a diagram for explaining the encoding process according to the present invention. Fig. 3 is a diagram for explaining the decoding process according to the present invention. Fig. 4. 5 is a diagram showing an embodiment of the encoding circuit of the present invention, and FIG. 5 is a diagram depicting an embodiment of the decoding circuit of the present invention. In the figure, 10...first simple parity calculation unit, 12...block encoding unit, 14...code synthesis unit, 20...R
S encoding section, 50... Second simple parity calculation section, 52... Block decoding section, 54... Error symbol removal section, 56... Code separation section, 60... RS decoding Department.

Claims (1)

[Claims] An encoding circuit for block-coding a sequence of multi-component codes in which each symbol is composed of a plurality of bits, the first simple coding circuit calculating the simple parity of the plurality of bits constituting each symbol. 1 of the simple parity calculated by the parity calculation unit (10) and the first simple parity calculation unit (10)
a block encoding unit (12) that encodes at least a part of the block into a binary block; and a block encoding unit (12) that encodes a check code portion of the binary block code generated by the block encoding unit (12) and a multi-dimensional code of one block. An encoding circuit comprising: a code synthesis unit (14) that synthesizes code words into one code word. 2. A decoding circuit for decoding a code word encoded by the encoding circuit according to claim 1, wherein the check code part of the binary block code and the multi-dimensional code of the one block are decoded from the one code word. Code separator (
56), a second simple parity calculation unit (50) that calculates simple parity of multiple bits constituting each symbol of the multi-dimensional code of the one block, and a second simple parity calculation unit (50) that calculates A portion of the simple parity that corresponds to the simple parity that was encoded by the block encoding unit (12) and a check code portion of the binary block code separated by the code separation unit (56) are combined. and a block decoding unit (52) that specifies the error position by calculating the syndrome;
52). A decoding circuit comprising: an error symbol removal unit (54) that removes a symbol corresponding to the error position identified by step 52) as an error symbol. 3. The multi-component code sequence is subjected to Reed-Solomon encoding and the code synthesis unit (14) and the simple parity calculation unit (14)
2. The encoding circuit according to claim 1, further comprising an RS encoding section (20) for supplying an RS encoder to an RS encoder (20). 4. A decoding circuit for decoding a code word encoded by the encoding circuit according to claim 3, wherein the code separation unit (56)
The error symbol removing unit (54) performs Reed-Solomon decoding processing on one block of multi-dimensional code separated by
). Claim 2 further comprising: an RS decoding unit (60) for supplying the RS to the
The decoding circuit described.