JPH04233351A - Inspection device for series controller - Google Patents

Abstract

PURPOSE:To improve the function of a main controller by inspecting an automatic sampling determining function and an automatic frame length function of the main controller based on outputs of an output point number counter and a time counting means. CONSTITUTION:An input signal sends out an initial frame signal to a main controller 100 through an inspecting device 20. The controller 100 varies length of input and output data contained in the frame signal and transmits them. Subsequently, a signal corresponding to the initial frame signal received by executing an automatic sampling time determining function and frame length based on the initial frame signal is formed and transmitted. This data frame signal is received by a receiving means, and an output point number counter counts the number of all bits of output data in the signal, based on an output of the receiving means. Also, a time counting means executes time counting of sampling. In such a way, by discriminating an output of a counter output means, the function of the controller 100 can be improved.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is a serial control device suitable for use in centralized control systems for various machines such as presses, machine tools, construction machines, ships, and aircraft, as well as for unmanned conveyance devices, unmanned warehouses, etc. In particular, a main controller and multiple nodes are connected in series in a closed loop, and each node is connected to one or more sensors that output data and one or more actuators that input data. The present invention relates to a testing device for a serial control device for testing various functions of the main controller in a control device.

0002

[Prior Art] When centrally managing presses, machine tools, construction machinery, ships, aircraft, unmanned transport devices, unmanned warehouses, etc.
A large number of sensors to detect the state of each part of the device and a large number of actuators to control the state of each part of the device are required. For example, when considering a press, the number of sensors and actuators is as high as 3,000 or more, and in other devices, the number may be even larger.

The present applicant has already filed an application for a serial control device as shown in FIG. 9 as a central management system for centrally managing this type of device. The main feature of this serial control device is that although it has a configuration in which nodes are connected in series, it abandons the idea of assigning an address to each node and identifies each node by the order in which it is connected, thereby improving address processing. This makes it unnecessary, eliminates the time delay associated with address processing, and further simplifies the configuration of the node.

In the series control device shown in FIG.
-1, 1-2, . . . 1-N are arranged at each part of the machine and detect the status of each part of the machine. The actuator groups 2-1, 2-2, . . . 2-N are arranged at each part of the machine and drive each part of the machine. These sensor groups 1-N
and actuator group 2-N are respectively nodes 10-
N (N=1 to N), and these nodes 10
-1 to 10-N are connected in series in a loop including the main controller 100. Main controller 10
0 mainly controls data exchange with the plurality of connected nodes 10-1 to 10-N. The host controller 200 centrally controls a machine (such as a press) in which this system is mounted, and serves as a higher-level controller of the main controller 100. Further, the host controller 200 performs an operation of transmitting data to be transmitted to each node to the main controller 100 and receiving data received from each node via the main controller 100.

FIG. 10 shows a frame structure of a data signal used in the system when the number N of nodes is 5. This data frame signal is sent from the main controller 100 and sent to the nodes 10-1 and 10-1. -2,
...After passing through 10-N, the main controller 100
will be returned to. Note that FIG. 10(a) shows the data frame signal immediately after being output from the main controller 100, and FIG.
The data frame signals output from nodes 10-2, 10-3, and 10-4 are shown in FIG. signals) are shown respectively.

The contents of each signal in the frame structure of FIG. 10 are as follows.

[0007] STI; input data (sensor data) DI
1st start code DI indicating the starting position; Input data (sensor data) DIq; Input data STO from the sensor connected to the q-th node; 2nd start code indicating the starting position of the output data (actuator drive data) Start code DO; Output data (actuator drive data) D
Oq; Output data SP to the actuator connected to the qth node; Stop code C indicating the end position of the data string
RC: CRC code for CRC check ERR: Code indicating the presence or absence of an error, error content, and error location In each node 10-1 to 10-N shown in FIG.
As shown in (b) to (f), the detection data DIq of the sensor 1 connected to the node is added between the start code STI and the start code STO, and the detection data DIq of the sensor 1 connected to the node is added after the start code STO. The output data DOq to the actuator 2 is extracted. Therefore, in this system, if the main controller 100 sends a data frame signal including actuator control data DO as shown in FIG. 1→node 10-2→node 10-3→node 10-4→10-5, the actuator control data DO in the data frame signal is allocated to the corresponding node, and each The detection data of the sensor group obtained at the node is incorporated into the same data frame signal. As a result, when the data frame signal is fed back to the main controller 100, as shown in FIG. 10(f), the actuator control data D
All O's disappear, and the detection data of the sensor group is included in the same frame signal.

In this configuration, the main controller 100 mainly has the functions listed below.

■Data length automatic determination function: When the power is turned on, the initial frame signal with all actuator control data DO in the data frame signal shown in FIG. 10 turned off (the length of DO is longer than the total number of possible actuators) is used. The number of output points (total number of actuators) is automatically detected from the difference between the length of the actuator data in the initial frame signal sent to and received by the node and the length of the actuator data in the transmitted initial frame signal. Data length Ld in the data frame signal actually sent (Figure 1
0) is determined.

■Sampling time automatic determination function...The number of input points (total number of sensors) is automatically detected from the length of sensor data in the received initial frame signal, and the detected value of this number of input points and the detected number of output points are The sending period T (sampling time) of the data frame signal shown in FIG. 10 is determined according to the above (see FIG. 11).

[0011] Function for checking the number of input/output points multiple times: The initial frame is sent out many times at a predetermined period, and only when the detected number of input/output points is the same a predetermined number of times in succession is adopted as the true number of input/output points. However, if a transmission error occurs in the received initial frame signal, it is ignored and not included in the number of times of verification.

■ Transmission data frame signal creation function: Forms the data frame signal shown in FIG. 10 based on the actuator control data sent from the host controller 200, and sends it to the node.

■Disconnection and disconnection position detection function: detects disconnections and disconnection positions between nodes based on disconnection signals sent from nodes.

[0014] Function to verify sensor data multiple times: The sensor data in the received data frame signal is adopted as true sensor data only after it has been the same for a predetermined number of consecutive times. However, if a transmission error occurs in the received data frame signal, it is ignored and not included in the number of times of verification.

Conventionally, the following methods have been used to test the various functions of the main controller 100 when a failure occurs or during a shipping inspection.

[0016] Sampling time T and transmission data length Ld
When inspecting, the main controller 100 was disassembled, predetermined signal lines on the board were connected to an oscilloscope or logic analyzer, and the waveforms of the oscilloscope or logic analyzer were checked. However, with such a primitive method, there are problems in that the inspection takes time and accurate inspection cannot be performed.

Conventionally, in order to test various functions of the main controller 100, a personal computer is connected to the main controller 100, and the personal computer forms a data frame signal to be received by the main controller 100. The signal was sent to the main controller 100. When forming this data frame signal, conventionally, as shown in FIG. 12, all the data frame signals for a plurality of periods desired to be sent are written in a memory, and by reading out the data stored in this memory, a plurality of data frame signals as shown in FIG. The data frame signal for the period is sent to the main controller 100.
I was trying to send it to. This data becomes the reception data of the main controller 100, and each of the functions (1) to (4) above are tested. In other words, conventionally, in order to transmit a data frame signal of one data pattern (data content, data length, length of non-transmission interval) for multiple cycles, the same data pattern is written to multiple different addresses. It was.

[0018] Such a conventional method has the problem that it is necessary to rewrite the data stored in the memory each time data with a different data pattern is transmitted, and each test takes time.

[0019]

[Problems to be Solved by the Invention] The present invention has been made in view of the above circumstances, and an object thereof is to provide an inspection device for a series control device that can perform various functions of a main controller simply, accurately, and at high speed. shall be.

[0020]

[Means for Solving the Problems] In the first invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller is connected to first and second special nodes. A data frame signal containing a code and output data to the actuator is sent at a predetermined period, and each node adds input data from a sensor connected to the node after the first special code and connects to the node. The main controller extracts the output data to the actuators after the second special code, and the main controller extracts the output data for the first and second special codes and the number of actuators before sending the data frame signal. transmitting an initial frame signal containing data, based on the length of the input data and the output data in the initial frame signal received via the plurality of nodes, the total number of bits of the sensor and the length of the actuator; A sampling time automatic determination function that detects the total number of bits and determines the transmission interval of the data frame signal according to these detected values, and automatically determines the length of the data frame signal according to the total number of bits of the detected actuator. In the serial control device having an automatic frame length determination function, the lengths of the input data and output data in the initial frame signal are varied and the initial frame signal to be received by the main controller is sent to the main controller. a transmitting means for receiving the data frame signal formed and transmitted by the main controller based on the initial frame signal transmitted by the transmitting means; and a receiving means for receiving the data frame signal formed and transmitted by the main controller based on the initial frame signal transmitted by the transmitting means; an output point counter for counting the total number of bits of the output data in the data frame; and a timer for timing the sending interval of the data frame signal based on the output of the receiving means; Based on the output, the automatic sampling time determination function and automatic frame length determination function of the main controller are checked.

[0021] In the second invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller sends a data frame signal containing output data to the actuator in a predetermined manner. each node adds input data from a sensor connected to the node to the data frame signal, and extracts output data to an actuator connected to the node from the data frame signal; In the serial control device, the output data portion of the transmitted data frame signal is specified by a host controller higher than the main controller, and the output data portion specified by the host controller is configured to have the same data pattern for every predetermined number of bits. and a first register having the same number of bits as the predetermined number of bits to which the same data pattern as the output data specified by the host controller is set, and a main controller formed by the data designation by the host controller. a receiving means for receiving the transmitted data frame signal; a second register for latching the output data portion being outputted by the receiving means for the predetermined number of bits;
a comparison means for comparing outputs of the first and second registers; an error detection means for detecting a transmission error in a data frame signal received by the reception means; and a detection signal not outputted by the error detection means. and detecting means for detecting that the main controller is operating normally when a coincidence signal is output from the comparing means.

In the third invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller sends a data frame signal containing output data to the actuator in a predetermined manner. Serial control in which each node adds input data from a sensor connected to the node to a data frame signal and extracts output data to an actuator connected to the node from the data frame signal. In the apparatus, a memory means for storing a plurality of types of data for one cycle of the data frame signal including non-transmission interval data, a start address register for latching a read start address of the memory means;
The outputs of an end address register for latching a read end address of the memory means and the start address register are initially loaded, and a counting operation from the initial loading is performed by counting a predetermined clock signal,
a counter means that outputs this count output to the memory means as a read address of the memory means; and a counter means that compares the output of the counter means with the output of the end address register, and outputs an output of the start address register each time the comparison result matches. a comparison means for initially loading the value into the counter means; and a control means for outputting a control signal for controlling readout of the memory means and setting the readout start address and readout end address in the start address register and end address register. The data frame signal read from the memory means is transmitted to the main controller to perform various tests on the main controller.

The start address register and the end address register each have a two-stage configuration, and the second stage start address register and end address register are as follows:
When a match signal is output from the comparison means, each latch data of the start address register and the end address register of the first stage may be latched.

In the fourth invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller sends a data frame signal containing output data to the actuator in a predetermined manner. Serial control in which each node adds input data from a sensor connected to the node to a data frame signal and extracts output data to an actuator connected to the node from the data frame signal. In the device, when inspecting the main controller, the data string in the data frame signal received by or transmitted from the main controller is set so that the basic data pattern is repeated every predetermined bit, and the basic data The pattern is characterized by employing a data string that does not match the original data string even if the data is rotated lower or upper by 1 to the predetermined bit minus 1 bit. In the fifth invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller sends first and second special codes and output data to the actuator. Each node adds the input data from the sensor connected to the node after the first special code, and sends the output data to the actuator connected to the node at a predetermined period. The main controller periodically extracts an initial frame signal including the first and second special codes and data for detecting the number of actuators before sending out the data frame signal. and detecting the total number of bits of the sensor and the total number of bits of the actuator based on the lengths of the input data and the output data in an initial frame signal received via the plurality of nodes. In the serial control device, the detection result is adopted as a true detection value when the detection result coincides with the plurality of consecutive times, and the sending interval of the data frame signal is determined according to the adopted detection value. memory means for storing a plurality of types of data for one cycle of the initial frame signal including transmission interval data;
A start address register for latching the read start address of the memory means, an end address register for latching the read end address of the memory means, and the output of the start address register are initially loaded, and by counting a predetermined clock signal, A counter means that performs a counting operation from an initial load and outputs this count output to the memory means as a read address of the memory means, and an output of this counter means and an output of the end address register are compared, and the comparison result is a match. a comparison means for initially loading the output of the start address register into the counter means each time the main controller receives at least two different input data; The initial frame signal with length and output data length is 1
or a control means for setting the read start address and read end address in the start address register and end address register so as to be output every plural cycles, and a transmitter for transmitting the output of the memory means to the main controller. a transmitter, further comprising a receiver for receiving a frame signal formed and transmitted by the main controller based on the frame signal transmitted by the transmitter, and a receiver for receiving the frame signal formed and transmitted by the main controller based on the frame signal transmitted by the transmitter; a receiving device having an output point counter for counting the total number of bits of the output data of the receiver, and a clock means for counting the sending interval of the data frame signal based on the output of the receiving means; Based on the output of the timer, the main controller verifies the detection function of the total number of bits of the actuator and sensor multiple times.

In the sixth invention, a plurality of nodes to which one or more sensors and actuators are connected are connected in a loop including a main controller, and the main controller is connected to the first and second special cords and the actuators. A data frame signal containing output data is sent at a predetermined period, and each node adds input data from a sensor connected to the node after the first special code, and outputs the data to the actuator connected to the node. The main controller extracts data after the second special code, and the main controller is configured to extract data after the second special code, and when the input data of the sensor in the data frame signals received via the plurality of nodes match n times in a row, In a serial control device having a verification function adopted as true input data, a memory means for storing a plurality of types of data for one cycle of the data frame signal including non-transmission interval data;
A start address register that latches the read start address of the memory means, an end address register that latches the read end address of the memory means, and the outputs of the start address register are initially loaded, and by counting a predetermined clock signal, A counter means that performs a counting operation from the initial load and outputs the count output to the memory means as a read address of the memory means, and an output of the counter means and an output of the end address register are compared, and a comparison result is obtained. comparing means for initially loading the output of the starting address register into the counter means each time there is a match; a transmitting device having a control means for setting a read start address and a read end address in the start address register and the end address register; and a transmitting means for transmitting the output of the memory means to the main controller; Upon receiving a data frame signal, the input data verification function is tested while varying the number of times n of verification of the input data verification function in the main controller.

[0026]

[Operation] The first invention provides a data frame signal transmission interval (sampling time) according to the total number of bits (number of input points) of the sensor detected based on the initial frame signal and the total number of bits (number of output points) of the actuator. This is to test the sampling time automatic determination function that determines the data frame signal and the frame length automatic determination function that determines the length of the data frame signal according to the detected number of output points, and the data frame signal is received by the main controller via the node. Instead of the initial frame signal, the transmitting means is used to send an initial frame signal to the main controller to be received by the main controller. Then, the lengths of the input data and output data included in this initial frame signal are appropriately varied and transmitted. In the main controller,
Forming a data frame signal having a sampling period and data length corresponding to the received initial frame signal by executing the sampling time automatic determination function and the frame length automatic determination function based on the received initial frame signal; Send. The data frame signal sent from the main controller is received by the receiving means on behalf of the node. The output point counter counts the total number of bits of the output data in the data frame signal based on the output of the receiving means, and the timer counts the total number of bits of the output data in the data frame signal based on the output of the receiving means. Measure the sampling time. Therefore, by identifying the outputs of these output point counters and timekeeping means, the automatic sampling time determination function and automatic frame length determination function of the main controller can be tested.

A second aspect of the present invention is to test the data frame signal creation function of the main controller that creates a data frame signal to be transmitted based on output data specified by the host controller. The output data portion designated by the controller is made to repeat the same data pattern every predetermined number of bits. Then, the same data pattern as the output data designated by the host controller is set in the first register, and the output data part of the data frame signal formed and transmitted by the main controller according to the data designation by the host controller is set in the second register. , compares the outputs of the first and second registers, detects a transmission error in the received data frame signal, and detects that no error detection signal is output due to this error detection and that the comparison results match. When this occurs, it is determined that the data frame signal creation function of the main controller is operating normally. A third invention is an improvement in the configuration for creating a frame signal to be transmitted to the main controller in order to test various functions of the main controller, and a memory means stores the data frame signal including non-transmission interval data. Multiple types (multiple patterns) of data for one cycle are stored. This memory means is addressed by the count output of said counter means. When reading data stored in this memory means, the start address of the memory means is initialized in the counter means according to the contents of the data frame signal desired to be transmitted, and the contents of the desired data frame signal are The end address of the memory means is set in the end address register in accordance with the end address of the memory means. When the counting operation is started from the start address set by the counter means, this count value is outputted to the memory means as an address signal, thereby executing reading from the start address. The comparison means constantly compares the address of the currently accessed memory means with the set end address, and outputs a match signal when they match. When this match signal is output, the start address set in the start address register is reloaded into the counter means, and the counter means again performs the counting operation from the reloaded start address. Such operations are repeatedly executed. That is, by repeatedly specifying addresses from a set start address to an end address, a data frame signal stored for only one cycle is transmitted over a plurality of cycles. By changing the designation of the start address and end address, arbitrary data and data frame signals of arbitrary cycles can be transmitted to the main controller. Note that if the start address register and end address register are configured in two stages, no matter when the setting data of the start address register and end address register in the first stage are changed, the data frame signal being transmitted will be the data frame signal. It will no longer be interrupted in the middle.

The fourth invention relates to the contents of a data string in a frame signal transmitted to the main controller in order to test various functions of the main controller. (Number of bits in the basic pattern below - 1 bit) For example, by adopting a data string such as 00111001 (in the case of 8 bits) that does not match the original data string even if the bits are shifted to the lower or higher bits, the bit shift can be avoided. Even if it occurs, it can be immediately identified. Therefore, if this data string is used as a basic pattern and the basic pattern is repeated, it becomes possible to determine bit shifts in all data.

[0029] The fifth invention examines the continuous verification function of the number of input and output points, which is adopted as a true detected value when the detection results match multiple times in a row when detecting the number of input points and the number of output points described above. Instead of the initial frame signal that the main controller receives via the node, the transmitting device is used to send the initial frame signal that the main controller should receive to the main controller. At this time, a transmission operation is performed such that initial frame signals having different input data lengths and output data lengths are output every one or more cycles. If the number of input/output points does not match in the plurality of consecutive verifications, the main controller sends the initial frame signal to the node again, and the transmitting device cannot determine the number of input/output points in the continuous verification. Therefore, the initial frame signal is being sent. Therefore, in this case, if the main controller continues to send out the initial frame signal, it means that the continuous verification function of the main controller is operating normally. Therefore, the continuous verification function is tested by checking whether or not the initial frame signal is being sent from the main controller based on the output of the output point counter or the time measuring means of the receiving device.

[0030] The sixth invention inspects the input data matching function, which is adopted as true input data when the input data of the sensor in the data frame signal received via a plurality of nodes matches n times in a row. The transmitter continuously transmits data frame signals having a plurality of different input data contents. In the main controller, while receiving the data frame signal from the transmitting device, the number of times of collation n of the input data collation function is changed as appropriate, and the input data collation result is determined according to this change. Determine whether the data matching function is working properly.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows the overall configuration of an embodiment of the present invention, in which an inspection device 20 for inspecting various functions of a main controller 100 includes a personal computer (personal computer) 30 and an expansion board EB loaded in this personal computer 30. It consists of A part of the part consisting of the personal computer 30 and the expansion board EB receives transmission data from the main controller 100, and also receives transmission data from the main controller 100.
It has a function of transmitting received data of 0, and this part replaces the part constituted by the plurality of nodes 10-1 to 10-N of the serial control device system shown in FIG. 9 earlier.

FIG. 2 shows the configuration of the data transmission side (main controller 10) in the circuit configuration within the expansion board EB.
0 indicates the side that sends the data received. The configuration shown in FIG. 2 writes data for forming a data frame signal to be transmitted into a transmission memory 44 (backed up by a backup power source) by a personal computer 30, and also reads out data written in the transmission memory 44 and arbitrarily reads the data written in the transmission memory 44. This frame signal is transmitted at an arbitrary period.

FIG. 3 shows data for forming a data frame signal stored in the transmission memory 44. That is, in FIG. 3, the first storage area contains a data frame signal A having a certain data pattern and non-transmission interval data (all bits are set to 1) for determining the non-transmission interval of this data frame signal A. 11 t) A is memorized and the second
The data frame signal B has a different content or data length from the data frame signal A, such as data DO (see FIG. 10), and a non-transmission interval that determines the non-transmission interval of this data frame signal B. Data B (with all bits set to 1) is stored, and similarly data frame signals C, D, E, etc. with data patterns different from these data frame signals A and B, and these data frame signals C, D , E, non-transmission interval data C, D, E, . . . are sequentially stored in each storage area in pairs. In this way, the transmission memory 44 stores a plurality of different data patterns and non-transmission interval data for one cycle each.

Therefore, when reading data stored in the transmission memory 44, for example, the start address for reading is designated as STA in FIG. 3, the end address is designated as EDA in FIG. By repeatedly specifying the address range many times, it is possible to send out the data frame signal A for multiple cycles as shown in FIG. 13, even though the stored data is for one cycle. can.

Similarly, the start address is set as shown in FIG.
By specifying the data frame signal A and the data frame signal B to the STA and specifying the end address to the EDB in FIG. 3, the data frame signal A and the data frame signal B can be transmitted alternately, as shown in FIG.

In FIG. 2, the register 45 and the three-state buffer 46 are configured to write transmission data from the personal computer 30 to the transmission memory 4. When writing, first, the personal computer 30 writes predetermined control data to the control bus CB. The write enable (write) signal W is output from the decoder 31, and the address of the transmission memory 44 is sent to the data bus DB. As a result, the address of the transmission memory 44 is written into the register 45. Next, predetermined control data is output from the personal computer 30 via the control bus CB to the decoder 3.
By outputting the OE1 signal and the OE2 signal from 1, the 3-state buffers 46 and 47 are enabled to output, and the transmission data to be written to the address previously output to the register 45 is sent to the data bus DB. As a result, the address latched in the register 45 is transferred to the 3-state buffer 4
6 to the address terminal of the transmitting memory 44, and the transmitting data is applied to the data terminal of the transmitting memory 44 via the tri-state buffer 47.
Data is written to. This kind of action,
Data as shown in FIG. 3 is written in the transmission memory 44 in advance by repeatedly executing the process while updating the addresses of the transmission memory one by one.

When reading the data written in the transmission memory 44, the start address and end address of the transmission memory 44 corresponding to the data frame signal to be transmitted by the personal computer 30 are set to the start address register 40 and the end address of the first stage, respectively. address register 36
write to. That is, the personal computer 30 first outputs the write signal WS of the start address register 40 from the decoder 31 and sends the start address to the data bus DB, thereby writing the start address into the start address register 40. Next, the personal computer 30 causes the decoder 31 to output the write signal WE of the end address register 36 to send the end address to the data bus DB, thereby writing the end address to the end address register 36.

The start address register 41 and end address register 37 in the second stage are the same as the start address register 40 and end address register 3 in the first stage.
6 is transferred, and this data transfer is performed by a data transfer control unit 50 composed of three flip-flops 32 to 34 and an AND gate 35.
It is controlled by the transfer enable signal CKE signal output from. The loadable counter 42 initially loads the start address written in the start address register 41, performs a counting operation from this initialized start address in synchronization with the clock signal CK, and transfers the count value via the three-state buffer 43. is applied to the address terminal of the transmission memory 44 and the comparison circuit 3.
Enter 8. The comparison circuit 38 compares the output of the end address register 37 and the output of the loadable counter 42, and when they match, sends a match signal SAME to the AND gate 3.
5 and a flip-flop 39. The flip-flop 39 captures the output SAME of the comparison circuit 38 at the falling edge of the system clock CK, and outputs an initial load signal LOD to the loadable counter 42.

[0040] When powering up, flip-flop 3
2. Since the start address register 40, end address register 37, and loadable counter 42 are reset by the reset signal RST, the comparison circuit 38 detects a match when the power is turned on, and outputs the match signal SAM.
Outputs E. Further, after turning on the power, if writing of the start address and end address to the start address register 40 and end address register 36 is completed as described above, the write signal WE of the end address register (WE signal is (to be output later) is detected by the flip-flop 32, and this detection signal is subjected to timing adjustment in the flip-flop 33 and then output to the AND gate. Therefore, the transfer enable signal CKE signal output from the AND gate 35 becomes H after the write signal WE of the end address register is output after the power is turned on. The data written in the register 36 is transferred to the second stage start address register 41 and end address register 37. Furthermore, the flip-flop 39 is configured to latch the output of the comparator circuit 38 at the falling edge of the clock signal CK, so that after the power is turned on, the data in the start address register 40 is transferred to the start address register 41. Up to this point, the data of the start address register 41, which is reset each time the clock signal CK falls, is initially loaded. However, when the data of the start address register 40 is transferred to the start address register 41, the data of the end address register 37 is also transferred to the end address register 37.
Since the data of 6 is transferred, the output of the comparator circuit 38 falls to L at the time of the data transfer. However, as described above, since the flip-flop 39 latches the output of the comparison circuit 38 at the falling edge of the clock signal CK, the initial load signal output from the flip-flop 39 is still As a result, the data in the start address register 41 is stored in the loadable counter 42 at the time of data transfer.
will be initially loaded.

After this initial loading is completed, the OE3 signal output from the decoder 31 is enabled by the personal computer 30. As a result, the count value of the loadable counter 42 is transferred to the transmission memory 4 via the 3-state buffer 43.
The transmission memory 44 starts reading data sequentially from the start address set in the start address register 41. The parallel data of the read data is converted into serial data by the P/S converter 48 and then transmitted to the main controller 100 via the transmitter 49. After this, the address of the transmission memory 44 is sequentially increased by +1 by the count operation synchronized with the clock signal CK of the loadable counter 42.
The count is counted up, and data reading from the address corresponding to the count value is executed. As this counting operation progresses, the output of the loadable counter will eventually match the end address set in the end address register 37. The comparison circuit 39 detects this coincidence and raises the output SAME to H at the time of detection of the coincidence. Therefore, the flip-flop 39 outputs the initial load signal LOD again, and the loadable counter 42 outputs the initial load signal LOD to the start address register 4.
The set start address of 1 will be initially loaded again. Therefore, after this, the loadable counter 42 again executes the counting operation from this start address up to the end address set in the end address register 37, and as a result, the same data frame signal as, for example, one cycle of data frame signal that was read last time is A data frame signal with the same content and sampling period will be output from the transmission memory 44. By repeating such operations, even though the transmission memory 44 only stores data for one cycle, the main controller 100 receives data frame signals for multiple cycles as shown in FIG. 13, for example. can be sent to.

When changing the contents of the transmission data, the settings of the end address register 36 and the start address register 40 can be changed by following the same procedure as described above. In this case, the end address register and the start address register are configured in two stages, and the end address register 37 and the start address register 41 in the second stage are set to the end address register 37 and the start address register 41 in the first stage only when the output SAME of the comparator circuit 38 matches. End address register 36
Since the setting data of the start address register 36 and start address register 40 are transferred, no matter when the setting data of the first stage end address register 36 and start address register 40 are changed, the main controller 100
The data frame signal transmitted to the data frame signal will no longer be interrupted in the middle of the data frame signal.

[0043] According to this configuration on the sending side, by appropriately changing the data content written in the transmission data and the start address and end address when reading, arbitrary data content and sampling period can be obtained with a small storage capacity. frame signals can be sent to the main controller.

FIG. 5 shows the configuration of the data receiving side (the side that receives data transmitted from the main controller 100) in the circuit configuration within the expansion board EB shown in FIG.

In FIG. 5, the main controller 100
The received frame from the receiving unit 61 is received by the receiving unit 61. The receiving section 61 inputs the received frame to the special code detecting section 62, shift register 67, and error detecting section 77, and forms and outputs a clock signal CK from the received frame signal.

The special code detection section 62 detects the first start code STI, second start code STO, stop code SP, etc. in the data frame signal shown in FIG. It outputs a start code detection signal STO and a stop code detection signal SP to each circuit, and also detects the end of the data frame signal and outputs an end detection signal FE.

The output point counter 63 calculates the data frame signal shown in FIG. 10 by counting the number of clock signals CK from when the second start code detection signal STO is input to when the stop code detection signal SP is input. The total number of actuators (number of output points) is counted by counting the number of bits of the output data DO to the actuators inside. In this case, the number of bits obtained by adding the number of bits of the output data DO to the number of bits of the stop code SP is counted, but the number of bits of the stop code SP is subtracted as appropriate by the output point counter 63 or the personal computer 30. It has become. The non-transmission period detection counter 64 is
By counting the number of clock signals CK from the input of the termination detection signal FE until the input of the first start code detection signal STI, the non-transmission interval t between the data frame signals (Fig. 11 (see).

Note that the measured values of the output point counter 63 and the non-transmission interval detection counter 64 can be determined by validating the output enable signals OE1 and OE2 output from the decoder 60 in response to a command from the personal computer 30. The information is input to the personal computer 30 via the .

In this case, the shift register 67 is an 8-bit shift register, receives the frame signal as serial data received by the receiving section 61 as input, and shifts this frame signal in synchronization with the clock signal CK. The comparison setting value register 65 is also composed of 8 bits, and operates to write data on the data bus DB when the output WP of the decoder 60 according to a command from the personal computer 30 is input.

The comparison circuit 66 compares the parallel output (8 bits) of the shift register 67 with the setting data (8 bits) of the comparison setting value register 65, and outputs a mismatch signal EXSUM when there is a mismatch in even one bit among the eight bits. Set to H.

The clock enable generation circuit 74 receives the second start code detection signal STO, stop signal detection signal SP, and clock signal CK, and generates a clock enable signal every 8 bits during the period from the STO signal to the SP signal. Output CKE1. That is, the actuator output data DO in the data frame signal of FIG.
Clock enable signal C every 8 bits only during the period of
Output KE1. In this case, appropriate timing adjustment is performed so that the clock enable signal CKE1 is not output during the period of the SP code. For example, if the SP code is 8 bits, shift register 6
7 is set to 16 bits, so that the SP code does not reach the 8-bit output at the subsequent stage where it is compared with the comparison setting value register 65.

Flip-flop 75 latches the second start code STO using clock signal CK, and outputs the latch output to gate 76 . That is, the detection output of the STO signal by the flip-flop 75 is output to the gate 76 every time a frame signal is received. The gate 76 also receives a write pulse signal W from the decoder 60.
P is input. Therefore, each time a frame signal is received from the gate 76, the comparison setting value register 65
A signal is output every time the setting data is rewritten.

Gates 68-72 and flip-flop 7
The configuration according to No. 3 is a configuration for holding the mismatch signal EXSUM when the mismatch signal EXSUM is output even once in one data frame signal. If there is a CHKEND signal, a CHKEND signal is output. This CHKEND
As described above, the signal is reset each time a frame signal is received by the gate 76 and each time the setting data of the comparison setting value register 65 is rewritten, so it changes in synchronization with the reception cycle of one frame signal. This is a signal to

The error detection section 77 detects a transmission error in the data frame signal received by the reception section 61 by performing a CRC check or the like, and sets the error detection signal DTERR to H when an error is detected. Gate 78 receives error detection signal D
The inverted signal of TERR and the frame end signal FE are ANDed and the AND result is output. Therefore, gate 7
The output of 8 becomes H when no error is detected and the frame end signal FE is input.

Therefore, the CHKEND signal is incorporated into the configuration of gates 79 to 82, flip-flop 83, and OR gate 85 when no transmission error is detected during one data frame. Furthermore, since the output CHGDT of the flip-flop 83 is reset by the write pulse signal WP, the output CHGDT of the flip-flop 83 corresponds to multiple cycles of the frame signal until the setting data of the comparison setting value register 65 is rewritten. During the period, when even one bit of the frame signal does not match the setting data of the comparison setting value register 65 when no transmission error occurs, the signal becomes H. This mismatch signal CHGDT is the output BE of the decoder 60.
By enabling N, the data is input to the personal computer 30 via the three-state buffer 84 and can be observed on the personal computer 30.

Next, a procedure for testing various functions of the main controller 100 using the testing apparatus shown in FIGS. 2 and 5 will be explained for each testing item.

(1) Inspection of the data length automatic determination function and the sampling time automatic determination function As mentioned above, the main controller 100 turned off all the actuator control data DO in the data frame signal shown in FIG. 10 when the power was turned on. (The length m of the DO is longer than the total number of possible actuators) An initial frame signal as shown in Fig. 6 is sent to the node, and the length of the actuator data in the received initial frame signal and the actuator in the transmitted initial frame signal are The number of output points (total number of actuators) is automatically detected from the difference in data length, and the number of input points (total number of sensors) is automatically detected from the length of sensor data in the received initial frame signal. ing.

That is, the initial frame signal, like the data frame signal shown in FIG. 10, includes the first start code STI, second start code STO, output point detection data DO', stop code SP, CRC code, and E.
It consists of RR code. However, the output point number detection data DO' consists of m-bit "0" data so that the actuator does not operate at each node. Here, m is set to a number of bits greater than the number of all actuators used in this system.

This initial frame signal, like the data frame signal explained earlier, is transmitted from node 10-1 to node 10-
2→node 10-3→node 10-4→10-5, the output point detection data DO' in the initial frame signal is allocated to the corresponding node, and the output point detection data DO' obtained at each node is The detection data of the sensor group is incorporated into the same initial frame signal. That is, each node 1
In 0-1, 10-2, ...10-N, sensor groups 1-1, 1-2, ... are connected to the node after the first start code STI of the input initial frame signal.
Data DI of 1-N is added, and data for actuator groups 2-1, 2-2, . . . 2-N connected to the node is extracted from data DO following the second start code STO. And node 10-1,1
The initial frame signal output from the node 10-N after passing through nodes 0-2, . . . 10-(N-1) is input to the main controller 100 in a state as shown in FIG. The main controller 100 counts the number of bits LI of data DI following the first start code STI in the input initial frame signal, uses this count result LI as the number of input points, and The number of bits l of the data DO following the start code STO of 2 is counted, and this count value l is calculated as the number of bits m of the output point detection data DO' at the time of initial frame transmission shown in FIG.
The subtraction result G (=ml) is used as the output point number.

Then, the main controller 100 calculates the length Ld of the actuator drive data DO in the normal data frame signal shown in FIG. 10 from the calculated output point number G.
At the same time, the transmission period T (sampling time) of the data frame signal shown in FIG. 10 is determined according to the detected number of input points and number of output points (see FIG. 11).
.

In detecting these functions, the start address and end address of the transmission memory 44 shown in FIG. 2 are set appropriately by the personal computer 30, and the initial frame signal to be received by the main controller shown in FIG. It is periodically transmitted from the transmission memory 44 to the main controller 100 via the transmission section 49. Of course, a plurality of patterns of initial frame signals to be received by the main controller for this inspection as shown in FIG. 7 are written in advance in the transmission memory 44.

When the main controller 100 receives this initial frame signal, it automatically calculates the number of input/output points corresponding to the received initial frame signal using the above-mentioned function of detecting the number of input/output points. Note that when calculating the number of output points, the length m of the actuator data DO' in the transmission initial frame signal shown in FIG. 6 is required;
As described above, is fixedly set in the main controller 100 to an appropriate value m that is greater than the number of all actuators used in this system.

Therefore, the main controller 100 automatically determines the data length Ld (see FIG. 10) in the data frame signal according to the detected number of output points, and also determines the sampling period T according to the detected number of input/output points. A data frame signal of long length and sampling period is to be sent to the node. This transmission data is sent to the receiving section 6 of the receiving side configuration shown in FIG. 5 of the inspection device 20.
1 is received. The output point counter 63 counts the number of output data to all actuators in the data frame signal received by the above-described operation, and reports this to the personal computer. Further, the non-transmission interval detection counter 64 measures the interval (t in FIG. 11) between the received data frame signals, and reports this timing output to the personal computer 30. By determining these outputs from the personal computer 30, the operator checks whether the automatic data length determination function and the automatic sampling time determination function of the main controller 100 are operating normally. Such a test is performed over a plurality of initial frame signals having different data contents.

(2) Verifying the number of input/output points multiple times In the main controller 100, as described above, the number of input/output points detected based on the output of the initial frame signal at the time of power-up is repeated a predetermined number of times in succession. It is used as the true number of input/output points only when N is the same. However, in this case, if a transmission error occurs in the received initial frame signal, it is ignored and not included in the number of times of verification. Furthermore, in this function, the main controller 100 sends out the initial frame signal until the true number of input/output points is determined through the plurality of verifications. When the true number of input/output points is determined, the data length and sampling period are determined based on the determined true number of input/output points, and a data frame signal having the determined data length and sampling period is transmitted.

To test this function of the main controller 100, it is of course necessary to transmit an initial frame signal as shown in FIG. 7, as in the test (1) above. 4, two different initial frame signals (more precisely, initial frame signals in which the length of input data and the length of output data in the initial frame signal are different) are alternately transmitted to the main controller 1.
The start address and end address of the transmission memory 44 in FIG. 2 are appropriately set by the personal computer 30 so that the signal is received at 00. Of course, it is necessary to store data in an appropriate storage area of the transmission memory 44 so that data as shown in FIG. 4 is output. Further, it is not necessarily necessary to alternate, and it is sufficient that initial frame signals with different data contents are sent out at a cycle number that is less than the number of times of matching N. In addition, in order to test the function in the event of an error, data that will cause an error to occur is appropriately mixed into the initial frame signal.

Therefore, when the main controller 100 is powered on while such an initial frame signal is being sent to the main controller 100, the main controller 100 sends out the initial frame signal and tries to detect the number of input/output points. However, at this time, as described above, initial frame signals having different lengths of input data and different lengths of output data are alternately inputted from the transmitting side of the inspection apparatus, so that the main controller 100 Since the true number of input/output points cannot be determined forever, the initial frame signal is continued to be transmitted instead of the data frame signal.

[0067] This transmission initial frame signal is transmitted to the inspection device 2.
The received signal is received by the receiving section 61 having the receiving side configuration shown in FIG. The output point counter 63 counts the number of output data to all actuators in the data frame signal received by the above-described operation, and reports this to the personal computer. Further, the non-transmission interval detection counter 64 measures the interval (t in FIG. 11) between the received data frame signals, and reports this timing output to the personal computer 30. The operator verifies that the multiple verification function of the input/output points of the main controller 100 is operating normally by confirming that the initial frame signal rather than the data frame signal is input from the output of the personal computer 30. . That is, since the initial frame signal and the data frame signal usually have different sampling periods, by looking at the output of the non-transmission period detection counter 64, it is possible to confirm which frame signal is being received.

Furthermore, as described above, since the data length m (see FIG. 6) of the initial frame signal is set longer than the data length Ld (see FIG. 10) of the data frame signal,
It is also possible to confirm which frame signal is being received by identifying the output of the output point counter 63.

(3) Transmission data frame signal creation function The main controller 100 is connected to the host controller 200.
Based on the actuator control data sent from the node, a data frame signal including the designated actuator control data shown in FIG. 10 is automatically formed and sent to the node.

In testing this function, the same data pattern is repeated in units of 8 bits as actuator control data specified by the host controller 200. For example, if the data pattern in units of 8 bits is "01101001", the host controller 200 specifies actuator control data such that this data pattern is repeated. Based on this designation, the main controller 100 forms a data frame signal shown in FIG. 10 consisting of the control data of the designated actuator and special codes such as STI code and STO code, and this data frame signal is transmitted at a predetermined sampling period. Send by. On the other hand, the computer 30 inputs the same data pattern (in this case "01101001") as the 8-bit data pattern specified by the host controller 200 into the comparison setting register 65 on the receiving side of the inspection device 20 shown in FIG. It is written in advance before receiving the data frame signal from 100. The data frame signal transmitted from the main controller 100 is received by the receiving section 61 and input to the shift register 67 or the like. The shift register 67 sequentially shifts the input data according to a clock signal. The parallel 8-bit output of this shift register is sequentially compared in 8-bit units with the setting data of the comparison setting register 65 in the comparison circuit 66.
Output CKE of the clock signal enable generation circuit 74
1 signal, the output EXSUM of the comparator circuit is taken in only in the actuator data section of the data frame signal. Therefore, as described above, by observing the mismatch signal CHGDT output from the flip-flop 83 on the personal computer 30, the comparison setting value register 6
During multiple periods of the data frame signal until the setting data in No. 5 is changed, when no transmission error has occurred, even one bit of mismatch occurs in the actuator control data with the setting data in the comparison setting value register 65. If so, this can be detected reliably.

In this way, the main controller 10
0's transmission data frame signal generation function is checked.

By the way, the host controller 200
The 8-bit data pattern specified by is 1 bit to 7 bits.
A data pattern is adopted that does not match the original data pattern even if the bits are shifted (rotated) to the right or left.

For example, if the data pattern "00111001" is shifted one bit to the right, it becomes "10011".
100”, and if 2 bits are added to the right, it becomes “010011”.
10”, and if 3 bits are moved to the right, it becomes “0010011”.
1”, and if shifted 4 bits to the right, it becomes “10010”.
011", and if shifted 5 bits to the right, it becomes "110".
01001", and if shifted 6 bits to the right, it becomes "1
1100100", and if shifted 7 bits to the right, it becomes "01110010", which will be different from the original data pattern even if a bit shift occurs in the serial/parallel conversion process in the shift register in Figure 5,
Bit misalignment can be determined reliably. By the way, ``
If a data pattern such as "01010101" is adopted, even if it is shifted to the right or left by 2 bits, it will match the original data pattern, and a bit shift cannot be determined.

That is, when considering an 8-bit data pattern, the original data pattern is D, the data pattern shifted by 1 bit to the right is D1, and
Assuming that the data patterns shifted by 7 bits are D2 to D7, data patterns satisfying the following are adopted: D≠D1 D≠D2 D≠D3 D≠D4 D≠D5 D≠D6 D≠D7 D=D8.

Note that this data pattern may be used not only for checking the output data string but also for checking error numbers (data indicating the position where an error has occurred), disconnection numbers (data indicating the position where the disconnection has occurred), and the like.

(4) Inspecting the sensor data multiple verification function The main controller 100 verifies the sensor data in the periodically received data frame signal multiple times, and determines that the sensor data is true when it matches a predetermined number of times n consecutively. It has a function to be adopted as sensor data. However, if a transmission error occurs in the received data frame signal, it is ignored and not included in the number of times of verification.

In testing this function, for example, as shown in FIG. 8, a plurality of data frame signals having different sensor data contents are successively transmitted, and one group of data consisting of these plurality of data frame signals is The computer 30 is configured so that the frame signal is repeatedly sent out.
The start address and end address of the transmission memory 44 shown in FIG. 2 are set as appropriate. Of course, data for that purpose is stored in an appropriate storage area of the transmission memory 44 so that data as shown in FIG. 8 is output. However, the plurality of data frame signals are set so that the number of input and output points is the same. Further, data that may cause an error is appropriately mixed into the plurality of data frame signals in order to test the function in the event that the error occurs.

As described above, the main controller 100 transmits the sensor data in the received data frame signal to the host controller 200, and the sensor data in the data frame signal can be observed by the host controller 200. I can do it.

Therefore, the main controller 100 receives the data frame signal sent from the transmission side of the inspection device 20, and while checking the sensor data on the host controller 200, the set value n of the number of verifications of the multiple verification function is adjusted as appropriate. By changing n (n is changed by operating a switch attached to the main controller), it is confirmed whether the sensor data multiple verification function is operating normally.

For example, when a plurality of data frame signals including sensor data with different data contents as shown in FIG. When E2 is not fixed to 0 or 1 and is in an undefined state, and the other bits are fixed to 0, it is determined that the sensor data multiple verification function is operating normally. Similarly, if n=1 is set, the least significant bit E0 is fixed to 1, the E1 and E2 bits are in an undefined state, and the other bits are fixed to 0, and the above sensor data multiple verification function is normal. It is determined that the system is working properly. Also, if we set n=3, E2
bit is fixed to 1, the E0 and E1 bits are fixed to the initial value of the reception memory (memory that stores received data) in the main controller 100, and the other bits are fixed to 0. Determine that the multiple verification function is working properly.

[0081] In this way, the multiple verification function of sensor data is tested.

Note that this invention can be modified as appropriate; for example, the circuit configurations shown in FIGS. 2 and 5 may be modified to other circuits as long as they achieve the same function. good.

[0083]

[Effect of the invention] As explained above, according to the first invention,
The sampling time and data length automatic creation function of the main controller can be easily and quickly inspected. According to the second invention, the data frame signal creation function of the main controller can be tested quickly and accurately. In the third invention, various frame signals to be transmitted to the main controller can be transmitted at high speed with a small storage capacity, and frame signals having arbitrary sampling periods and arbitrary data contents can be easily transmitted. In the fourth invention,
Even if a data string is erroneously shifted due to malfunction of a circuit such as a serial-to-parallel converter or a parallel-to-serial converter, this can be easily detected. In the fifth invention, the input/output point checking function of the main controller can be easily, quickly and reliably tested. In the sixth invention, the input data verification function of the main controller can be easily, quickly and reliably tested.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the invention.

FIG. 2 is a block circuit diagram showing an example of the configuration of the transmitting side of the inspection device.

FIG. 3 is a diagram showing an example of storage contents of a transmission memory.

FIG. 4 is a diagram showing an example of a transmitted data frame signal sequence.

FIG. 5 is a block circuit diagram showing an example of the configuration of the receiving side of the inspection device.

FIG. 6 is a diagram showing an initial frame signal transmitted from the main controller.

FIG. 7 is a diagram showing an initial frame signal received by the main controller.

FIG. 8 is a diagram showing an example of data used in multiple verification function tests of sensor data.

FIG. 9 is a diagram showing the overall configuration of a system to which the present invention is applied.

FIG. 10 is a diagram showing a propagation mode of a data frame signal.

[Figure 11] Diagram showing sampling period etc.

FIG. 12 is a diagram showing a prior art.

FIG. 13 is a diagram showing a propagation mode of a data frame signal.

[Explanation of symbols]

1...Sensor group 2...Actuator group 10...Node 20...Inspection device 30...Personal computer 100...Main controller 200...Host controller

Claims (7)

[Claims] 1. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller sends first and second special codes and output data to the actuators. Each node adds the input data from the sensor connected to the node after the first special code, and sends the output data to the actuator connected to the node at a predetermined period. Second
At the same time, the main controller sends out an initial frame signal including the first and second special codes and data for detecting the number of actuators before sending out the data frame signal, and detecting the total number of bits of the sensor and the total number of bits of the actuator based on the lengths of the input data and the output data in the initial frame signal received via a plurality of nodes; The series controller has an automatic sampling time determination function that determines the transmission interval of the data frame signal according to the data frame signal, and an automatic frame length determination function that automatically determines the length of the data frame signal according to the total number of bits of the detected actuator. In the control device, a transmitting means for transmitting to the main controller an initial frame signal to be received by the main controller by varying the length of the input data and output data in the initial frame signal, and receiving means for receiving a data frame signal formed and transmitted by the main controller based on the initial frame signal; and counting the total number of bits of the output data in the data frame signal based on the output of the receiving means. an output point counter, and a timer for timing the transmission interval of the data frame signal based on the output of the receiving means, and a sampling time of the main controller based on the output of the output point counter and the timer. A testing device for a serial control device that tests the automatic determination function and automatic frame length determination function. 2. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller sends out a data frame signal containing output data to the actuator at a predetermined period. Each node adds input data from a sensor connected to the node to a data frame signal and extracts output data to an actuator connected to the node from the data frame signal, and the main controller In the serial control device, the output data portion specified by the host controller is configured to repeat the same data pattern every predetermined number of bits. At the same time, a first register having the same number of bits as the predetermined number of bits is set with the same data pattern as the output data specified by the host controller, and data formed and transmitted by the main controller according to the data specification by the host controller. a receiving means for receiving a frame signal; a second register for latching the output data portion of the receiving means for the predetermined number of bits; and a comparing means for comparing the outputs of the first and second registers; an error detecting means for detecting a data error in a data frame signal received by the receiving means; and a main controller operating normally when the error detecting means does not output a detection signal and the comparing means outputs a coincidence signal. An inspection device for a series control device, comprising: detection means for detecting that 3. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller sends out a data frame signal containing output data to the actuator at a predetermined period. In the serial control device, each node adds input data from a sensor connected to the node to a data frame signal, and extracts output data to an actuator connected to the node from the data frame signal, a memory means for storing a plurality of types of data for one cycle of the data frame signal including non-transmission interval data; a start address register for latching a read start address of the memory means; and a start address register for latching a read end address of the memory means. The outputs of the end address register and the start address register are initially loaded, and a counting operation from the initial loading is performed by counting a predetermined clock signal, and this count output is stored in the memory means as a read address of the memory means. a counter means for outputting an output, a comparing means for comparing an output of the counter means with an output of the end address register and initially loading an output of the start address register into the counter means each time the comparison result matches, and the memory means. control means for outputting a control signal for controlling readout of the data frame signal and setting the readout start address and readout end address in the start address register and the end address register; An inspection device for a serial inspection device, characterized in that various inspections of the main controller are performed by transmitting data to the main controller. 4. The start address register and the end address register each have a two-stage configuration, and the second stage start address register and end address register are configured as follows:
4. The test device for a serial test device according to claim 3, wherein each latch data of a start address register and an end address register of the first stage is latched when a match signal is output from the comparison means. 5. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller sends out a data frame signal containing output data to the actuator at a predetermined period. In the serial control device, each node adds input data from a sensor connected to the node to a data frame signal, and extracts output data to an actuator connected to the node from the data frame signal, When inspecting the main controller, a data string in a data frame signal received by or transmitted from the main controller is made such that a basic data pattern is repeated for every predetermined bit, and the basic data pattern is 1. A test device for a serial test device, characterized in that a data string that does not match the original data string even if the data is rotated from 1 to the predetermined bit minus 1 bit lower or higher is adopted. 6. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller transmits first and second special codes and output data to the actuators. Each node adds the input data from the sensor connected to the node after the first special code, and sends the output data to the actuator connected to the node at a predetermined period. Second
The main controller periodically sends out an initial frame signal including the first and second special codes and data for detecting the number of actuators before sending out the data frame signal. detecting the total number of bits of the sensor and the total number of bits of the actuator based on the lengths of the input data and the output data in the initial frame signal received via the plurality of nodes; In a serial control device, a non-transmission interval is adopted as a true detection value when the detection result matches a plurality of consecutive times, and the transmission interval of the data frame signal is determined according to the adopted detection value. one of said initial frame signals containing data;
a memory means for storing a plurality of types of data for a cycle; a start address register for setting a read start address of the memory means; an end address register for latching a read end address of the memory means; a counter means that performs a counting operation from the initial loading by counting a predetermined clock signal, and outputs the count output to the memory means as a read address of the memory means; Comparing means for comparing the outputs of the end address registers and initially loading the output of the start address register into the counter means each time the comparison results match, and outputting a control signal for controlling readout of the memory means; The read start address and the read end address are set in the start address register and the end address so that an initial frame signal having at least two different input data lengths and output data lengths to be received by the main controller is output every one or more cycles. a transmitting device having a control means for setting in a register, and a transmitting means for transmitting the output of the memory means to the main controller, and further includes a frame signal that the main controller generates based on a frame signal transmitted by the transmitting device. a receiving means for receiving the frame signal transmitted by the receiving means; an output point counter for counting the total number of bits of the output data in the frame signal based on the output of the receiving means; a receiving device having a timer for timing the sending interval of the data frame signal, and all bits of the actuator and sensor are checked by the main controller multiple times based on the output of the output point counter or the timer. An inspection device for a serial control device, characterized in that it inspects a number detection function. 7. A plurality of nodes connected to one or more sensors and actuators are connected in a loop including a main controller, and the main controller transmits first and second special codes and output data to the actuators. Each node adds the input data from the sensor connected to the node after the first special code, and sends the output data to the actuator connected to the node at a predetermined period. Second
At the same time, when the input data of the sensor in the data frame signals received via the plurality of nodes match n times in a row, the main controller extracts the special code from the end of the special code. In a serial control device having an input data matching function, one of the data frame signals including non-transmission interval data is used.
A memory means for storing a plurality of types of data corresponding to a cycle, a start address register for latching a read start address of the memory means, an end address register for latching a read end address of the memory means, and an output of the start address register. a counter means that is initially loaded, performs a counting operation from the initial load by counting a predetermined clock signal, and outputs the count output to the memory means as a read address of the memory means; and an output of the counter means. Comparing means for comparing the outputs of the end address registers and initially loading the outputs of the start address registers into the counter means each time the comparison results match, and a plurality of different input data contents when reading from the memory means control means for setting the read start address and read end address in the start address register and end address register so that the data frame signals having the data frame signal are continuously transmitted; and a transmitter for transmitting the output of the memory means to the main controller. and a transmitting device having a transmitting device, which receives a transmission data frame signal from the transmitting device and inspects the input data matching function while varying the number of matchings n of the input data matching function in the main controller. An inspection device for a series control device characterized by the following.