JPH0568043A - Check device for series controller - Google Patents

Abstract

PURPOSE:To simply and surely check an input data collation function or the like while an input data transmission priority function of a main controller (MC) is kept. CONSTITUTION:The check device 20 having a similar function to that of plural nodes connecting in a loop and implementing various checks for an MC 100 is provided with a personal computer 30 and an extension board EB having a reception function receiving transmission data from the MC 100 for implementing various checks and a transmission function to the MC 100 and mounted to the personal computer 30. In the input data collation function check of the MC 100, the check device 20 consecutively sends plural data frame signals whose data contents differ generated by the personal computer, receives the result of collation of the MC 100 to check the function by varying the number N of times of collation of the collation function. In the case of read of data in the check device, when the transmission of plural data frame signals is finished and the reception for setting the number of times is not finished, data for non-transmission blocks are kept being sent till the reception for the setting number of times is finished to avoid interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is suitable for a centralized control system for various machines such as a press, a machine tool, a construction machine, a ship, and an aircraft, and an unmanned transfer apparatus, an unmanned warehouse, etc. With regard to the above, in particular, a main controller and a plurality of nodes are connected in series in a closed loop, and each node is connected to one or a plurality of sensors that output data and one or a plurality of actuators that input data. In a control device, the present invention relates to an inspection device of a serial control device for inspecting various functions of the main controller.

[0002]

2. Description of the Related Art When centrally managing presses, machine tools, construction machines, ships, aircraft, unmanned conveyors, unmanned warehouses, etc.,
A large number of sensors for detecting the state of each part of the device and a large number of actuators for controlling the state of each part of the device are required.
The number of sensors and actuators is, for example, 3000 or more in the case of considering a press, and may be larger in other devices.

As a centralized management system for centrally managing this type of device, a serial control device as shown in FIG. 19 has already been filed by the present applicant. The main feature of this serial control device is that the concept of assigning an address to each node is abandoned even though the nodes are connected in series, and each node is identified by the order of its connection. This is because it is unnecessary and eliminates the time delay associated with address processing, and the node configuration can be greatly simplified.

In the serial controller of FIG. 19, sensor groups 1-1, 1-2, ... 1-N are arranged in each part of the machine and detect the state of each part of the machine. The actuator groups 2-1, 2-2, ... 2-N are arranged in various parts of the machine,
It drives various parts of the machine. These sensor groups 1-
N and the actuator group 2-N are node 10 respectively.
-N (N = 1 to N), and these node 1
0-1 to 10-N are connected in series in a loop including the main controller 100. Main controller 1
00 mainly controls data exchange with a plurality of connected nodes 10-1 to 10-N. The host controller 200 centrally controls a machine (press or the like) on which this system is mounted, and is a higher-level controller of the main controller 100. Also, the host controller 200 sends data to be sent to each node to the main controller 100, and also receives data received from each node via the main controller 100.

FIG. 20 shows a frame structure of a data signal used in the system when the number N of nodes is 5, and this data frame signal is sent from the main controller 100 to the nodes 10-1 and 10. -2,
...... Main controller 100 after passing through 10-N
Returned to. Note that FIG. 1A shows the main controller 1
The data frame signal immediately after being output from 00 is shown in nodes (b), (c), (d) and (e) of FIG.
The data frame signals output from 0-2, 10-3, and 10-4 are input to the main controller 100 by feedback (in the case of N = 5, the signal output from the node 10-5 in FIG. Signals) respectively.

The contents of each signal in the frame structure of FIG. 20 are as follows.

STI: Input data (sensor data) DI
Start code DI indicating the start position of the input data (sensor data) DIq; input data from the sensor connected to the q-th node STO; second position indicating the start position of the output data (actuator drive data) Start code DO; Output data (actuator drive data) DOq; Output data SP to the actuator connected to the qth node SP; Stop code CRC indicating the end position of the data string CRC; CRC code for CRC check ERR; The presence / absence of an error, a code indicating an error content, and an error position, each node 10-1 to 10-N shown in FIG.
As shown in 0 (b) to (f), the start code STI
Between the start code STO and the start code STO, the detection data DIq of the sensor 1 connected to the node is added, and after the start code STO, the output data DOq to the actuator 2 connected to the node is extracted.

Therefore, in this system, the main controller 100 sends to the node 10-1 as shown in FIG.
If a data frame signal including the actuator control data DO as shown in (a) is transmitted, this data frame signal becomes node 10-1 → node 10-2 → node 10
-3 → node 10-4 → 10-5 is sequentially propagated to allocate the actuator control data DO in the data frame signal to the corresponding node, and the detection data of the sensor group obtained at each node. Are taken into the same data frame signal. As a result, when the data frame signal is fed back to the main controller 100, as shown in FIG. 20 (f), all the actuator control data DO disappears and the detection data of the sensor group is included in the same frame signal. It will be.

In such a configuration, the main controller 100 mainly has the functions listed below in order to automatically execute the transmission / reception operation.

(1) Automatic data length determination function: When the power is turned on, all the actuator control data DO in the data frame signal is turned off as shown in FIG. 21 (DO
Is longer than the total number of possible actuators) The initial frame signal is sent to the node, the length m of the actuator data in the transmitted initial frame signal and the length L1 of the actuator data in the received initial frame signal (Fig. 22), the number of output points (the total number of actuators) is automatically detected from the difference (m-L1), and the data length Ld (FIG.
Refer)). Further, the number of input points (the total number of sensors) is automatically detected from the length l of the sensor data in the received initial frame signal.

(2) Automatic sampling time determination function ...
The number of input points (the total number of sensors) is automatically detected from the length 1 of the sensor data in the received initial frame signal, and the transmission cycle of the data frame signal is determined according to the detected value of the input points and the detected number of output points. T (sampling time) is determined (see FIG. 22). (3) Multiple input / output point matching function: The initial frame is sent many times in a predetermined cycle, and the detected input / output points are consecutively the same for a predetermined number of times to be adopted as the true input / output points. However, if a transmission error occurs in the received initial frame signal, it is ignored and it is not included in the number of times at the time of the collation.

(4) Transmission data frame signal generation function ...
After the transmission of the initial frame signal, (1) to
When the data length Ld and the sampling time T are determined using the function (3), the data frame signal shown in FIG. 20 is automatically formed based on the actuator control data sent from the host controller 200. Then
This is sent to the node at a predetermined sampling period T.

(5) Multiple collation function of sensor data: When the data frame signal is transmitted, the data frame signal in which the sensor data is inserted is transmitted from the node. The sensor in the received data frame signal is transmitted. The data is continuously adopted the same number of times a predetermined number of times before being adopted as true sensor data. However, if a transmission error has occurred in the received data frame signal, it is ignored, and it is not included in the number of times of the above collation.

Main controller 1 having such a function
00 is configured as shown in FIG.

That is, in this case, the main controller 1
The transmission / reception data memory 1 shares a memory for storing the transmission data frame signal and a memory for storing the reception data frame signal. That is, the transmission / reception data memory 11 is a dual port memory (DPM), one port is connected to the bus of the host controller 200, and the other port is connected to the transmission device 12 of the main controller 100.
It is also shared by the receiver 13 and the transmission / reception data memory 11 stores the transmission data to the node and the reception data from the node. The transmission data and the reception data are stored in different storage areas of the transmission / reception data memory 11 by distinguishing designation of the most significant 1 bit of the address bus.

When transmitting, the host controller 20
0 stores the required actuator drive data in the transmission / reception data memory 11. The transmitter 12 forms a data frame signal shown in FIG. 20 by adding a start code or the like based on the transmission data stored in the transmission / reception data memory 11, and transmits this to the node at a predetermined sampling period T.

In the case of reception, the reception data frame signal from the node is temporarily stored in the reception memory 14 in the reception device 13, and the stored data is collated by the reception device processing circuit 15 a plurality of times as described above. After the error check processing is added, serial / parallel conversion is performed by the S / P converter and then stored in the transmission / reception data memory 11.

The reception memory 14 is a memory having a data width of 1 bit, and the transmission / reception data memory 11 is a memory having a data width of 8 bits. The output data of the reception memory 14 is S
Since / P conversion is performed and stored in the transmission / reception data memory 11,
The data of the lower 3 bits of the address bus ABR of the receiving memory 14 corresponds to 1 byte.
The 4th bit from the least significant bit of is equivalent to the least significant bit of the transmission / reception data memory 11.

In such a configuration, one port of the transmission / reception data memory 11 is shared by the transmission side and the reception side of the main controller, so that the data transmission timing and the data reception timing do not overlap in each node. The data transmission interval (sampling time) is determined in consideration of the data propagation delay time. However, in case an access collision occurs, the transmission side (transmission / reception data memory 1
The access of reading data from 1) is prioritized to the receiving side (writing of data to the transmission / reception data memory 11).

That is, in the memory control circuit 17, the circuit is configured with the following priority logic.

For the access to the transmission / reception data memory 11, the transmission process is prioritized.

Send / receive data memory 1 for reception processing
The transmission / reception data memory 11 is accessed after confirming that the data bus 1 is empty.

An interrupt signal INT from the transmission device 12 (each time data is read from the transmission / reception data memory 11 in synchronization with the sampling cycle T of transmission) during reception processing (writing to the transmission / reception data memory 11). (INT is output) is input, the reception process is stopped, and the process is restarted from the beginning after the interruption is completed.

By the way, the main controller 10
As a device for inspecting various functions of No. 0 when a failure occurs or at the time of shipment inspection, the present inventor applied for “inspection device for serial controller” as of December 28, 1990 (Japanese Patent Application No. -408756).

According to the invention of this application, as shown in FIG. 25, the inspection device 20 is connected to the main controller 100, and the inspection device 20 has a function of receiving transmission data from the main controller 100 and the main controller 1.
00 is equipped with a function of transmitting the received data of any main controller 100, etc.
A plurality of nodes 10-1 to 10 of the serial controller shown in FIG.
The part composed of -N is substituted.

In the inspection using the inspection device 20, for example, the inspection device 20 sends data for checking the various functions of the main controller 100 to the main controller 100, and the output of the main controller 100 upon receiving the data. For example, the host controller 20
By checking with 0, it is confirmed whether the various receiving functions of the main controller 100 are operating normally, and the host controller 200 designates appropriate control data of the actuator, and the main controller 10 is designated by this designation.
Whether the transmission function of the main controller 100 is operating normally by receiving the data frame signal formed by 0 in the inspection device 20 and confirming whether this received data matches the designated data in the host controller 200. Inspect whether or not.

For example, in checking the multiple collation function of the sensor data executed by the reception processing circuit 15 of the receiving device 13 of the main controller 100, a plurality of sensors having different sensor data contents as shown in FIG. PC 3 so that the data frame signals of are continuously transmitted, and a group of data frame signals composed of the plurality of data frame signals are repeatedly transmitted.
The transmission data from the inspection device 20 is appropriately set by 0. However, the plurality of data frame signals are set so that the number of input / output points is the same. In addition, in order to inspect the function in the case where the error occurs, data that causes an error is appropriately mixed in the plurality of data frame signals.

In the main controller 100, the sensor data in the received data frame signal is transmitted to the host controller 200, and the sensor data in the data frame signal can be observed by the host controller 200.

Therefore, the main controller 100 receives the data frame signal sent from the transmitting side of the inspection device 20, and the host controller 200 checks the sensor data and appropriately sets the setting value N of the number of times of verification of the multiple-time verification function. By changing (N is changed by operating the switch attached to the main controller), it is confirmed whether the multiple collation function of the sensor data is operating normally.

For example, when a plurality of data frame signals including sensor data having different data contents as shown in FIG. 26 are continuously input, if N = 0 is set (no collation), the lower 3 bits E0 to E0 are set. When E2 is not fixed to 0 or 1 and is in an indefinite state and the other bits are fixed to 0, it is determined that the above-mentioned multiple collation function of sensor data is operating normally. Similarly, when N = 1 is set, the least significant bit E0 is fixed to 1, the E1 and E2 bits are in an undefined state, and the other bits are fixed to 0, the above-mentioned multiple collation function of sensor data is normal. It is determined to be working. If N = 3 is set, E
The 2 bits are fixed to 1, the E0 and E1 bits are fixed to the initial value of the reception memory (memory for storing reception data) in the main controller 100, and the other bits are 0.
When it is fixed to, it is judged that the above-mentioned multiple collation function of the sensor data is operating normally.

In this way, the verification function of the sensor data is checked a plurality of times.

[0032]

By the way, when data is transmitted from the inspection device 20 to the main controller 100 and the reception processing contents of the main controller 100 based on the transmission data are to be confirmed by the host controller 200, At this time, since the transmitter 12 of the main controller 100 is also operating naturally, the transmitter 12 tries to perform the transmission operation periodically corresponding to the sampling time T. Therefore, the transmission interval of the data transmitted from the inspection device 20 is appropriately set. The main controller 100
There is a possibility that a collision will occur in the access to the transmission / reception data memory 11 of the above. Since one port of the transmission / reception data memory 11 is shared by the transmission device 12 and the reception device 13 of the main controller 100 as described above,
The transmission side priority logic described above is incorporated.

Therefore, during the inspection using the inspection device 20, an interrupt INT is generated from the transmission side during the reception process (writing to the transmission / reception data memory 11), and the reception process is interrupted midway. Sometimes it was impossible to inspect the controller.

In particular, in the above-mentioned multiple verification function inspection of the sensor data, as shown in FIG. 25, a plurality of data frame signals having different sensor data contents must be continuously transmitted, so that However, there was a problem that if the data was interrupted on the way, erroneous inspection would be performed.

For this reason, in the conventional case, when the main controller 100 concerning the receiving process is inspected, the transmitting side priority logic of the main controller 100 is changed and the transmission / reception data memory 11 is occupied by the receiving device 13 only. I was trying to do a reception inspection.

However, in such a case, there are problems in the inspection itself and in that it takes time and effort to change the circuit.

During the inspection of the main controller 100, the address bus ABR of the reception memory 14, the address bus ABM of the transmission device 12 and the reception device 13 of the transmission / reception data memory 11 and the transmission / reception data memory shown in FIG. There is a test of the address bus ABP on the side of the host controller 200 of No. 11, but in order to perform this test easily, conventionally, the same data is sent from the test device 20 in 1-byte units, and all the storage areas of the transmission / reception data memory 11 are sent. The address of each memory is updated so that all the same data is written in byte units, and then the host controller 200 confirms whether or not the same data is written in all the addresses of the transmission / reception data memory 11 to check the memory Whether the address buses ABR, ABM and ABP are normal It had to be 査.

However, in such inspection, even if a defect such as a short circuit or an open occurs in a part of the address bus ABR of the transmission / reception memory 14, the host controller 200
In some cases, the product was determined to be normal when checked with and the defective product could not be detected.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an inspection device for a serial controller capable of performing the input data collating function of the main controller and the address bus abnormality detection easily, accurately and at high speed. To aim.

[0040]

According to the present invention,
A plurality of nodes to which one or a plurality of sensors and actuators are connected are connected in a loop including a main controller, and the main controller outputs a data frame signal including first and second special codes and output data to the actuator. The data is sent at a predetermined cycle, and each node adds the input data from the sensor connected to the node after the first special code and outputs the output data to the actuator connected to the node with the second special code. The input that the main controller adopts as true input data when the input data of the sensor in the data frame signals received via the plurality of nodes match N times consecutively. It has a data collating function, and the main controller can also In a serial control device having a data transmission priority function of forcibly ending the data reception process and switching the process to the data transmission process at the transmission cycle, a plurality of types of data for one cycle of the data frame signal including non-transmission interval data are stored. Memory means, a start address register for latching the read start address of the memory means, an end address register for latching the read end address of the memory means, and the output of the start address register are initially loaded and a predetermined clock signal Counting operation to perform the counting operation from the initial load, and output the count output to the memory means as a read address of the memory means, and the output of the first counter means and the end. Compare the output of the address register and compare , A first comparing means for outputting a first coincidence signal each time, a second counter means for counting the number of received frames from the main controller, and a number of received frames for synchronization processing are set. The reception number setting means, second comparison means for comparing the output of the second counter means with the set number of the reception number setting means, and outputting a second coincidence signal each time the comparison result coincides, Control means for setting the read start address and the read end address in the start address register and the end address register so that data frame signals having a plurality of different input data contents are continuously transmitted when the memory means is read; Transmitting means for transmitting the output of the memory means to the main controller; and the first means for reading from the memory means. When the first comparing signal is output from the first comparing unit, if the second comparing signal is not output from the second comparing unit, the same predetermined address is output until the second matching signal is output. Data is read from the memory means, and when the second match signal is output, first synchronization control means for restarting data read from the start address and the first match signal are output. And a second synchronization control means for interrupting the data reading and restarting the data reading from the start address when the second coincidence signal is output in the non-operating state, While receiving the input data collation result in the main controller, the input data collation function in the main controller is varied while changing the input data collation count N. Characterized in that so as to check the data matching function.

According to the present invention, when the input data collating function of the main controller is inspected, a plurality of data frame signals having different data contents are continuously transmitted from the inspection device to the main controller. Then, while receiving the input data comparison result in the main controller,
The input data collating function is inspected while changing the collation number N of the input data collating function in the main controller. However, when reading the data from the memory means, a plurality of data frame signals are transmitted. When the inspection device has not completed the reception of the set number of data frame signals at the end of one way, no data is transmitted by, for example, transmitting the data of the end address until the reception of the set number of times is completed. Continue sending the data of the section,
When the set number of receptions is completed, the transmission operation is restarted from the first data frame signal. Therefore, the data transmitted from the inspection device is not interrupted on the way, and the input data collating function can be efficiently inspected without erroneous inspection.

When the reception of the set number from the main controller is completed before the transmission of the plurality of data frame signals is completed, the transmission of the plurality of data frame signals is restarted from the beginning. In this way, we are prepared for data interruption.

Further, according to the present invention, the receiving means having the receiving memory for storing the received serial data, the serial / parallel converting means for converting the serial data in the receiving memory into serial / parallel, and the serial / parallel converted receiving. In the transmission / reception memory, there is provided a main controller having a transmission / reception memory in which transmission data of the stored parallel data is read while data is written, and transmission means for converting the data read out from the transmission / reception memory into serial data and transmitting the serial data. A host controller for outputting the stored transmission data to the main controller and receiving the reception data written in the transmission / reception memory, the address bus of the reception memory, the address bus on the host controller side of the transmission / reception memory, and the In an inspection device of a serial control device for inspecting an abnormality of the transmission means of the reception memory and the address bus on the reception means side, the transmission data of the transmission means of the main controller is received and the data is transmitted to the reception memory of the main controller. The inspection means is connected to the main controller, the same data is written from the host controller to all addresses of the transmission / reception memory of the main controller, the data is transmitted to the inspection device via the transmission means of the main controller, and the inspection means is used. A first check is performed to check whether the same data has been written to all addresses of the transmission / reception memory, and the same data is transmitted from the inspection means to the transmission / reception memory via the reception memory of the main controller so that all the addresses of the transmission / reception memory are Write the same data and write normally The second check, which is performed by the host controller to check whether or not the data is congested, and all different data for the address in which only one bit in the address bus of the transmission / reception memory has an output state different from other bits. Data is transmitted from the inspection means to the main controller so as to be stored, and a third inspection in which the host controller inspects whether or not the storage is normally performed is executed. The address bus of the receiving memory based on the inspection result of the third inspection,
It is arranged to check which of the address bus on the host controller side of the transmission / reception memory and the address bus on the transmission means / reception means side of the transmission / reception memory has an abnormality.

According to the configuration of the present invention as described above,
The inspection of the stage 3 is performed, and it is determined which of the three address buses is short-circuited or open based on the normal / abnormal relationship.

[0045]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 2 shows the overall configuration of the embodiment of the present invention. An inspection apparatus 20 for performing various inspections of the main controller 100 is a personal computer (personal computer) 30 and an expansion board EB mounted on the personal computer 20. It is composed of. Then, a portion having the extension board EB has a reception function of receiving transmission data from the main controller 100 and performing various inspections, and a transmission function of transmitting the reception data of the main controller 100 to the main controller 100. I am trying to install it. The internal configuration of the main controller 100 is shown in FIG.
The configuration is the same as that shown in FIG.

FIG. 3 shows the configuration of the data receiving side of the inspection device 20 (the side that receives the data transmitted from the main controller 100).

In FIG. 3, the main controller 100
The reception frame from is received by the receiving unit 61. The receiving unit 61 inputs the received frame to the special code detecting unit 62, the shift register 67, and the error detecting unit 77, and also forms and outputs a clock signal CK from the received frame signal.

The special code detector 62 detects the first start code STI, the second start code STO, the stop code SP, etc. in the data frame signal shown in FIG. 20, and outputs the first start code detection signal STI and the second start code STI. The start code detection signal STO and the stop code detection signal SP are output to each circuit, the end of the data frame signal is detected, and the end detection signal FE is output.

The output point counter 63 counts the number of clock signals CK from the input of the second start code detection signal STO to the input of the stop code detection signal SP to thereby obtain the data frame signal shown in FIG. The total number of actuators (the number of output points) is counted by counting the number of bits of output data DO to the inside actuators.

The non-transmission section detection counter 64 counts the number of clock signals CK from the input of the end detection signal FE to the input of the first start code detection signal STI, and thereby the data frame signal and the data frame signal. A non-transmission section t (see FIG. 23) between the and is measured.

The measured values of the output point counter 63 and the non-transmission section detection counter 64 are set to the data bus DB by activating the output enable signals OE1 and OE2 output from the decoder 60 in response to a command from the personal computer 30. It is designed to be input to the personal computer 30 via.

In this case, the shift register 67 is an 8-bit shift register, receives the frame signal as serial data received by the receiving unit 61, and shifts this frame signal in synchronization with the clock signal CK. The comparison setting value register 65 is also composed of 8 bits, and the comparison setting value register 65 operates so as to write the data on the data bus DB when the output WP of the decoder 60 according to the instruction of the personal computer 30 is input.

The comparison circuit 66 compares the parallel output (8 bits) of the shift register 67 with the setting data (8 bits) of the comparison setting value register 65, and when even one bit among the 8 bits does not match, the mismatch signal EXSUM. To H.

The second start code detection signal STO, the stop signal detection signal SP and the clock signal CK are input to the clock enable generation circuit 74, and the clock enable signal is output every 8 bits during the period from the STO signal to the SP signal. Outputs CKE1. That is, the actuator output data DO in the data frame signal of FIG.
Clock enable signal C every 8 bits only during
Output KE1.

The flip-flop 75 latches the second start code STO with the clock signal CK and outputs the latch output to the gate 76. That is, the detection output of the STO signal by the flip-flop 75 is output to the gate 76 each time the frame signal is received. Further, the gate 76 receives the write pulse signal W from the decoder 60.
P is input. Therefore, each time the frame signal is received from the gate 76 or the comparison set value register 6
A signal is output every time the setting data of 5 is rewritten.

Gates 68 to 72 and flip-flop 7
The configuration according to 3 is a configuration for holding the non-coincidence signal EXSUM even if the non-coincidence signal EXSUM is output even once in one data frame signal, and even one bit does not coincide in one data frame signal. If there is, the CHKEND signal is output. This CHKEND
As described above, the signal is reset each time the frame signal is received by the gate 76 or each time the setting data of the comparison setting value register 65 is rewritten.
It is a signal that changes in synchronization with the reception cycle of one frame signal.

The error detector 77 detects a transmission error of the data frame signal received by the receiver 61 by CRC check or the like, and when it detects an error, sets the error detection signal DTERR to H. The gate 78 has an error detection signal D
The AND signal of the inverted signal of TERR and the frame end signal FE is taken and the AND result is output. Therefore, gate 7
The output of 8 becomes H when no error is detected and the frame end signal FE is input.

Therefore, the CHKEND signal is taken into the configuration of the gates 79 to 82, the flip-flop 83 and the OR gate 85 when no transmission error is detected in one data frame. Further, since the output CHGDT of the flip-flop 83 is reset by the write pulse signal WP, the output CHGDT of the flip-flop 83 corresponds to a plurality of cycles of the frame signal until the setting data of the comparison setting value register 65 is rewritten. During the period, even if even 1 bit in the frame signal when the transmission error does not occur, it becomes H when the mismatch with the setting data of the comparison setting value register 65 occurs. This mismatch signal CHGDT is the output B of the decoder 60.
When EN is enabled, the data is input to the personal computer 30 via the three-state buffer 84 and can be observed by the personal computer 30.

4 and 5 show the configuration of the data transmission side in the inspection device 20 (the side that transmits the data received by the main controller 100). The configuration shown in FIGS. 4 and 5 is such that the data for forming the data frame signal to be transmitted to the transmission memory 44 (backed up by the backup power supply) by the personal computer 30 is written and the data written in the transmission memory 44 is written. Is read out and an arbitrary frame signal is transmitted to the main controller 100 at an arbitrary cycle.

Here, in the configuration on the transmission side, the following two transmission modes can be selected by the personal computer 30.

Synchronous mode ... The first mode is a synchronous mode. In this synchronous mode, when the data frame signal is transmitted from the inspection device 20 to the main controller 100, the data frame signal from the main controller 100 is preset. The inspection device 20 by the predetermined number (n)
Each time it is received, the transmission data frame signal is synchronized. That is, when it is detected that n data frame signals from the main controller 100 have been received while transmitting the transmission data frame signal in this synchronous mode, the transmission of the transmission data frame signal is restarted from the beginning. I am trying. In addition, after the transmission of the data frame signal is completed, the transmission of the next data frame signal is started after it is detected that n data frame signals have been received from the main controller 100.

Asynchronous mode: a mode in which the above-mentioned synchronous processing is not performed, and the transmission operation in the inspection device 20 is executed regardless of the reception operation.

When the personal computer 30 executes the above synchronous mode, as shown in FIG. 6, the DB7 bit in the lower 8 bits DB0 to DB7 of the data bus DB of the personal computer 30 is set to "1" (asynchronous mode). In this case, the DB7 bit is "0"), and the number n of received data frame signals to be subjected to the above synchronization processing is set in DB0 to DB6. When the lower 8 bits DB0 to DB7 of the data bus DB are set to perform the synchronous mode, the personal computer 30 outputs predetermined control data to cause the decoder 31 to output the synchronous mode start signal STSYN.

That is, this synchronous mode start signal STS
When YN is output from the decoder 31, this signal STS
The set number n by YN is taken into the set number register 101 of the first stage of FIG. 5 via the data buses DB0 to DB6, and the synchronous mode identification bit DB7 is latched by the flip-flop 104.

Next, FIG. 7 shows data for forming a data frame signal stored in the transmission memory 44 of FIG. That is, in FIG. 7, a data frame signal A having a certain data pattern in the first storage area and non-transmission section data for determining a non-transmission section of the data frame signal A (all bits are set to 1 23 t) A is stored, and the data frame signal B and the data frame signal B in which the contents or data length of the data DO (see FIG. 20) and the like are different from the data frame signal A in the second storage area. Non-transmission period data (all bits are set to 1) B for determining the non-transmission period of B are stored, and similarly, data frame signals C, D, and B having different data patterns from those of the data frame signals A and B are stored. , And non-transmission interval data C, D, E, ... Which determine the non-transmission interval of these data frame signals C, D, E are sequentially stored in pairs in each storage area. There.

As described above, the transmission memory 44 stores a plurality of different data patterns and non-transmission section data for only one cycle each.

Therefore, when the stored data in the transmission memory 44 is read, for example, when the start address at the time of reading is designated in the STA of FIG. 7 and the end address is designated in the EDA of FIG. 7, the address from the address STA to the address EDA Since the section is repeatedly specified, the data frame signal A for a plurality of cycles as shown in FIG. 23 can be transmitted even though the stored data is for one cycle.

Similarly, the start address is set as shown in FIG.
7 and the end address is specified in the EDB of FIG. 7, the data frame signal A and the data frame signal B can be transmitted alternately as shown in FIG.

Next, referring to FIG. 4, registers 45 and 3
The status buffer 46 is configured to write the transmission data from the personal computer 30 to the transmission memory 44. When writing, the personal computer 30 first controls the control bus CB.
To output a write enable (write) signal W from the decoder 31 and output predetermined control data to
The address of the transmission memory 44 is sent to the data bus DB. As a result, the address of the transmission memory 44 is written in the register 45. Next, by outputting predetermined control data from the personal computer 30 via the control bus CB and causing the decoder 31 to output the OE1 signal, the OE2 signal and the write pulse signal (not shown) to the transmission memory 44, the three-state buffer. 46 and 47 are set to the output enable state, and the transmission data to be written to the address previously output to the register 45 is sent to the data bus DB.
As a result, the address latched in the register 45 is applied to the address terminal of the transmission memory 44 through the 3-state buffer 46, and the transmission data is transmitted in the 3-state buffer 4.
7 to the data terminal of the transmission memory 44, and data writing to the transmission memory 44 is performed.

By repeating the above operation while updating the addresses of the transmission memory one by one, the data shown in FIG. 7 is written in the transmission memory 44 in advance. When reading the data written in the transmission memory 44, the start address SA and the end address EA of the transmission memory 44 corresponding to the data frame signal to be transmitted by the personal computer 30 are set to the start address register 40 and the end address of the first stage, respectively. Register 36
Write in. That is, the personal computer 30 first outputs the write signal WS of the start address register 40 from the decoder 31 to cause the start address SA on the data bus DB.
Is transmitted, the start address SA is written in the start address register 40. Next, personal computer 30
Thus, the write signal WE of the end address register 36 is output from the decoder 31 and the end address EA is sent to the data bus DB, so that the end address EA is written in the end address register 36. Also, at this time,
The transmission memory 44 is set to the read state by the personal computer 30.

The write signal WE is the set count register 102 and the flip-flop 10 in the second stage of FIG.
5, when the end address EA is input to the end address register 36, the set number n and the synchronization mode identification bit DB7 are input from the first stage set number register 101 and the flip-flop 104 to the second stage. Set count register 102 and flip-flop 105
Transferred to.

The data written in the start address register 40 and the end address register 36 of the first stage are transferred to the start address register 41 and the end address register 37 of the second stage of FIG. Data transfer is performed by three flip-flops 32 to 3
4 and an AND gate 35 to control the transfer enable signal CKE output from the data transfer control unit 50.

The data transfer control section 50 is composed of flip-flops 32, flip-flops 33 and 34, and an AND gate 35 whose D terminal is high clamped and a WE signal is input to the clock terminal. The transfer enable signal CKE formed by the logical product of the STALOAD signal and the output of the flip-flop 33 becomes H only when the first STALOAD signal is output after the WE signal is output (the flip-flop 34 Because the output of the flip-flop 32 is reset by this), the data written in the start address register 40 and the end address register 36 of the first stage at this time are stored in the start address register 41 and the end address register 37 of the second stage. Forward. In this way, the transfer timing to the start address register 41 and the end address register 37 of the second stage is inspected by forming the transfer enable signal CKE by biting the STALOAD signal to the write signal WE output from the personal computer 30 side. Device 2
It is synchronized with the circuit within 0.

The loadable counter 42 initially loads the start address SA written in the start address register 41 at the timing of the initial load signal SAME1 and performs a counting operation in synchronization with the clock signal CK from the initially set start address. , The count value is sent to the transmission memory 4 via the 3-state buffer 43.
4 is applied to the address terminal of the transmission memory 44.
Read data from. However, as for the clock signal CK, the clock enable signal COUNTEN1 is at H level.
Is valid only when is set.

The data read from the transmission memory is P
After the parallel / serial conversion is performed by the / S converter 48, the data is transmitted to the main controller 100 via the transmitter 49.

On the other hand, the output of the loadable counter 42 is also input to the comparison circuit 38. The comparison circuit 38 outputs the output of the end address register 37 and the loadable counter 4
When the two outputs are compared and they match, a match signal SAME
Is output to the OR gate 120 and the AND gate 118 in FIG.

Next, in FIG. 5, the receiving section 61 is the same as that shown in FIG.
Receive a data frame signal from 0. The STI detection circuit 62 'is shown by extracting only the STI detection portion of the special code detection unit 62 shown in FIG.
The first start code STI in the data frame signal indicated by 0 is detected, and the detection signal FRSTDTECT is applied to the clock terminal of the reception frame counter 109.

The reception frame counter 109 counts the detection signal FRSTDTECT of the STI detection circuit and inputs the count value to the comparison circuit 108.

The comparison circuit 108 compares the set number n of the received data frame signals set in the third stage set count register 103 with the count value of the received frame counter 109, and when both match, a match signal FRSTOK is given. Output.

The third stage setting count register 103
And the flip-flop 106 includes the flip-flop 1
At the timing of the SAME1 signal output from 24, the second stage setting count register 102 and the flip-flop 1
Each data is transferred from 05.

The selector 131 includes an AND gate 117,
The match signal FRSTOK output from the comparison circuit 108 and the match signal SAME output from the comparison circuit 38 are selected by the output STMOD of the flip-flop 106 by the configuration including the 118 and the OR gate 119. Basically, the STMOD signal is When it is H (in the synchronous mode), the FRSTOK signal is selected, and when the STMOD signal is L (in the asynchronous mode), the SAME signal is selected. That is, the output STAL of the selector 131
Basically, the OAD signal becomes H each time the output of the loadable counter 42 matches the end address EA in the asynchronous mode, and the number of data frame signals received from the main controller 100 in the synchronous mode. It becomes H each time it matches the set value n.

This STALOAD signal is delayed by the flip-flop 124 to become the SAME1 signal. This SAME1 signal is input to the set count register 103 and the flip-flop 106, and at the timing of this SAME1 signal, the respective data from the second-stage set count register 102 and the flip-flop 105 are transferred to the third-stage set count register 103 and the flip-flop. 106. Further, this SAME1 signal is applied to the loadable counter 42.
Is input to the loadable counter 42 at the timing of the SAME1 signal.

Next, the OR gate 120, the gate 121,
The loadable counter 42 includes a logic block 132 including an AND gate 122 and a flip-flop 123.
COUNTEN, which is the enable signal for the count operation of
A COUNTEN_ signal, which is the basis of one signal, is formed. In this specification, the signal COUNTE
_ Added after the signal name such as N_ is logical inversion (bar)
, And signals with _ are valid at L.

Further, the ring counter 126 is set to P / in FIG.
The S / converter 48 counts the conversion clock signal CK_ for P / S conversion, and in this case, it is composed of a 3-bit counter. That is, in this case, the transmission memory 4
The read data of No. 4 is in units of 8 bits, and the P / S converter 48 converts the 8-bit data into serial data by the P / S converter 48.
It is necessary to synchronize the data so that the data is read from the transmission memory 44 each time the S conversion is performed. Therefore, the P / S conversion clock CK_ is counted by the 3-bit ring counter 126 and the carry signal is input to the gate 127. The gate 127 causes the carry signal to be bitten by the COUNTEN_ signal.
The carry signal is passed only when the N_ signal is L, and the carry signal is used as the COUNTEN1 signal.
I am trying to input in 2. The counter 26 is SA
It is reset by the ME1 signal.

In such a configuration, the operation in the asynchronous mode will be described first.

When the power is turned on, the flip-flop 3
2. Since the start address registers 40 and 41, the end address register 37 and the loadable counter 42 are reset by the reset signal RST, the comparison circuit 38 detects a match and outputs a match signal SAME when the power is turned on. This allows the selector 131 to S
The TALOAD signal is output and input to the AND gate 35 of the data transfer control unit 50. Further, after the power is turned on, the start address register 40 is set as described above.
If the writing of the start address SA and the end address EA to the end address register 36 is completed, the write signal W of the end address register is written.
E (the WE signal is output after the WS signal) is detected by the flip-flop 32, and the detection signal is output to the AND gate 35 after timing adjustment is performed by the flip-flop 33.

Therefore, the transfer enable signal CKE signal output from the AND gate 35 becomes H after the power signal is turned on and the write signal WE of the end address register is output, whereby the start address register 40 of the first stage is set. And the data written in the end address register 36 is the start address register 4 in the second stage.
1 and the end address register 37.

Further, the flip-flop 124 which outputs the SAME1 signal is configured to latch the output SAME of the comparison circuit 38 at the falling edge of the clock signal CK. Therefore, after the power is turned on, the data in the start address register 40 is Until the data is transferred to the start address register 41, the loadable counter 42 is initially loaded with the data of the start address register 41 that is reset at each falling edge of the clock signal CK.

However, when the data of the start address register 40 is transferred to the start address register 41, the data of the end address register 36 is also transferred to the end address register 37, so that the output of the comparison circuit 38 is output at the time of the data transfer. SAME falls to L. However, as described above, the flip-flop 12
Reference numeral 4 is for latching the output SAME of the comparison circuit 38 (in this case, the selector 131 selects the SAME signal because it is in the asynchronous mode) at the falling edge of the clock signal CK. Initial load signal SA output from
ME1 still maintains H, and as a result, the data in the start address register 41 is initially loaded into the loadable counter 42 at the time of the data transfer.

After the initial loading is completed, the personal computer 30 enables the OE3 signal output from the decoder 31. As a result, the count value of the loadable counter 42 is transmitted to the transmission memory 4 via the 3-state buffer 43.
4 is added to the address terminals, and the transmission memory 44 sequentially starts reading data from the start address SA set in the start address register 41. The read data is converted from parallel data to serial data by the P / S converter 48, and then transmitted to the main controller 100 via the transmission unit 49. After that, the count operation in synchronization with the clock signal CK of the loadable counter 42 sequentially increments the address of the transmission memory 44 by +1 and the data is read from the address corresponding to the count value. In addition,
In the asynchronous mode, since the STMOD signal is L, the output COUTEN_ of the flip-flop 123 is also always L. Therefore, the clock enable signal COUNTEN1 signal input to the loadable counter 42 is output every time the counter 126 outputs carry. Therefore, the count operation of the loadable counter 42 is not stopped.

As the counting operation proceeds, the output of the loadable counter eventually coincides with the end address EA set in the end address register 37. The comparison circuit 38 detects this coincidence and raises the output SAME to H at the time of coincidence detection.

Therefore, the initial load signal SAME1 is output again from the flip-flop 124, whereby the loadable counter 42 is again initially loaded with the set start address SA of the start address register 41. Therefore, after this, the loadable counter 42 again executes the counting operation from the start address SA up to the end address EA set in the end address register 37, and as a result, the previously read data frame signal for one cycle, for example, is obtained. A data frame signal having the same data content and the same sampling period will be output from the transmission memory 44. By repeating such operations, the transmission memory 44
Although only one cycle of data is stored in, the data frame signals of a plurality of cycles as shown in FIG. 23, for example, can be transmitted to the main controller 100.

When changing the contents of the transmission data, the start address register 40 is followed by the same procedure as described above.
The setting contents of the end address register 36 may be changed.

Next, the operation in the synchronous mode will be described.

It is assumed that the synchronous mode is selected after the transmission operation in the asynchronous mode. First, the operator sets the DB7 bit in the lower 8 bits DB0 to DB7 of the data bus DB to "1" (DB7 bit is "0" in the asynchronous mode), and the received data for performing the above synchronization processing on DB0 to DB6. The number n of frame signals is set. Further, by outputting predetermined control data from the personal computer 30, the synchronous mode start signal STSYN is output from the decoder 31. The signal STSYN causes the set number n to be taken into the set number register 101 in the first stage of FIG. 5 via the data buses DB0 to DB6, and the synchronous mode identification bit DB7 to be latched in the flip-flop 104.

Then, the required start address SA and end address E are obtained in the same manner as in the asynchronous mode.
A is written in the start address register 40 and the end address register 36. At this time, the write signal WE is output when the end address EA is written to the end address register 36.
By E, the set count n and the synchronization mode identification bit DB7 are transferred from the set count register 101 and flip-flop 104 in the first stage to the set count register 102 and flip-flop 105 in the second stage.

At the time of this transfer, the end address register 37 and the start address register 41 have
The end address EA and the start address SA in the previous asynchronous mode are still stored. The loadable counter 42 also continues the counting operation. Therefore, the count value output from the loadable counter 42 eventually coincides with the end address EA in the previous asynchronous mode set in the end address register 37, and at this time, the comparison circuit 38 outputs the coincidence signal SAME.

When the coincidence signal SAME is output, the third stage set count register 103 and the flip-flop 106 still have the second stage registers 102 and 105.
Data has not been transferred, so the STMOD signal remains L. Therefore, at this point, the selector 13
1 selects the SAME signal. Therefore, when the count value output from the loadable counter 42 matches the end address EA in the previous asynchronous mode set in the end address register 37, the match signal SAME output from the comparison circuit 38 is the STALOAD signal. Is input to the AND gate 35 of the data transfer control unit 50, which outputs the transfer enable signal CKE,
The end address EA and the start address SA in the synchronous mode set in the end address register 36 and the start address register 40 of the first stage are the end address register 37 and the start address register 4 of the second stage.
Forwarded to 1.

The STALOAD signal is slightly delayed by the flip-flop 124, and the initial load signal SAM
It is input to the loadable counter 42 as E1. Therefore, the start address SA for the synchronous mode transferred to the start address register 41 of the second stage is initially loaded in the loadable counter 42 immediately after the transfer. And
Due to this initial load, the output SAME of the comparison circuit 38 becomes L.
Fall to.

On the other hand, the SAME1 signal is input to the third-stage setting count register 103 and the flip-flop 106 as a transfer timing signal. Therefore, at the output timing of the SAME1 signal, the second-stage setting count register 102 and The setting data of the flip-flop 105 is transferred to the third-stage setting count register 103 and the flip-flop 106. Further, the ring counter 126 is reset by the SAME1 signal.

As a result, the STMOD signal becomes H, and thereafter the selector 131 shifts to the synchronous mode for selecting the FRSTOK signal output from the comparison circuit 108.

When the STMOD signal becomes H, one of the inputs of the AND gate 122 becomes H, but the other input remains L because SAME becomes L.
Therefore, the output COUNTEN of the flip-flop 23
_ Maintains L. Therefore, the output C of the gate 127
COUNTEN1 becomes H each time the 3-bit ring counter 126 outputs a carry signal.
One signal is input to the loadable counter 42 as a clock enable signal.

Therefore, the loadable counter 42 is set to the above S.
The counting operation from the initial load value is executed from when the AME1 signal is output.

When the SAME1 signal is output, the OE3 signal output from the decoder 31 is enabled by the personal computer 30, whereby the count value of the loadable counter 42 is set to the 3-state buffer 43.
The data is added to the address terminal of the transmission memory 44 via, and the transmission memory 44 sequentially starts reading data from the start address SA set in the start address register 41. The read data is converted from parallel data to serial data by the P / S converter 48, and then transmitted to the main controller 100 via the transmission unit 49.

After that, the address of the transmission memory 44 is sequentially incremented by +1 by the count operation in synchronization with the carry signal of the counter 126, and the data read from the address corresponding to the count value is set in the end address register 27. The end address EA is executed.

In this synchronous mode, as shown in FIG. 1A, n data frame signals from the main controller 100 have been received while the transmission data frame signal was being transmitted from the inspection device 20. Is detected. That is, it is assumed that the FRSTOK signal is output from the comparison circuit 108 before the count value of the loadable counter 42 matches the end address EA.

At this time, the FRSTOK signal is selected by the selector 131, and the SAME1 signal becomes H. Therefore, when the FRSTOK signal is output, the loadable counter 42 is loaded with the set start address SA of the start address register 41 as an initial value.

In addition, the gate 121 of the logic block 132
Since the FRSTOK signal of H is input to the
The output of 21 remains L. Therefore, the H COUNTEN1 signal is input to the loadable counter 42 every time the counter 126 outputs a carry, and the count operation of the loadable counter 42 is not stopped.

Therefore, as shown in FIG. 1A, when the FRSTOK_ signal is output from the comparison circuit 108 before the count value of the loadable counter 42 matches the end address EA, the transmission memory 44 starts. The read operation from the address SA is re-executed.

Further, as shown in FIG. 1B, when the transmission of the data frame signal is finished (when the count value of the loadable counter 42 reaches the end address EA), the FRSTOK signal is still output from the comparison circuit 108. Is not output, the reading from the start address SA is executed after the output of the FRSTOK signal.

That is, when the output of the loadable counter 42 coincides with the end address EA set in the end address register 37, the coincidence signal S from the comparison circuit 38.
Since AME goes high and the FRSTOK signal is low at this time, the gate 121 of logic block 132 goes high. Therefore, the output COU of the flip-flop 123
The NTEN_ signal becomes H, and as a result, the clock enable signal COUNTEN1 signal of the loadable counter 42 becomes L regardless of the carry of the counter 126.

As a result, the output of the loadable counter 42 is not updated and is fixed at the end address EA. As a result, the data of the end address EA, that is, the data of the non-transmission section is output from the transmission memory 44. Will continue.

After that, when the number of received frame signals from the main controller 100 matches the number n set in the set number register 103, the comparison circuit 108 outputs a match signal FR.
STOK becomes H. This FRSTOK signal is selected by the selector 131, which causes the SAME1 signal to go high. Therefore, when the FRSTOK signal is output, the startable address register 4 is added to the loadable counter 42.
The set start address SA of 1 is loaded as the initial value.

In addition, the gate 121 of the logic block 132
Since the FRSTOK signal of H is input to the
The output of 21 goes from H to L, and the output of the logic block 132, COUNTEN_, goes to L. Therefore, the loadable counter 42 has an H level for each carry of the counter 126.
COUNTEN1 signal is input, and the loadable counter 42 restarts the counting operation.

Therefore, as shown in FIG. 1B, when the count value of the loadable counter 42 reaches the end address EA, if the FRSTOK signal is not yet output from the comparison circuit 108, the FRSTOK signal is output. The data of the end address EA, that is, the data of the non-transmission section is continuously transmitted until it is output, and the reading from the start address SA is restarted after the output of the FRSTOK signal. In this way, the main controller 10
The data frame signal can be repeatedly transmitted from the inspection device 20 to the main controller 100 in synchronization with the received frame signal from 0. Although the end address data is continuously transmitted in the above embodiment, the start address data may be continuously transmitted.

FIG. 9 shows a time chart of various signals in the synchronous mode of FIG. 1A, and FIG.
The time chart of various signals in the synchronous mode of (b) is shown.

Next, a processing procedure in the case of inspecting the sensor data of the main controller 100 for a plurality of collating functions by using the inspection device 20 will be described.

As described above, the main controller 10
After the power is turned on, 0 is the number of output points (from the difference between the length of the actuator data in the received frame signal and the length of the actuator data in the transmitted initial frame signal shown in FIG. The total number of actuators is automatically detected, and the data length Ld (Fig.
(Refer to) (Data length automatic determination function)
The number of input points (the total number of sensors) is automatically detected from the length l of the sensor data in the received initial frame signal, and the transmission cycle T of the data frame signal is detected according to the detected value of this input point and the detected number of output points. The (sampling time) is determined (sampling time automatic determination function), and the actuator sent from the host controller 200 after the data length and sampling time are determined (by the multiple input / output point verification function). The normal data frame signal shown in FIG. 20 is automatically formed on the basis of the control data and is sent to the node at a predetermined sampling period T.

Then, when the data frame signal is received, the main controller 100 adopts the sensor data in the received data frame signal as the true sensor data, starting from the same number of times in succession. Multiple times matching function). However, if a transmission error has occurred in the received data frame signal, it is ignored, and it is not included in the number of times of the above collation.

In testing this function, first, an initial frame signal to be received by the main controller is written, for example, in the area A (see FIG. 7) of the transmission memory 44, and in the area B (see FIG. 7). Write the first to ninth data frame signals having a plurality of different sensor data portions as shown in FIG. In order to inspect the function in the case where the error occurs, data that causes an error is appropriately mixed in the plurality of data frame signals.

Next, the mode of the inspection apparatus 20 is set to the asynchronous mode, and the start address SA and the end address EA are designated so that the initial frame signal written in the area A can be read from the transmission memory 44. And
Main controller 100 and host controller 20
The power of 0 is turned on, and the initial frame signal is repeatedly transmitted to the main controller 100.

Upon receipt of this initial frame signal, the main controller 100 determines the data length and sampling time by using the data length determining function and the sampling time determining function, and after determining the actuator control data sent from the host controller 200. A normal data frame signal is automatically formed on the basis of the data and sent to the node at a predetermined sampling period T.

This normal data frame signal is sent to the inspection device 2
0 is received by the receiving side configuration shown in FIG. Therefore, the output point counter 63 counts the number of output data to all actuators in the data frame signal received by the above-described operation, and reports this to the personal computer.
Further, the non-transmission section detection counter 64 measures the interval (t in FIG. 23) of the received data frame signal and reports the measured output to the personal computer 30. The personal computer 30 determines the outputs of the main controller 100.
From the normal data frame signal is detected.

When this detection is performed, the personal computer 30 sets the mode of the inspection device 20 to the synchronous mode, specifies the set number n (n = 9 in this case) of the received data frame signal, and writes it in the area B. The start address SA and the end address EA are designated so that the plurality of data frame signals are continuously read from the transmission memory 44.

As a result, nine data frame signals having different sensor data contents as shown in FIG. 11 are continuously transmitted from the transmission memory 44.

As described above, the main controller 100 transmits the sensor data in the received data frame signal to the host controller 200, and the host controller 200 should observe the sensor data in the data frame signal. You can

Therefore, the main controller 100 receives the data frame signal sent from the transmission side of the inspection device 20, and the host controller 200 checks the sensor data and appropriately sets the set value N of the number of times of verification of the multiple times verification function. By changing (N is changed by operating the switch attached to the main controller), it is confirmed whether the multiple collation function of the sensor data is operating normally.

For example, when a plurality of data frame signals including sensor data having different data contents as shown in FIG. 11 are continuously input, assuming that a data frame signal having a communication error is normally removed, n If = 0 is set (no collation), the lower 3 bits are 0 or 1.
When it is not fixed to and is in an undefined state and the other bits are fixed to 0, it is judged that the above-mentioned multiple collation function of the sensor data is operating normally. Similarly, when n = 1 is set, the least significant bit is fixed to 1, the lower 2nd bit and the 3rd bit are in an undefined state, and the other bits are fixed to 0. Judge that the function is operating normally. Further, when n = 3 is set, the lower 3rd bit is fixed to 1, the lower 2nd bit and the 1st bit are fixed to the initial value of the reception memory (memory for storing reception data) in the main controller 100, When the other bits are fixed to 0, it is determined that the above-mentioned multiple collation function of the sensor data is operating normally.

When an error occurs in which it is impossible to remove the data frame signal including the communication error in the main controller 100, as shown in FIG. 11, even if the set number N is the same, the input data to the host controller 200 remains unchanged. Since this is different from the normal state, it is possible to detect that an error has occurred in the error detection function of the main controller 100.

In this way, the collation function of the sensor data is tested a plurality of times.

When inspecting the collation function of the sensor data a plurality of times, the inspection device 20 is set to the synchronous mode. Therefore, for example, even if the transmission intervals of the data frame signals having a plurality of different data contents shown in FIG. 11 which are transmitted from the inspection device 20 are set to be somewhat rough (the state shown in FIG. 1A does not occur). When the FRSTOK signal is input, when the FRSTOK signal is input, the data in the non-transmission section of the last data frame signal is set to be rough as shown in Fig. 1 (a). The stored data is set to the state of being transmitted.), And the transmission state of the state shown in FIG. 1B is continued, whereby the main controller 100 in which the transmission side priority logic is built is transmitted from the inspection device 20. Data can be transferred to the transmission / reception data memory 11 without interruption in the middle, and the above-mentioned collation function of the sensor data can be efficiently performed without erroneous inspection. It can be.

Next, the main controller 1 shown in FIG.
The inspection of the address bus ABR of the receiving memory 14 in 00, the address bus ABM of the transmitting / receiving data memory 11 on the transmitting device 12 and receiving device 13 side, and the address bus ABP of the transmitting / receiving data memory 11 on the host controller 200 side will be described.

However, as described above, the reception memory 14
Is a memory with a data width of 1 bit, a send / receive data memory 1
1 is a memory having a data width of 8 bits, and the receiving memory 1
S / P conversion of output data of 4 and transmission / reception data memory 1
1, so that the address bus AB of the reception memory 14 is stored.
The lower 3 bits of data of R corresponds to 1 byte. That is, the fourth least significant bit of the reception memory 14 corresponds to the least significant bit of the transmission / reception data memory 11. As described above, the transmission data and the reception data stored in the transmission data memory 11 are the highest 1 of the address bus ABM.
The transmission / reception data memory 11 by distinguishing the bit designation
Are stored in different storage areas. Therefore, hereinafter, the area where transmission data is stored is referred to as a transmission data area, and the area where reception data is stored is referred to as a reception data area.

In this inspection, the quality of each address bus is inspected by combining the following three inspections.

Inspection X: All addresses of the transmission data area of the transmission / reception data memory 11 of the main controller 100 from the host controller 200 (1 for each address)
The same data is written in (the byte data is stored), and the data is transmitted to the inspection device 20 via the transmission device of the main controller 100. By checking the transmission data by the comparison circuit 66 of the receiving side configuration shown in FIG. 3 of the inspection device 20, it is inspected whether or not the same data is written in all the addresses of the transmission / reception data memory 11.

Inspection Y: By transmitting the same data in 1-byte units from the inspection device 20 to the transmission / reception data memory 11 via the reception memory 14 of the main controller 100, all the addresses in the reception data area of the transmission / reception data memory 11 are the same. Data is written, and it is confirmed on the host controller 200 side whether or not normal writing is performed.

Inspection Z: As shown in FIG. 12, only 1 bit in the address bus ABM of the transmission / reception data memory 11 is H and the others are L (or only 1 bit is L and the others are H). ) Address (for example, 1 (0000
(0001) address, 2 (00000010) address, 4 (00000100) address, etc.) are transmitted from the inspection device 20 to the main controller 100 so that all different data are stored, and those data are stored normally. It is confirmed by the host controller 200 whether or not it has been deleted.

Next, each address bus ABP, ABM, A
A method for inspecting various abnormalities in BR will be described respectively.

(1) Short circuit at the address bus ABP of the transmission / reception data memory 11 First, the host controller 200 and the main controller 1
A case where an abnormality due to a short-circuit occurs in the address bus ABP between 00 and 00 will be described using FIG. The abnormality in this case is that a short circuit has occurred in the bit ABP1 next to the least significant bit of the address bus ABP and the bit ABP2 next to it. In case of short circuit, one line is L
Both lines become L at.

In the inspection X, since data cannot be written in the addresses "2" to "5", the data in the addresses "2" to "5" will be different from the data in other addresses. Therefore, since the inspection device 20 cannot receive the same data from all the address areas, it is detected as "abnormal" in this inspection.

In the inspection Y, when the data of the addresses "2" to "5" is read, the address "0" is actually read.
Or the data of "1" is read out. However,
In this case, since the same data is written in all the addresses, the host controller 200 indicates “normal”.
To judge.

In the inspection Z, when the data of the addresses "2" and "4" is read, the address "0" is actually read.
Will read the data of. Also, the address "3",
When trying to read the data of "5", the data of the address "1" is read. In the inspection Z, all different data should be read from all addresses, so that it is determined as "abnormal".

(2) Short-circuit at the address bus ABM of the transmission / reception data memory 11 It is assumed that, similarly to the above, a short circuit occurs between the bit ABM1 next to the least significant bit and the next bit ABM2 of the address bus ABM.

In the inspection X, when the data of the addresses "2" to "5" is read, the address "0" is actually read.
Or the data of "1" is read out. However,
In this case, since the same data is written in all the addresses, the inspection device 20 determines that it is “normal”.

In the inspection Y, since data cannot be written in the addresses "2" to "5", the data in the addresses "2" to "5" are different from the data in other addresses. Therefore, since the host controller 200 cannot receive the same data from all the address areas, it is detected as "abnormal" in this inspection.

In the inspection Z, when the data of the addresses "2" and "4" is read, the address "0" is actually read.
Will read the data of. Also, the address "3",
When trying to read the data of "5", the data of the address "1" is read. In the inspection Z, all different data should be read from all addresses, so that it is determined as "abnormal".

(3) Address bus AB of the receiving memory 14
Short at R As described above, the address bus ABR of the reception memory 14
Since the lower 3 bits of 1 correspond to 1 byte of the address ABM of the transmission / reception data memory 11, the lower 4 bits of the reception memory 14 correspond to the least significant bit of the address bus ABM of the transmission / reception data memory 11. Therefore, the short circuit of the address bus ABR will be described separately when the short circuit occurs in the lower 3 bits and when the short circuit occurs in the higher bits.

When a short circuit occurs in the bits higher than the lower 3 bits of the address bus ABR In this case as well, it is assumed that a short circuit occurs in the lower 5th bit and the 6th bit of the ABR, taking FIG. 13 as an example. That is, the addresses in FIG. 13 are addresses converted into the address bus ABM.

In the inspection X, since the receiving memory 14 is not used, it is determined as "normal" regardless of the occurrence of an abnormality in the receiving memory 14.

In the inspection Y, the data to be written to the addresses "2" to "5" (ABM conversion address) of the reception memory 14 is actually the address "0" or "1" (AB).
It writes to the address of M conversion). Therefore, when the data at the addresses "2" to "5" are transferred to the transmission / reception data memory 11, the data at the address "0" or "1" are transferred. However, in this case, since the same data is written in all the addresses, the host controller 200 determines that it is “normal”.

In the inspection Z, the data to be written to the addresses “2” and “4” (ABM conversion address) of the reception memory 14 are written to the address “0” (ABM conversion address). Further, the data at the addresses "3" and "5" are written to the address "1". When transferring these data to the transmission / reception data memory 11, FIG.
As shown in FIG. 4, all of the received data memory 14 is assigned to the addresses “0”, “2”, and “4” of the transmission / reception data memory 11.
The same data from the address "0" of is written. In this case, in the inspection Z, different data should all be read from the addresses “0”, “2”, and “4” of the transmission data memory 11, so it is determined as “abnormal”.

When a short circuit occurs in the lower 3 bits of the address bus ABR: In the inspection X, since the receiving memory 14 is not used, even if an abnormality occurs in the receiving memory 14, it is determined to be "normal".

The inspection Y is judged to be "abnormal" for the following reasons.

The same data transmitted from the inspection device 20 is set to 1
It is assumed that C6 (11000110) is set in hexadecimal, and the lower 2nd bit and lower 3rd bit of ABR are shooting. Further, it is assumed that data is written in the receiving memory 14 bit by bit from the upper bit to the lower bit. As can be seen from FIG. 13 above, when the address is originally designated as "5", the address is actually "1".
In the same manner, specify address "0" when address "4", address "1" when address "3",
When the address is "2", the address "0" is designated. Therefore, as shown in FIG. 15, data is written to the address "1" three times when the addresses "5", "3" and "1" are designated, and as a result, the data is finally written to the address "1". The data "1" when the address "1" is designated is written. Similarly, the data "0" when the last written address "0" is designated is written in the address "0".

Thereafter, when the data is read from the reception memory 14, the data is not read from the addresses "5" to "2" in the same manner, and the data is read from the addresses "0" and "1" as shown in FIG. The data is read out three times, and the data C6 is different from the first written data C6, which is determined as "abnormal".

In the inspection Z, it is judged as "abnormal" for the following reasons. If the data shown in FIG. 12 is adopted as the different data for each address, the same bit transfer as that shown in FIG. 15 is performed, and as a result, the data shown in FIG. It will be remembered. In this case, it is determined to be abnormal because different data must be stored in each address. Note that in FIG. 16, bit transfer is performed for all addresses in exactly the same manner as in FIG. 15, but the arrow shown in FIG. 16 results in data from “0” to “1” or “1”. Only the portion changing from "1" to "0" is shown.

The above results (1) to (3) are summarized in the table of FIG. That is, inspections X, Y,
If the inspection of Z is performed once, even if an abnormality occurs in any of the inspections, by comparing the combination of the normality and the abnormality in the table of FIG. 17, the abnormality occurs in any address bus in the main controller 100. Can be identified.

Next, the inspection of the address bus open abnormality will be described.

When open, the signal line is indefinite and can be regarded as fixed at H or L within the inspection time. Assuming that the lower 2nd bit is open and fixed at L, the designated address changes as shown in FIG.

That is, when the address bus is opened, the result is that the address that should originally be specified is replaced by another address, just as when the address bus is shorted. Therefore, each address bus ABP, AB
The inspection results for the inspections X, Y, and Z when an open abnormality occurs in M and ABR are as follows:
That is, it is exactly the same as that shown in the table of FIG.

[0162]

As described above, according to the present invention,
Multiple data frame signals with different data contents are continuously sent from the inspection device to the main controller. When the input data matching function of the main controller is inspected and data is read, one data frame signal is sent. When it is finished, if the reception of the number of data frame signals set from the main controller is not finished,
Since the predetermined same data is continuously transmitted until the reception of the set number of times is completed, and the transmission of the data frame signal is restarted at the time when the reception of the set number of times is completed, it is transmitted from the main controller. The frame signal and the frame signal transmitted from the inspection device can be synchronized, the data in the main controller is not interrupted in the middle, and the inspection of the input data collating function is erroneously inspected without changing the circuit. Can be done efficiently.

Further, according to the present invention, it is possible to perform three different tests and determine which of the address buses is short-circuited or open based on the normal / abnormal relationship, so that the test time can be greatly reduced. You can

[Brief description of drawings]

FIG. 1 is a diagram conceptually showing the main points of the present invention.

FIG. 2 is a block diagram generally showing an embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a configuration of a receiving side of the inspection device.

FIG. 4 is a block circuit diagram showing a configuration example of a receiving side of the inspection device.

FIG. 5 is a block circuit diagram showing a configuration example of a receiving side of the inspection device.

FIG. 6 is a diagram showing a setting register of a synchronization mode and a reception setting frequency.

FIG. 7 is a diagram showing an example of stored contents of a transmission memory.

FIG. 8 is a diagram showing an example of a data frame signal transmitted.

FIG. 9 is a time chart illustrating an embodiment of the invention.

FIG. 10 is a time chart explaining an embodiment of the present invention.

FIG. 11 is a diagram showing an example of data for checking an input data collating function.

FIG. 12 is a diagram showing an example of data used for inspection of an address bus.

FIG. 13 is a diagram showing an example of an address bus short circuit abnormality.

FIG. 14 is a diagram showing a transfer abnormality when an address bus short circuit abnormality occurs.

FIG. 15 is a diagram showing a bit transfer abnormality when the address bus is short-circuited.

FIG. 16 is a diagram showing a bit transfer abnormality when the address bus is short-circuited.

FIG. 17 is a diagram showing a correspondence between three inspections and an address bus abnormal position.

FIG. 18 is a diagram showing an example of an abnormality when the address bus is opened.

FIG. 19 is a diagram showing an overall configuration of a serial control device.

FIG. 20 is a diagram showing a manner of propagation of a data frame signal.

FIG. 21 is a diagram showing an initial frame signal transmitted from the main controller.

FIG. 22 is a diagram showing an initial frame signal received by the main controller.

FIG. 23 is a diagram showing a sampling period and the like.

FIG. 24 is a diagram showing an internal configuration around a memory of a main controller.

FIG. 25 is a view showing the connection between the main controller and the inspection device.

FIG. 26 is a diagram showing an example of data used in multiple-time collation function inspection of sensor data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Sensor group 2 ... Actuator group 10 ... Node 20 ... Inspection device 30 ... Personal computer 44 ... Transmission memory 100 ... Main controller 200 ... Host controller

Claims (3)

[Claims] 1. A plurality of nodes to which one or a plurality of sensors and actuators are connected are connected in a loop including a main controller, and the main controller outputs first and second special codes and output data to the actuator. A data frame signal including the data frame signal is transmitted at a predetermined cycle, each node adds input data from the sensor connected to the node after the first special code, and outputs data to the actuator connected to the node. Second
In addition to extracting from the special code of the above, the main controller determines as true input data when the input data of the sensor in the data frame signals received via the plurality of nodes match N times consecutively. In the serial controller having an input data collating function to be adopted, further, the main controller has a data transmission priority function of forcibly terminating the data reception process and switching the process to the data transmission process when the data transmission cycle comes during data reception, Memory means for storing a plurality of types of data for one cycle of the data frame signal including non-transmission section data, a start address register for latching a read start address of the memory means, and a read end address of the memory means The end address register and the start address register An output is initially loaded, and a counting operation from the initial load is performed by counting a predetermined clock signal, and a first counter means for outputting the count output to the memory means as a read address of the memory means, The output of the first counter means is compared with the output of the end address register, and a first comparing means for outputting a first coincidence signal each time the comparison result is coincident with the number of frames received from the main controller is calculated. The second counter means for counting, the reception number setting means for setting the number of reception frames for synchronization processing, the output of the second counter means and the set number of the reception number setting means are compared, and the comparison result is A second comparing unit that outputs a second matching signal each time a match occurs, and a plurality of different input data when reading the memory unit. Control means for setting the read start address and the read end address in the start address register and the end address register so that data frame signals having data contents are continuously transmitted, and an output of the memory means is transmitted to the main controller. And a second matching signal is not output from the second comparing means when the first matching signal is output from the first comparing means during reading from the memory means. Reads the data at the same predetermined address from the memory means until the second match signal is output, and restarts the data read from the start address when the second match signal is output. 1 and the second coincidence signal is output when the first coincidence signal is not being output. When the input data collation result is received by the main controller, the transmitting device includes: a second synchronization control unit that suspends the data reading and resumes the data reading from the start address when the input data matching result is received. In addition, the inspection device of the serial controller is characterized in that the input data collating function is inspected while changing the collation number N of the input data collating function in the main controller. 2. The serial controller inspection device according to claim 1, wherein the predetermined same address is a set value of the end address register. 3. Receiving means having a receiving memory for storing received serial data, serial / parallel converting means for converting serial data in the receiving memory into serial / parallel, and writing the serial / parallel converted received data. Stored in the transmission / reception memory, the main controller having a transmission / reception memory for reading out the stored transmission data of the parallel data, a transmission unit for converting the data read out from the transmission / reception memory into serial data, and transmitting the serial data; A host controller that outputs data to the main controller and receives received data written in the transmission / reception memory, the address bus of the reception memory, the address bus on the host controller side of the transmission / reception memory, and the transmission / reception memory The above In an inspection device of a serial control device for inspecting an abnormality of an address bus on the side of a transmission means and a reception means, a main inspection means for receiving the transmission data of the transmission means of the main controller and transmitting the data to a reception memory of the main controller is provided. In addition to connecting to the controller, the host controller writes the same data to all addresses of the transmission / reception memory of the main controller, sends the data to the inspection device via the transmission means of the main controller, and the inspection means transmits all of the transmission / reception memory. The first test to check whether the same data is written to the address and the same data is written to all addresses of the transmission / reception memory by transmitting the same data from the inspection means to the transmission / reception memory via the reception memory of the main controller , Normal writing is done The second check that checks with the host controller whether or not there is data, and all different data is stored for addresses where only one bit in the address bus of the transmission / reception memory has an output state different from other bits. And a third inspection in which the host controller inspects whether or not the storage is normally performed by transmitting data from the inspection means to the main controller, and the first, second and third inspections are performed. On the basis of the inspection result of (1), it is inspected which one of the address bus of the receiving memory, the address bus of the transmitting / receiving memory on the host controller side and the address bus of the transmitting / receiving memory of the transmitting / receiving memory has an abnormality. An inspection device for a serial control device characterized by the above.