JPH0496848A - Interface monitoring device - Google Patents

Abstract

PURPOSE:To surely detect the service response due to the malfunction of input/ output devices by storing a first normal response time and comparing second and following response times with the normal response time. CONSTITUTION:The first response time from a specific input/output device 6 is stored in a monitoring circuit 3b after an information request signal is generated to the specific input/output device 6 from an operation circuit 3a in a channel device 3; and if second and following response times are shorter than the stored response time, abnormality is decided. Thus, abnormality is detected if the response time is shorter than the reference response time because of the malfunction of another input/output device 6, and the service response due to the malfunction of input/output devices is surely detected.

Description

[Detailed Description of the Invention] [Summary] Regarding the current device, the present invention aims to detect a service response caused by a malfunction of an input/output device. In a system in which the input/output devices are connected in the same manner as the input/output devices are connected to the channel device, the channel device outputs the information request signal C1- into the channel device, and then 1) Provide a monitoring circuit that monitors the time until a service response signal is returned, and store the initial response time in the monitoring circuit. response 1
If the response time is shorter than the response time of 1if or Q, it is determined to be l/c'.

[Field of Industrial Application] The present invention relates to an interface monitoring device for monitoring differences in input/output devices.

There is a system in which the CPU, channel device, and input/output devices are connected via a lotus. In this type of device, a plurality of input/output devices are connected to the bus in a chain-like manner, so that malfunctions may cause the plurality of input/output devices to compete on the bus. If contention occurs on the bus, subsequent operations will be erroneous. Therefore, it is necessary to be able to reliably detect the occurrence of contention on the bus.

[Prior Art] FIG. 3 is a conceptual diagram of the configuration of a conventional system. In the figure, 1 is a CPU, 2 is a memory connected to the CPU, and 3 is a CPU.
is a channel device (CH) connected to the CPUI, and 4 is a buffer connected to the channel device 3. 5 is a bus connected to the channel device 3; Reference numeral 6 denotes a plurality of input/output devices (110) connected to the bus 5 in a cascading manner. .

In the system configured as described above, a data write command (write command) or a data read command (read command) from the CPU is outputted onto the bus controller via the channel device 3. After confirming that each input/output device 6 connected to the bus 5 is designated from the address on the lotus,
Write data or read data.

For example, in the case of reading data, the data read from the human power device 6 is transferred to the bus 5 and stored in the buffer 4 of the channel device 3 --EJI. Then, the channel device 3 finds free time of the CPU 1 and transfers the data stored in the buffer 4 to the memory 2 of the CPU 1.

Before exchanging such data, channel device 3
Information is exchanged between the input/output device 6 and the input/output device 6 as shown in FIG. First, the channel device 3 outputs a Hasbin signal (BBSY) as shown in (a). Then, as shown in (b), 11
0 machine number is established. After that, the channel device 3 (C)
An information request signal (SRVI) as shown in is sent to the lotus 5 soil.

When each input/output device 6 learns that it has been selected by checking the contents on the lotus 5, it sends a service response signal (SR 0) to the lotus 5 as shown in (d). Before that, status information must be established on the data bus (DB) as shown in (e).

[Problems to be Solved by the Invention] In the conventional method described above, each input/output device 6 or the city
Is there any problem when using γ7 and other input/output devices 6?
If the channel or device 3 malfunctions, it will respond at the wrong timing. This will be explained using FIG. It takes a certain amount of time after the information request signal 5RVI shown in (c) is output until the status information of the predetermined input/output device 6 is established on the bus 5. Therefore, originally, after the status information is established on the lotus 5, the service response signal 5RVO should be output. Therefore, 5RVI
After 5RVO is output, the 4th
As shown in the figure, a predetermined time T is required. However,
If another input/output device 6 malfunctions, it is likely that 5RVO will be output in a period T' that is much shorter than T, as shown in (d). When 5RVO is output, (
As shown in e'), status information is also not established.

Therefore, if the channel device 3 goes to check the contents of the lotus 5 at this timing, something strange will happen.

The present invention has been made in view of the second problem, and it is an object of the present invention to provide an interface monitoring device that can reliably detect service responses due to malfunctions of input/output devices.

[Method for solving the problem] FIG. 1 is a block diagram of the principle of the present invention. For items that are the same as Figure '3, the same initial numbers are changed to A, I, and J.
PU1. This system is composed of a channel device 3 and a plurality of input/output devices 6 connected to the channel device 3, and the input/output devices 6 are connected in a threaded manner to a lotus 5 connected to the channel device 3.

2 is a memory connected to the CPU], 4 is a channel device 3
is a buffer connected to 3a is an operating circuit that performs normal operation as a channel device, and 3b monitors the time from when the channel device 3 outputs the information request signal 5RVI until the service response signal 5RVO is returned from the corresponding input/output device 6. This is a monitoring circuit.

[Operation] The first response time from the input/output device 6 is monitored by the monitoring circuit 3b.
If the response time from the second time onward is shorter than the stored response time, it is determined that the response time is abnormal. As a result, a case where the response time is shorter than the reference response time due to malfunction of another input/output device 6 is detected as an abnormality, and a service response due to malfunction of the input/output device can be reliably detected.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing one embodiment of the present invention, in which the monitoring circuit 3
This shows the configuration of b. In the figure, 11 is a clock;
A 4-bit binary counter 12 receives 5RVI and 5RVO, and 12 is a plurality of (n-16) inputs that invert the 4-bit output of the counter 11 as necessary for each bit.
) is an AND gate. Counter 11 is 5RVI
or when the clock is manually operated, start counting the clock and 5RVO.
Counting is stopped when the number is manually input.

As the counter 1, for example, 5N74161 is used.

The number of AND gates 12 is the same as the number of turnout devices 6 connected to the channel device 3. In response to the fact that the response time T of each input/output device 6 is different, 16 units are provided in order to set the response time T for each input/output device 6.

13 is a flip-flop (FF) that latches the output of each AND gate 12 with a launch pulse, and 14 is a time information storage circuit that manually inputs the output of these flip-flops 13. 5 is a pulse output circuit that creates a pulse by differentiating the rising edge of 5RVO, and its output is given to the flip-flop 3 as the latch pulse. Time information storage circuit] 4 is 5RVO from the rising edge of 5RVI
The time until the rise (response time) is memorized. and once [response time of I and twice [-1
Subsequent response times are compared and a signal corresponding to the comparison result is output. The operation of the circuit configured as described above will be explained as follows.

When an information request 5RVI is generated from the operation circuit 3a in the channel device 3 to a specific input/output device 6, the counter 1
1 starts counting the clock. When the service response signal 5RVO is generated from the input/output device 6 after a suitable predetermined period of time, the clock count of the counter 1 is stopped. When the counting operation of the counter 11 stops, there is always one anchor 12 whose output becomes '1''.
I do it. 5 outputs of each flip-flop 13
is latched to.

The output of each flip-flop 13 is the time information storage circuit 14.
to go into. The time information storage circuit [4] is 1? from when SRVI rises until it receives the output of the flip-flop [3]. ? J (response "r 1347)" and memorize the period T. Here, the first response time T
It will be remembered. Next, the response times after 2 times [-1 are also written tθ in the same manner. Here, the time information storage circuit]4 compares the first period T and the period T' from the second time 11 onward. If it is T-T-, it can be determined that it is a service response from the input/output device 6 that is [1].

here,? °, If T < T, the received SR
It can be determined that the VO is from the malfunctioning input/output device 6. Therefore, in this case, the operation circuit 3a (Figure 1' = !T<!) receives the abnormality response signal from the monitoring circuit 3b and performs abnormality processing.

In the above embodiment, a 4-bit binary counter is used as the counter 11, but the present invention is not limited to this, and a counter with an arbitrary number of bits can be used depending on the number of input/output devices. Furthermore, by storing the response times of all input/output devices in the time information storage circuit 14, it becomes possible to determine the normality of the service response regardless of which input/output device is accessed. .

[Effects of the Invention] As described above in detail, according to the present invention, the first normal response time is memorized and the input/output is performed by comparing the second and subsequent response times with the normal response times. Service responses due to device malfunction can be reliably detected.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention, Fig. 3 is a conceptual diagram of the configuration of a conventional system, and Fig. 4 is a time chart showing the operation of the conventional system. FIG. 5 is a time chart at the time of malfunction. In Figure 1, 1 is a CPU. 2 is a memory, 3 is a channel device, 3a is an operating circuit, 3b is a monitoring circuit, 4 is a buffer, 5 is a lotus, and 6 is an input/output device. Patent applicant Fujitsu Ltd.

Claims (1)

[Claims] Consisting of a CPU (1), a channel device (3), and a plurality of input/output devices (6) connected to the channel device (3), and connected to the channel device (3). In a system in which input/output devices (6) are connected to a bus (5) in a series, the channel device (3) outputs an information request signal into the channel device (3), and then the corresponding input/output device (6) A monitoring circuit (3b) is provided for monitoring the time from 1 to 3 until a service response signal is returned, the first response time is stored in the monitoring circuit (3b), and the second and subsequent response times are stored in the monitoring circuit (3b). 1. An interface monitoring device characterized in that the interface monitoring device is configured to determine that there is an abnormality if the response time is shorter than the specified response time.