JPH04143690A - Radiation identification circuit and electronic circuit used for it - Google Patents

Radiation identification circuit and electronic circuit used for it

Info

Publication number
JPH04143690A
JPH04143690A JP2266828A JP26682890A JPH04143690A JP H04143690 A JPH04143690 A JP H04143690A JP 2266828 A JP2266828 A JP 2266828A JP 26682890 A JP26682890 A JP 26682890A JP H04143690 A JPH04143690 A JP H04143690A
Authority
JP
Japan
Prior art keywords
error
circuit
data
radiation
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2266828A
Other languages
Japanese (ja)
Other versions
JP2699640B2 (en
Inventor
Koichiro Yamamura
山村 耕一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2266828A priority Critical patent/JP2699640B2/en
Publication of JPH04143690A publication Critical patent/JPH04143690A/en
Application granted granted Critical
Publication of JP2699640B2 publication Critical patent/JP2699640B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Measurement Of Radiation (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)
  • Light Receiving Elements (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To make possible the identification of a radiation dose to contrive the modification of redundancy of the same dose by generating an error signal when the error bit read from a memory storing specified data reaches specified number. CONSTITUTION:An address control circuit 1 increases an address according to a clock signal to supply an SRAM 3. A data control circuit 2 makes a light enable VE signal zero to make the SRAM 3 a write state to write data in each bit successively and, if they are written, the VE signal is made 1 to be in a read state. At this time the circuit 1 reads the data of the whole bit of the SRAM 3 according to the clock signal. During this time the circuit 2 detects the error bit of read data to count the number and, when the number of the generation of the error bit becomes specified predeterminated value, the error signal is generated. Further, the sensitivity of a circuit for radiation can be changed by changing the value of operating voltage Vcc. In addition, the threshold for counting the number of error bits had better be changed.

Description

【発明の詳細な説明】 技術分野 本発明は放射線認識回路及びそれを用いた電子回路に関
し、特に宇宙線量の増減の大きい宇宙空間で使用される
電子回路に用いて好適な放射線認識回路に関するもので
ある。
[Detailed Description of the Invention] Technical Field The present invention relates to a radiation recognition circuit and an electronic circuit using the same, and particularly relates to a radiation recognition circuit suitable for use in an electronic circuit used in outer space where the amount of cosmic radiation varies greatly. be.

従来技術 通信衛星等宇宙空間で使用される電子機器においては、
放射線、例えばα線量の増減が大きいために、設計の際
に最悪の状況を想定する必要がある。そのために、実際
の使用環境では十分すぎる冗長性をハードウェア的に備
えておく必要が生じる。
Conventional technology In electronic equipment used in outer space such as communication satellites,
Because the radiation dose, for example alpha radiation, varies greatly, it is necessary to assume the worst-case scenario when designing. Therefore, it is necessary to provide hardware with sufficient redundancy in the actual usage environment.

また、不良が発生した場合、この不良が使用環境におけ
るα線量によるものか、他の要因によるものかの判別が
困難であり、その不良解析に時間がかかるという欠点が
ある。
Furthermore, when a defect occurs, it is difficult to determine whether the defect is due to the α-ray dose in the usage environment or other factors, and it takes time to analyze the defect.

発明の目的 そこで、本発明はこの様な従来技術の欠点を解決すべく
なされたものであって、その目的とするところは、α線
等の放射線量の認識をなすことが可能な放射線認識回路
を提供することにある。
Purpose of the Invention The present invention has been made to solve the drawbacks of the prior art, and its purpose is to provide a radiation recognition circuit that can recognize the amount of radiation such as alpha rays. Our goal is to provide the following.

本発明の他の目的は、放射線量の認識を可能として、こ
の認識された結果に応じて回路の冗長性を変更できるよ
うにした電子回路を提供することである。
Another object of the invention is to provide an electronic circuit which allows radiation dose to be recognized and the redundancy of the circuit to be changed in response to this recognized result.

発明の構成 本発明による放射線認識回路は、所定データを予め格納
したメモリと、前記メモリから順次データを読出す読出
し制御手段と、この読出しデータのエラーピットを検出
してこのエラーピットが所定数に達したときにエラー出
力を発生するエラー検出手段とを含み、前記エラー出力
により放射線量の認識をなすようにしたことを特徴とし
ている。
Structure of the Invention The radiation recognition circuit according to the present invention includes a memory in which predetermined data is stored in advance, read control means for sequentially reading data from the memory, and detecting error pits in the read data so that the number of error pits reaches a predetermined number. It is characterized in that it includes an error detection means that generates an error output when the radiation dose is reached, and the radiation dose is recognized based on the error output.

本発明による電子回路は、放射線に対する信頼性を向上
させるべく設けられた冗長回路と、所定データを予め格
納したメモリ、前記メモリから順次データを読出す読出
し制御手段、この読出しデータのエラーピットを検出し
てこのエラーピットが所定数に達したときにエラー出力
を発生するエラー検出手段からなる放射線検出回路と、
前記エラー出力に応じて前記冗長回路の冗長性を変更制
御する制御手段とを含むことを特徴としている。
The electronic circuit according to the present invention includes a redundant circuit provided to improve reliability against radiation, a memory in which predetermined data is stored in advance, a read control means for sequentially reading data from the memory, and detecting error pits in the read data. a radiation detection circuit comprising an error detection means that generates an error output when the number of error pits reaches a predetermined number;
The apparatus is characterized in that it includes a control means for changing and controlling the redundancy of the redundant circuit in accordance with the error output.

実施例 次に本発明について図面を用いて説明する。Example Next, the present invention will be explained using the drawings.

第1図は本発明の実施例によるα線認識回路のブロック
図である。アドレス制御回路1はクロック信号に同期し
てSRAM 3のアドレスを初期値“0゜から順次イン
クリメントして生成するものである。
FIG. 1 is a block diagram of an α-ray recognition circuit according to an embodiment of the present invention. The address control circuit 1 generates addresses of the SRAM 3 by sequentially incrementing them from an initial value "0°" in synchronization with a clock signal.

データ制御回路2はクロック信号に同期してSl?AM
3に対してデータの書込み読出し制御を行うものであり
、データ書込み時には予め定められたブタパターン(本
例ではオール“0゛)を書込む。
Data control circuit 2 synchronizes with the clock signal and outputs Sl? A.M.
3, and when writing data, a predetermined pig pattern (all "0" in this example) is written.

また、データ読出し時には、エラーピットの有無を検出
して、そのエラーピットの数に応じてエラー信号出力を
生成するものである。
Furthermore, when reading data, the presence or absence of error pits is detected and an error signal output is generated according to the number of error pits.

SRAM (スタティックランダムアクセスメモリ)3
は動作電源をVccとするメモリICであり、α線に対
して弱いメモリとする必要がある。具体的には、メモリ
ICパッケージが薄く、セルの保持電荷が小さいものを
選んでおく必要がある。
SRAM (Static Random Access Memory) 3
is a memory IC whose operating power supply is Vcc, and the memory needs to be weak against alpha rays. Specifically, it is necessary to select a memory IC package that is thin and holds a small amount of charge in the cell.

かかる構成において、クロック信号に従ってアドレス制
御回路1はアドレスを“0”から1づつインクリメント
してSRAM3へ供給する。データ制御回路2はWE(
ライトイネーブル)信号を“0゜としてSRAM 3を
書込み状態に制御し、上記アドレスに従ってSRAM 
3の各ビットに順次“0”ノテータを書込んでいく。
In this configuration, the address control circuit 1 increments the address by 1 from "0" according to the clock signal and supplies the incremented address to the SRAM 3. The data control circuit 2 is WE(
The write enable) signal is set to “0°” to control SRAM 3 to write state, and the SRAM 3 is written according to the above address.
A "0" notator is sequentially written to each bit of 3.

データ制御回路2は、SRAM 3の全ビットに“0”
が書込まれたら、その後にWE倍信号“1”として読出
し状態とする。このとき、アドレス制御回路1はクロッ
ク信号に従って再びアドレスを“O゛から順次1づつイ
ンクリメントし、SRAM 3の全ビットのデータを読
出すのである。
Data control circuit 2 sets all bits of SRAM 3 to “0”
After writing, the WE multiplication signal is set to "1" and the state is set to read. At this time, the address control circuit 1 again sequentially increments the address by 1 from "O" according to the clock signal, and reads out data of all bits of the SRAM 3.

この間データ制御回路2は読出しデータのエラーピット
を検出しており、“1”があればSRAM 3のデータ
が変化したことになるので、このエラーピットの発生数
をカウントする。このエラーピット発生数が予め定めら
れた1以上の所定値になると、エラー信号として外部へ
報告されるようになっている。
During this time, the data control circuit 2 detects error pits in the read data, and if "1" is detected, it means that the data in the SRAM 3 has changed, so the number of occurrences of these error pits is counted. When the number of error pits that occur reaches a predetermined value of 1 or more, it is reported to the outside as an error signal.

SRAM 3のα線耐量は動作電圧Vccに依存して大
きく変化するので、VCCの電圧値を変化させることに
よりα線に対する回路の感度を変えることができる。ま
た、エラーピットの発生数をカウントする閾値を変化さ
せるようにしても良い。
Since the α-ray resistance of the SRAM 3 varies greatly depending on the operating voltage Vcc, the sensitivity of the circuit to α-rays can be changed by changing the voltage value of VCC. Further, the threshold value for counting the number of error pits may be changed.

第2図は第1図のα線認識回路を用いた本発明の実施例
による電子回路のブロック図である。本実施例の電子回
路は、第1図に示したα線認識部10と、アドレス制御
部11と、メモリI C12゜13と、データ制御部1
4とからなっている。
FIG. 2 is a block diagram of an electronic circuit according to an embodiment of the present invention using the α-ray recognition circuit of FIG. The electronic circuit of this embodiment includes an α-ray recognition section 10, an address control section 11, a memory IC 12゜13, and a data control section 1 shown in FIG.
It consists of 4.

α線認識部10によりエラー信号が発生されていない場
合、アドレス制御部11及びデータ制御部14は共にメ
モリIC12,13を別のアドレス空間のメモリとして
認識しており、上位アドレスによりC8(チップセレク
ト)信号を生成してメモリIC12,13のいずれかの
アドレス空間を選択的にアクセス自在となっている。
When no error signal is generated by the α-ray recognition unit 10, the address control unit 11 and the data control unit 14 recognize the memory ICs 12 and 13 as memories in different address spaces, and the upper address indicates C8 (chip select ) signal can be generated to selectively access the address space of either memory IC 12 or 13.

α認識部10においてエラー信号が発生された場合、α
線が多いと認識されることから、回路全体を高信頼性モ
ードとする必要がある。
When an error signal is generated in the α recognition unit 10, α
Since it is recognized that there are many lines, the entire circuit needs to be in high reliability mode.

そこで、先ずメモリICl3の内容を外部装置に転送し
、メモリIC12の内容をメモリICl3にコピーする
処理を行う。そして、アドレス制御部11及びデータ制
御部14はメモリIC12と13とを同一のアドレス空
間を有するメモリと認識し、C8信号を両方共同−とみ
なしてアクセス処理を行うようにするのである。
Therefore, first, the contents of the memory ICl3 are transferred to an external device, and the contents of the memory IC12 are copied to the memory ICl3. Then, the address control section 11 and the data control section 14 recognize the memory ICs 12 and 13 as memories having the same address space, and perform access processing by regarding both of the C8 signals as common.

従って、メモリIC12と13とは二重化された状態と
なり冗長性が増大して、信頼性が向上する。よって、両
メモリICから読出したデータが互いに異なる場合には
、パリティによりエラー発生した方のデータを無視し、
正しい方のデータを外部へ読出すようにする。エラー発
生したデータは書直しておくことは勿論である。
Therefore, the memory ICs 12 and 13 are in a duplex state, increasing redundancy and improving reliability. Therefore, if the data read from both memory ICs are different from each other, the data in which the error occurred is ignored due to parity,
Read the correct data to the outside. Of course, data in which an error has occurred should be rewritten.

データ書込み時には両メモリICには同一のデータを書
込むことになり、従って通常の動作時と比較してアドレ
ス空間は半分になるものの信頼性は倍に向上する。
When data is written, the same data is written to both memory ICs, and therefore, although the address space is halved compared to normal operation, reliability is doubled.

尚、上記実施例ではα線認識回路をメモリ装置に適用し
た例を示したが、他の電子回路に適用できることは明ら
かである。また、α線の認識を例に説明したが他の放射
線であっても良い。
Incidentally, in the above embodiment, an example was shown in which the α-ray recognition circuit was applied to a memory device, but it is obvious that the invention can be applied to other electronic circuits. Further, although the explanation has been given using the recognition of alpha rays as an example, other radiations may be used.

発明の効果 叙上の如く、本発明によれば、メモリICを放射線認識
のために用い、そのメモリビットのエラー発生状態に応
じて外部環境の放射線量を認識することができるので、
それに対処するハードウェアの構成を変更できるという
効果がある。
Effects of the Invention As described above, according to the present invention, a memory IC is used for radiation recognition, and the radiation dose in the external environment can be recognized according to the error occurrence state of the memory bit.
This has the effect of being able to change the hardware configuration to deal with it.

特に、放射線認識部を放射線がシールドされていない外
部に設置し、電子回路に使用されているICよりも更に
放射線耐力が弱いICをその放射線認識部に使用すれば
、その認識結果に応じて回路の信頼性を変更制御できる
ことになり、回路の外部からの放射線による誤動作を未
然に防止でき、外部環境による不具合を切分けることが
容易になる。
In particular, if the radiation recognition section is installed outside where radiation is not shielded, and an IC with lower radiation resistance than the IC used in the electronic circuit is used in the radiation recognition section, the circuit will be activated depending on the recognition result. This makes it possible to change and control the reliability of the circuit, preventing malfunctions caused by radiation from outside the circuit, and making it easier to isolate problems caused by the external environment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の回路ブロック図、第2図は第
1図の回路を用いた電子回路のプロ・ツク図である。 主要部分の符号の説明 1・・・・・・アドレス制御回路 2・・・・・・データ制御回路 3・・・・・・SRAM 10・・・・・・α線認識部 12.13・・・・・・メモリIC
FIG. 1 is a circuit block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an electronic circuit using the circuit of FIG. Explanation of symbols of main parts 1... Address control circuit 2... Data control circuit 3... SRAM 10... Alpha ray recognition unit 12.13... ...Memory IC

Claims (3)

【特許請求の範囲】[Claims] (1)所定データを予め格納したメモリと、前記メモリ
から順次データを読出す読出し制御手段と、この読出し
データのエラービットを検出してこのエラービットが所
定数に達したときにエラー出力を発生するエラー検出手
段とを含み、前記エラー出力により放射線の認識をなす
ようにしたことを特徴とする放射線認識回路。
(1) A memory that stores predetermined data in advance, a read control means that sequentially reads data from the memory, detects error bits in the read data, and generates an error output when the number of error bits reaches a predetermined number. What is claimed is: 1. A radiation recognition circuit comprising: an error detection means for detecting radiation, and recognizing radiation based on the error output.
(2)前記メモリの動作電源を変化自在として放射線に
対する感度を制御自在としたことを特徴とする請求項1
記載の放射線認識回路。
(2) Claim 1 characterized in that the operating power source of the memory is freely changeable so that the sensitivity to radiation can be freely controlled.
The radiation recognition circuit described.
(3)放射線に対する信頼性を向上させるべく設けられ
た冗長回路と、 所定データを予め格納したメモリ、前記メモリから順次
データを読出す読出し制御手段、この読出しデータのエ
ラービットを検出してこのエラービットが所定数に達し
たときにエラー出力を発生するエラー検出手段からなる
放射線検出回路と、前記エラー出力に応じて前記冗長回
路の冗長性を変更制御する制御手段とを含むことを特徴
とする電子回路。
(3) A redundant circuit provided to improve reliability against radiation, a memory that stores predetermined data in advance, a read control means that sequentially reads data from the memory, and a system that detects error bits of this read data and detects errors. A radiation detection circuit comprising an error detection means that generates an error output when the number of bits reaches a predetermined number, and a control means that changes and controls the redundancy of the redundant circuit in accordance with the error output. electronic circuit.
JP2266828A 1990-10-04 1990-10-04 Electronic circuit using radiation recognition circuit Expired - Lifetime JP2699640B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2266828A JP2699640B2 (en) 1990-10-04 1990-10-04 Electronic circuit using radiation recognition circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2266828A JP2699640B2 (en) 1990-10-04 1990-10-04 Electronic circuit using radiation recognition circuit

Publications (2)

Publication Number Publication Date
JPH04143690A true JPH04143690A (en) 1992-05-18
JP2699640B2 JP2699640B2 (en) 1998-01-19

Family

ID=17436218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2266828A Expired - Lifetime JP2699640B2 (en) 1990-10-04 1990-10-04 Electronic circuit using radiation recognition circuit

Country Status (1)

Country Link
JP (1) JP2699640B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102087882A (en) * 2009-12-02 2011-06-08 Lsi公司 Closed-loop soft error rate sensitivity control
JP2018049610A (en) * 2016-09-16 2018-03-29 株式会社半導体エネルギー研究所 Semiconductor device, electronic apparatus and driving method thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7499308B2 (en) * 2007-03-21 2009-03-03 International Business Machines Corporation Programmable heavy-ion sensing device for accelerated DRAM soft error detection

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251284U (en) * 1985-09-20 1987-03-30
JPS63124987A (en) * 1986-11-14 1988-05-28 Nec Corp Alpha-ray detector using multidimensional semiconductor
JPS6433087U (en) * 1987-08-21 1989-03-01

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6251284U (en) * 1985-09-20 1987-03-30
JPS63124987A (en) * 1986-11-14 1988-05-28 Nec Corp Alpha-ray detector using multidimensional semiconductor
JPS6433087U (en) * 1987-08-21 1989-03-01

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102087882A (en) * 2009-12-02 2011-06-08 Lsi公司 Closed-loop soft error rate sensitivity control
JP2011118856A (en) * 2009-12-02 2011-06-16 Lsi Corp Closed-loop soft error rate sensitivity control
JP2018049610A (en) * 2016-09-16 2018-03-29 株式会社半導体エネルギー研究所 Semiconductor device, electronic apparatus and driving method thereof

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Publication number Publication date
JP2699640B2 (en) 1998-01-19

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