JPH0423321Y2 - - Google Patents
Info
- Publication number
 - JPH0423321Y2 JPH0423321Y2 JP438186U JP438186U JPH0423321Y2 JP H0423321 Y2 JPH0423321 Y2 JP H0423321Y2 JP 438186 U JP438186 U JP 438186U JP 438186 U JP438186 U JP 438186U JP H0423321 Y2 JPH0423321 Y2 JP H0423321Y2
 - Authority
 - JP
 - Japan
 - Prior art keywords
 - substrates
 - insulating film
 - conductive path
 - press
 - copper foil
 - Prior art date
 - Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 - Expired
 
Links
Classifications
- 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/4805—Shape
 - H01L2224/4809—Loop shape
 - H01L2224/48091—Arched
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/481—Disposition
 - H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
 - H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
 - H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
 
 - 
        
- H—ELECTRICITY
 - H01—ELECTRIC ELEMENTS
 - H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
 - H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
 - H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
 - H01L2224/42—Wire connectors; Manufacturing methods related thereto
 - H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
 - H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
 - H01L2224/481—Disposition
 - H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
 - H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
 - H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
 - H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
 
 
Landscapes
- Wire Bonding (AREA)
 
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP438186U JPH0423321Y2 (instruction) | 1986-01-16 | 1986-01-16 | 
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title | 
|---|---|---|---|
| JP438186U JPH0423321Y2 (instruction) | 1986-01-16 | 1986-01-16 | 
Publications (2)
| Publication Number | Publication Date | 
|---|---|
| JPS62116545U JPS62116545U (instruction) | 1987-07-24 | 
| JPH0423321Y2 true JPH0423321Y2 (instruction) | 1992-05-29 | 
Family
ID=30784995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date | 
|---|---|---|---|
| JP438186U Expired JPH0423321Y2 (instruction) | 1986-01-16 | 1986-01-16 | 
Country Status (1)
| Country | Link | 
|---|---|
| JP (1) | JPH0423321Y2 (instruction) | 
- 
        1986
        
- 1986-01-16 JP JP438186U patent/JPH0423321Y2/ja not_active Expired
 
 
Also Published As
| Publication number | Publication date | 
|---|---|
| JPS62116545U (instruction) | 1987-07-24 | 
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