JPH0423299A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To improve reliability and maintainability for the whole device in addition to cost reduction by performing data setting on an address decoder circuit without preparing an out-fitted component and performing it programmably by the control of a CPU. CONSTITUTION:A signal inputted to an address input terminal 2 is held with a data latch 4. Thence, data held with the data latch 4 is written on a nonvolatile memory cell 6 via a read/write control circuit 5. After write is completed, an address input signal is fetched, and when it coincides with address input decided in advance, set data read in the cell 6 is read out by operating the read/write control circuit 5, and is sent to one of two pairs of input terminal groups in a coincidence decision circuit 7. The input terminal on the other side of the coincidence decision circuit 7 is connected to the terminal 2, and coincidence decision for both signal groups is performed, and a result output signal, the inverse of OUT is outputted to a decode output terminal 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory device using an electrically rewritable nonvolatile memory element.

[Summary of the invention]

In a semiconductor non-volatile memory device consisting of an electrically rewritable non-volatile memory element, this invention uses a non-volatile The nonvolatile memory element is connected to the nonvolatile memory element, and writing to the nonvolatile memory element is started by constantly monitoring the other signal line input and detecting a change in a predetermined input signal. This allows the signal data on the side connected to to be freely set.

[Conventional technology]

Determining whether or not two sets of signal lines each having a length of several bits match or differ is required to configure a circuit that generates a selection signal for a connected peripheral device, especially in equipment using CPV. . The selection operation is called address decoding, and the general-purpose IC used for it is called address decoding 1C.

Conventionally, circuits used for address decoding include those that combine a switch with mechanical contacts and a general-purpose IC for digital signal matching, and a general-purpose nonvolatile memory IJ.
A device using IC was known.

FIG. 2 shows a first example of a conventional address decoding circuit. An outline of the operation will be explained below based on the drawings. The match determination 1cII is a general-purpose IC that determines the match between two sets of signal inputs of hide (8 bits) length. One address input terminal 2 of the two sets of signal inputs is connected to the address bus output from CPv. The other signal input is normally connected to a data setting circuit consisting of a DIP switch 9 and a resistor array 10. In this circuit configuration, the 1-byte data set by the data setting circuit and the signal on the address bus of the CPv connected to the address input terminal 2 are constantly compared, and if they match, a match signal is output from the decode output terminal 8. be done.

FIG. 3 shows a second example of a conventional address decoding circuit, which uses a general-purpose nonvolatile memory Ic. As in the first example, one input of the match determination 1cII is connected to the address bus 15 output by the CPv.
The other signal input is connected to the data output terminal of the non-volatile memory ICI2. In addition, a data bus 14 is connected via a transceiver 17 to write and read data into and from the nonvolatile memory 1c12, and an address decoding ICl3 is used to generate a signal for selecting the nonvolatile memory ICI2. There is. In such a circuit configuration, the data settings required for address decoding are c
This is done by writing data to the nonvolatile memory 1c12 under the control of pv. and control signal line group 16
By operating the non-volatile memory IJIC12 and putting it in a read state, the signals on the address bus 15 are constantly compared by the match determination 1cII, and if they match, a match signal is output from the decode output terminal 8.

Problems to be Solved by Invention C] However, since conventional address decoding circuits use switches with mechanical contacts, in addition to deterioration in reliability due to poor contact and aging, the switch also suffers from Depending on the setting conditions, current will always flow through the resistor array, which is not suitable for reducing power consumption. Furthermore, in order to change data settings, it is necessary to operate a DIP switch, and the device may have to be stopped each time to insert or remove a circuit board. In order to solve these drawbacks, the conventional address decoding circuit replaces the setting part with a general-purpose nonvolatile memory, but in order to control the nonvolatile memory IC, a new address decoding IC is added.
In addition, a transceiver is required, and the number of signal wires to these two ICs increases, the load on the data bus and address bus becomes heavier, making it difficult to design a CPv system especially in high-speed operation areas, and control signal lines also increase. ! It gets messy. Furthermore, both when using a DIR switch and resistor array and when using a general-purpose non-volatile memory IC, the number of parts is large, resulting in cost reductions due to space savings, improved mounting density, and reduced mounting man-hours.

This is extremely unsuitable for improving reliability.

In order to solve these conventional drawbacks, this invention does not require any external parts, has a small number of signal wires, and does not require connecting or disconnecting the circuit board to set data.
The object of the present invention is to provide a semiconductor nonvolatile memory that is programmable by controlling CPv.

[Means to solve the problem]

In order to solve the above problems, the present invention uses a non-volatile memory element to store and hold setting data, and also provides an address input monitoring circuit, and inputs the writing of the non-volatile memory element to the -m address input terminal. This is done by constantly monitoring the input signal and detecting changes in the predetermined input signal.

[For production]

In the semiconductor nonvolatile memory device configured as described above, the address input monitoring circuit constantly monitors changes in the address bus, detects a specific address change pattern, and converts a series of subsequent address input signals into a non-volatile state. The address input monitoring circuit continues to monitor the address bus and outputs the predetermined address input signal. starts address decoding.

The above operation sets the address decode data to CP.
The number of terminals required for this semiconductor non-volatile memory device is minimized by programmably controlling v and by importing setting data from the - set of address input terminals.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a nonvolatile memory device of the present invention. The device selection input terminal 1 to which the signal SEL is input and the 8-bit address input terminal 2 are connected to the address input monitoring circuit 3, and when the signal SEL is in the active state (“L” in this embodiment), It monitors the address input, and by detecting, for example, that the same address input is repeated twice, the next signal input to the address input terminal 2 is taken in as setting data to be written to the nonvolatile memory element. Further, the next address input signal is taken in as function setting data and each is held in the data latch 4. The data held in the data latch 4 is then written into the nonvolatile memory element 6 through the write/read control circuit 5. At this time, the high voltage pulse train and timing required for writing to the nonvolatile memory element are generated within the nonvolatile memory device of the present invention. After writing is completed, the address input signal is fetched, and if it is the same as the predetermined address input (in this embodiment, two successive address inputs), the address input signal is written to the nonvolatile memory element 6. The setting button is written, the readout control circuit 5 is activated, the readout data is sent to one of the two sets of input terminal groups of the match determination circuit 7. - The other input terminal of the defeat determination circuit 7 is connected to the address input terminal 2, performs a match determination between both signal groups, and outputs the resulting output signal OUT to the decode output terminal 8.

FIG. 4 is an operation timing chart explaining the above operation.

In this embodiment, the specific address change Bakun is based on the condition that the same address is input twice consecutively, but the condition is not limited to this, and in VTL using CPV, the address bus A cycle would be more ideal. To connect an actual CPV in a device, simply connect the output terminal of the CPV that outputs the memory read signal or I10 read signal to the device selection input terminal 1, and connect the address bus to the address input terminal 2. That's fine. The reason why the memory read signal or I10 read signal is used here is to avoid affecting other peripheral devices in the device using CPV.

In the operation timing diagram, decode setting data is taken in state T3 and function setting data is taken in state T4, but the function setting data is necessary for the following uses. First, if the bit length of the data to be decoded is not required to be 8 bits, part of the bit string must be invalidated in the match determination. Therefore, the bit string validity/invalidity information is taken in from the above function setting data. FIG. 5 shows an embodiment of a coincidence determination circuit that incorporates valid/invalid bit strings.

Second, when a plurality of nonvolatile memory devices of the present invention are used in a device using cpv, one or any desired memory device from among the plurality of memory devices of the present invention is used.
You need to choose. In such a case, state T4
Using the function setting data imported with i! Each time you choose. From the above, there are cases where the function setting data requires more data than the bit length that can be imported with one address input, but in such cases, the function setting data cannot be imported at T4. Next,
Furthermore, this can be easily realized by adding function setting data. Therefore, in the present invention, the captured data length and
There is no special limit on the number of data.

The only manual signals required for the woodworking volatile memory device are the SEL input to the device selection input terminal and the address input signal input to the address input terminal, so conventional DIP
Address decoding circuits using switches and resistor arrays can be easily replaced.

〔Effect of the invention〕

As explained above, the present invention provides an address lever 1 circuit without external components, with a small number of signal wires, and by programmably setting data under the control of CPv, reducing the number of components, saving space, and In addition to cost reductions due to improved density and reduced mounting man-hours, this device has the effect of improving reliability and maintainability of the entire device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a semiconductor nonvolatile memory device of the present invention, FIGS. 2 and 3 are circuit diagrams showing conventional address decoding circuits, and FIG. 4 is a semiconductor nonvolatile memory device of the present invention. FIG. 5, which is an operation timing diagram of an embodiment of the device, is a match determination circuit diagram in a semiconductor nonvolatile memory device according to the present invention. 1 ・ 2 ・ ・ 4 ・ ・ 5 ・ ・ 6 ・ ・ 7 ・ 8 ・ 9 ・ ・ 11 ・ 12 ・ 13 ・ 14 ・ 16 ・ Device selection input terminal Address input terminal Address input monitoring circuit Data latch write and read control circuit Non-volatile memory element / Match judgment circuit Decode output terminal / DIP switch / Resistor array / RC for match judgment / Non-volatile memory IC / 1c for address decoding / Data latch / Address bus / Control signal line group・Path transceiver - 27 doss input pigeon tongue 1,4 reeds ・) 1 Memory device a-diagram (Hikira's Godsis 1゛ circuit diagram ¥2

Claims (1)

[Claims] In a semiconductor nonvolatile memory device consisting of an electrically rewritable nonvolatile memory element, one signal line is connected to the nonvolatile memory element to determine whether two sets of signal lines each having a length of several bits match. In addition, writing to the nonvolatile memory element is performed by constantly monitoring the input state of the other signal line of the two sets of signal lines and detecting a change in a predetermined input signal. semiconductor non-volatile memory device.