JPH0423147U - - Google Patents

Info

Publication number
JPH0423147U
JPH0423147U JP6530590U JP6530590U JPH0423147U JP H0423147 U JPH0423147 U JP H0423147U JP 6530590 U JP6530590 U JP 6530590U JP 6530590 U JP6530590 U JP 6530590U JP H0423147 U JPH0423147 U JP H0423147U
Authority
JP
Japan
Prior art keywords
layer
conductivity type
buried
semiconductor
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6530590U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6530590U priority Critical patent/JPH0423147U/ja
Publication of JPH0423147U publication Critical patent/JPH0423147U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す構成説明図、
第２図は本考案の埋め込み部の概略製造工程を示
す図、第３図、第４図は本考案を利用した電源構
成図、第５図は従来装置の構成説明図、第６図は
従来の電源構成図である。 １……基板、２……埋込層（ＢＮ＋，ＢＰ＋）
、３……ウエル、１０ａ〜１０ｄ……レジスト、
１１……Ｎ型単結晶層。

Claims (1)

    【実用新案登録請求の範囲】
  1. 同一基板上に一導電型の半導体層と逆導電型の
    半導体層が埋め込まれ、その埋め込み層の上に同
    導電型のウエル層が形成され、そのウエル層上に
    バイポーラトランジスタとＮチヤンネルＭＯＳＦ
    ＥＴが混載された半導体装置において、前記Ｎチ
    ヤンネルＭＯＳＦＥＴの下に形成される埋め込み
    層をＮ＋層で構成したことを特徴とする半導体装
    置。
JP6530590U 1990-06-20 1990-06-20 Pending JPH0423147U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6530590U JPH0423147U (ja) 1990-06-20 1990-06-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6530590U JPH0423147U (ja) 1990-06-20 1990-06-20

Publications (1)

Publication Number Publication Date
JPH0423147U true JPH0423147U (ja) 1992-02-26

Family

ID=31597016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6530590U Pending JPH0423147U (ja) 1990-06-20 1990-06-20

Country Status (1)

Country Link
JP (1) JPH0423147U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199612A (ja) * 1995-12-30 1997-07-31 Lg Semicon Co Ltd 半導体素子の三重ウェル形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119958A (ja) * 1985-11-20 1987-06-01 Hitachi Ltd 半導体装置
JPH022155A (ja) * 1988-06-13 1990-01-08 Mitsubishi Electric Corp 半導体集積回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62119958A (ja) * 1985-11-20 1987-06-01 Hitachi Ltd 半導体装置
JPH022155A (ja) * 1988-06-13 1990-01-08 Mitsubishi Electric Corp 半導体集積回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09199612A (ja) * 1995-12-30 1997-07-31 Lg Semicon Co Ltd 半導体素子の三重ウェル形成方法

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