JPH04229716A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and a temperature rise due to a Joule heat. CONSTITUTION:With respect to the output buffer circuit employing a 1st final stage transistor(TR) T1 switching its output to an H state and a 2nd final stage TR T2 switching its output to an L state, a 1st pre-driver 10 delays a changeover of the 1st final stage TR T1 from OFF to ON state more than a changeover of the 2nd final stage TR T2 from ON to OFF state. A 2nd pre-driver 20 delays a changeover of the 2nd final stage TR T2 from OFF to ON state more than a changeover of the 1st final stage TR T1 from ON to OFF state. The delay employs a transient transition of a voltage or a current of an input signal caused at the changeover of the logic state of the input signal. Thus, the simultaneous ON state of the 1st final stage TR T1 and the 2nd final stage TR T2 is reduced.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to an output buffer circuit using final stage transistors, including a first final stage transistor that switches the output to an H state and a second final stage transistor that switches the output to an L state. In particular, the present invention relates to an output buffer circuit that can reduce power consumption and temperature rise due to Joule heat.

0002

2. Description of the Related Art A logic gate, which is a digital circuit that performs a binary logic operation, outputs two electrical states through an output circuit as a result of the logic operation.

[0003] Normally, these two electrical states are output as two types of voltage values. That is, logical value “0”
Low voltage state (or OV voltage state, hereinafter referred to as L state) corresponding to the logic value “1” and High voltage state corresponding to the logical value “1”.
h voltage state (or power supply voltage state; hereinafter referred to as H state).

[0004] Further, the L-state or H-state output from the output circuit of the logic gate is performed by a switching operation of a transistor.

[0005] For example, TTL (transistor
transistorlogic) circuits, LSTT
L (lowpower schottky TTL)
In the circuit, a bipolar transistor is used in an output circuit that switches output states. Also, MOS(
metal oxide semiconductor
) In a digital circuit, a MOS FET (first effect) is used in the output circuit that switches the output state.
transistor) transistor (hereinafter simply referred to as M
It is called an OS transistor. Depending on the structure, a P-channel MOS transistor or an N-channel MOS transistor is used.

Conventionally, in such an output circuit that drives the output by the switching operation of a transistor, in order to perform the switching operation at a higher speed, the impedance of the output transistor used for this switching has been lowered.

However, by lowering the impedance of the output transistor, a large current flows through the output transistor to drive a large load capacitance at the moment the output is switched by a switching operation. The generation of such peak current generates power supply noise and ground noise on the power supply line and ground line that supply power to this output circuit, causing malfunctions in other logic circuits that use this power supply. .

Furthermore, in an output buffer circuit using a P-channel MOS transistor that switches the output to the H state and an N-channel MOS transistor that switches the output to the L state, the output of the output buffer circuit changes from the L state to the H state. When the logic state changes from the H state to the L state, both the P channel MOS transistor and the N channel MOS transistor become on state or almost on state. There is a problem in that a through current occurs from the power supply to the ground.

In Japanese Patent Laid-Open No. 63-31217, the turn-on timing of each of the aforementioned P-channel MOS transistor and N-channel MOS transistor used in the output buffer circuit is made gentler than the turn-off timing of the other transistor. A technique has been disclosed to do this. That is, the output of the output buffer circuit is L.
When the logic state changes from the high state to the high state, the N-channel MOS transistor is quickly turned off, while the P-channel MOS transistor is slowly turned on. On the other hand, when the logic state of the output of the output buffer circuit changes from the H state to the L state, the P channel MOS transistor is quickly turned off, while the N channel MOS transistor is slowly turned on.

According to the technique disclosed in Japanese Patent Laid-Open No. 63-31217, it is possible to prevent both the P-channel MOS transistor and the N-channel MOS transistor used for the output of the output buffer circuit from being in the on state or almost on state. It is possible to reduce the through current from the power supply to ground. Further, by slowing down the turn-on timing of the P-channel MOS transistor and N-channel MOS transistor used for these outputs, it is possible to slow down the current change of the signal output from the output buffer. Further, the change in current consumption of this output buffer circuit becomes gentle, and power supply noise and ground noise can also be reduced.

[0011]

However, in the above-mentioned Japanese Patent Application Laid-Open No. 63-31217, when the rise or fall of the input signal input to the output buffer circuit is gradual, the output of the output buffer circuit is The turn-off timing of the P-channel MOS transistor and the N-channel MOS transistor used in this case also becomes slow.

At this time, the degree to which the turn-off of the P-channel MOS transistor becomes gradual and the degree to which the turn-off of the N-channel MOS transistor becomes gradual differs from each other as described in Japanese Patent Laid-Open No. 63-31217. If the turn-on timing of the other transistor is longer than the turn-off timing, a problem arises in that a through current is generated from the power supply to the ground.

That is, these P-channel MOS transistors and N-channel MOS transistors are activated when the logic state of the output of the output buffer circuit changes from the L state to the H state, or when the logic state of the output of the output buffer circuit changes from the H state to the L state. At the time of switching, both are almost in an on state, causing a problem that a through current occurs from the power supply to the ground.

The present invention has been made to solve the above-mentioned problems of the conventional art. In an output buffer circuit using stage transistors, when the logic state of the output of the output buffer circuit changes from the L state to the H state, or from the H state to the L state, these first and final stages Reduces the through current from the power supply to the ground due to both the transistor and the second final stage transistor being on or almost on, thereby reducing power consumption and temperature rise due to Joule heat. The purpose is to provide an output buffer circuit.

[0015]

[Means for Accomplishing the Object] The present invention provides an output buffer circuit using a final stage transistor including a first final stage transistor that switches the output to an H state and a second final stage transistor that switches the output to an L state. In this step, the first final stage transistor is switched from off to on by utilizing a transient transition of the voltage or current of the input signal that occurs when the logic state of the input signal is switched, and the second final stage transistor is switched from off to on. The second final stage transistor is switched from OFF to OFF by using a first pre-driver that delays the switching from OFF to OFF, and a transient transition of the voltage or current of the input signal that occurs when the logic state of the input signal changes. a second pre-driver that delays switching from on to off compared to switching from on to off of the first final stage transistor;
The above object is achieved by shortening the time during which both the final stage transistor and the second final stage transistor are in the on state, or by preventing both from being in the on state.

Furthermore, a Schmitt trigger circuit in a broad sense may be used for the first pre-driver or the second pre-driver.

[0017]

[Operation] The present invention provides the following effects when the logic state of the input signal input to the output buffer circuit changes, that is, when the logic state changes from the L state to the H state or from the H state to the L state. This was done by focusing on the fact that a transient transition occurs in the voltage or current of the input signal as the logic state changes.

FIG. 1 is a block diagram showing the gist of the present invention.

In FIG. 1, reference numeral T1 is a first final stage transistor of the present invention, and as an example, a P channel M
An OS transistor is shown. Further, reference numeral T2 is a second final stage transistor of the present invention, and an N-channel MOS transistor is shown as an example.

Further, in FIG. 1, reference numeral 10 indicates a first predriver of the present invention, and this first predriver 10
The threshold voltage from L state to H state is VTHH
1, and the threshold voltage from the H state to the L state is shown as VTHL1. Further, reference numeral 20 denotes a second pre-driver of the present invention, and the threshold voltage of this second pre-driver 20 from the L state to the H state is VTHH2.
The threshold voltage from the H state to the L state is shown as VTHL2.

In the present invention, the magnitudes of the threshold voltage VTHH1 and threshold voltage VTHL1 of the first pre-driver and the threshold voltage VTHH2 and threshold voltage VTHL2 of the second pre-driver are expressed by the following equation. By doing so, the switching from OFF to ON of the first final stage transistor T1 used for the output of the output buffer circuit is as follows.
This is delayed compared to the switching from on to off of the second final stage transistor T2. Further, the switching from off to on of the second final stage transistor T2 is delayed compared to the switching from on to off of the first final stage transistor T1.

[0022] Below, these threshold voltages VTH
The expression of the condition for the relationship between H1, VTHL1, VTHH2, and VTHL2 is expressed as follows:
0, the first final stage transistor T1, and the second final stage transistor T2.

(A) The switching timing of the first final stage transistor from off to on is the threshold voltage VTHH1.
and the switching timing of the second final stage transistor from off to on depends on the threshold voltage VTHL2.

[0024]

(B) The switching timing of the first final stage transistor from off to on is the threshold voltage VTHL1.
and the switching timing of the second final stage transistor from off to on depends on the threshold voltage VTHH2.

[0026]

(C) The switching timing of the first final stage transistor from off to on is the threshold voltage VTHH1.
and the switching timing of the second final stage transistor from off to on depends on the threshold voltage VTHH2.

[0028]

(D) The switching timing of the first final stage transistor from off to on is the threshold voltage VTHL1.
and the switching timing of the second final stage transistor from off to on depends on the threshold voltage VTHL2.

[0030]

In this way, the switching from off to on of the first final stage transistor used for the output of the output buffer circuit is delayed compared to the switching from on to off of the second final stage transistor. At the same time, it is possible to delay the switching from off to on of the second final stage transistor compared to the switching from on to off of the first final stage transistor.

As shown in FIGS. 2 and 3, this reduces the time during which both the first final stage transistor and the second final stage transistor are in the on state, or prevents both of them from being in the on state. It is possible to prevent this.

FIGS. 2 and 3 are graphs showing an example of the input signal of the output buffer circuit of the present invention, the output signal of each predriver, and the on/off state of each final stage transistor.

In FIGS. 2 and 3, symbol a indicates the waveform of the signal input to the output buffer circuit. That is, the waveform signal indicated by the symbol a is the first
This is a signal input to the input of the pre-driver and the second pre-driver.

In the on/off state of the final stage transistor shown in the lower part of FIG. 2, the switching timing of the first final stage transistor from on to off depends on the threshold voltage VTHH1, and This is a case where the switching timing of the second final stage transistor from off to on depends on the threshold voltage VTHL2. That is, the conditions of equations (1a) and (1b) described above are complied with.

[0036] Also, the waveform signal indicated by symbol b in Fig. 2 is as follows:
As shown in FIG. 1 described above, this is the waveform of the signal output from the first predriver 10 whose output is connected to the gate of the first final stage transistor T1, which is a P-channel MOS transistor. Also, the waveform signal of symbol c in FIG. 2 is as follows:
The second transistor, which is the N-channel MOS transistor in FIG.
The second transistor output to the gate of the final stage transistor T2
This is a waveform of a signal output from the predriver 20.

In FIG. 2, the threshold voltage VTHH1 and threshold voltage VTHL1 of the first pre-driver and the threshold voltage VTHH2 and threshold voltage VYHL2 of the second pre-driver have the following relationship, for example.

VTHH1=VTHH...(5a)VTH
L1=VTH...(5b)VTHH2
=VTH...(5c)VTHL2=V
THL...(5d)

[0039] Therefore,
The threshold voltage VTHH of these first predrivers
1. In the threshold voltages VTHH2 and VTHL2 of VTHL1 and the second pre-driver, the above-mentioned (1a
) and the relationship (1b) hold true.

Note that the voltage VTH is a normal threshold voltage, and the voltage VTHH is a normal threshold voltage.
This is a threshold voltage higher than TH, and the voltage VTHL is a threshold voltage lower than this threshold voltage VTH.

That is, these threshold voltages VTH,
There is a relationship between VTHH and VTHL as shown in the following equation.

VTHH>VTH>VTHL...(
6)

Further, in the solid line showing the on/off state of the final stage transistor shown in the lower part of FIG. 3, the switching timing of the first final stage transistor from off to on depends on the threshold voltage VTHL1. Moreover, the timing at which the second final stage transistor is switched from off to on depends on the threshold voltage VTHH2.

[0044] Furthermore, the waveform of the signal indicated by the symbol e in FIG. 3 is the waveform of the signal output from the first pre-driver, and the waveform of the signal indicated by the symbol d in FIG. This is the case when the waveform is .

That is, the above-mentioned case (B) follows the conditions of the above-mentioned equations (2a) and (2b).

As explained above, according to the present invention, the switching of the first final stage transistor from off to on is performed by
The switching from on to off of the second final stage transistor is delayed compared to the switching from on to off, and the switching from off to on of the second final stage transistor is delayed compared to the switching from on to off of the first final stage transistor. By doing so, the time during which both the first final stage transistor and the second final stage transistor are in the on state is shortened, or
Alternatively, it is possible to prevent both from turning on.

Furthermore, in the present invention, even if the transient transition of the voltage or current at the time of switching the logic state of the input signal input to the output buffer circuit becomes excessively gradual, This only increases the time during which both the first final stage transistor and the second final stage transistor are in the OFF state, and the P channel M.O.
There is no possibility that both the S transistor and the N channel MOS transistor are in the on state or almost on state.

[0048]

Embodiments Hereinafter, embodiments of the present invention will be explained in detail with reference to the drawings.

In the first embodiment of the present invention, the Schmitt trigger circuit shown in the circuit diagram of FIG. 4 is added to the first predriver 10 and the second predriver 20 of the output buffer circuit shown in the block diagram of FIG. It uses

The first final stage transistor T1 is a P-channel MOS transistor, and the second final stage transistor T2 is an N-channel MOS transistor.

FIG. 4 is a circuit diagram of a Schmitt trigger circuit used in the first pre-driver and second pre-driver of the first embodiment of the present invention.

In FIG. 4, input INA is the input of the predriver, and output OUTA is the output of the predriver. Further, symbols T10, T11, and T15 are P-channel MOS transistors. Code T20, T21, T
25 is an N-channel MOS transistor.

P-channel MOS transistors T10, T
11 is the output OUT when the input INA is in the L state.
A is switched to the power supply VDD to turn it on.

N-channel MOS transistors T20, T
21 is the output OUT when the input INA is in the H state.
A is switched to ground GND to turn it on.

Furthermore, the hysteresis characteristic in this Schmitt trigger circuit is that the P-channel MOS transistor T1
5 and an N-channel MOS transistor T25.

In the Schmitt trigger circuit of FIG. 4, the threshold voltage from the L state to the H state and the threshold voltage from the H state to the L state are
It can be determined by the respective characteristics of S transistors T10, T11, T15 and N channel MOS transistors T20, T21, T25.

That is, the average value of the threshold voltage from the L state to the H state and the threshold voltage from the H state to the L state is mainly determined by the P channel MOS transistors T10,
T11 and N-channel MOS transistors T20 and T2
It is determined in relation to 1. Moreover, the systeresis width in the hysteresis characteristic of this Schmitt trigger circuit is mainly determined by the P-channel MOS transistor T15 and the N-channel MOS transistor T15.
It can be determined by the S transistor T25.

Therefore, the Schmitt trigger circuit shown in FIG.
0, the conditions of equation (1a) and (1b
) are set so that both the conditions of the equation hold true.

That is, as a matter of course, the characteristics of the Schmitt trigger circuit of FIG. 4 used for the first predriver 10 of FIG. 1 and the characteristics of the Schmitt trigger circuit of FIG. 4 used for the second predriver 20 of FIG. 1 are as follows. They are different. That is, the threshold voltage from the L state to the H state is different from the threshold voltage from the H state to the L state.

According to the first embodiment of the present invention,
By utilizing a transient transition in the voltage or current of the input signal that occurs when the logic state of the input signal of the output buffer circuit changes, the first final stage transistor is switched from off to on, and the second final stage transistor is switched from off to on. It is possible to realize a first pre-driver that delays the switching from on to off compared to the switching from on to off.

Similarly, the second final stage transistor is switched from off to on by utilizing the transient transition of the voltage or current of the input signal that occurs when the logic state of the input signal of the output buffer circuit changes. a second transistor that delays the switching from on to off of the first final stage transistor;
A predriver can be realized.

Therefore, it is possible to prevent both the first final stage transistor and the second final stage transistor from being turned on.

The output buffer circuit of the second embodiment of the present invention is the first output buffer circuit of the output buffer circuit shown in the block diagram of FIG.
The pre-driver 10 uses a Schmitt trigger circuit in a broad sense as shown in the circuit diagram of FIG.
This circuit uses a Schmitt trigger circuit in a broad sense as shown in the circuit diagram.

FIG. 5 is a circuit diagram of a Schmitt trigger circuit in a broad sense used in the first predriver according to the second embodiment of the present invention.

In FIG. 5, the symbols INA, OUTA
, VDD, and GND are the same as those with the same symbols in FIG. 4 described above.

In FIG. 5, when the input INA is in the L state, the P-channel MOS transistor T10
The output OUTA is switched to the power supply VDD to turn it on. Further, the N-channel MOS transistors T20 and T21 switch the output OUTA to the ground GND to turn on when the input INA is in the H state.

Note that the hysteresis width of the hysteresis characteristic of the Schmitt trigger circuit shown in FIG.
It is composed of only an S transistor T25 (the P channel MOS transistor T15 in FIG. 4 described above is not used).

The Schmitt trigger circuit of FIG. 5 used for the first predriver 10 of FIG. 1 has a threshold voltage VTHH1 of the first predriver greater than a threshold voltage VTHH2 of the second predriver, and This was done by focusing on the fact that the threshold voltage VTHL1 of the second pre-driver is larger than the threshold voltage VTHL2 of the second pre-driver.

Therefore, in the Schmitt trigger circuit shown in FIG. 5, the number of P-channel MOS transistors can be reduced by one compared to the Schmitt trigger circuit shown in FIG. 4 described above.

FIG. 6 is a circuit diagram of a Schmitt trigger circuit used in the second predriver according to the embodiment of the present invention.

In FIG. 6, the symbols INA, OUTA
, VDD, and GND are the same as those with the same symbols in FIG. 4 described above.

In the Schmitt trigger circuit of FIG. 6, P channel MOS transistors T10 and T11 are
When the input INA is in the L state, the output OUTA is switched to the power supply VDD to turn it on. Further, the N-channel MOS transistor T20 has an input IN
When A is in H state, output OUTA is connected to ground GN
D is turned on to turn it on.

In the Schmitt trigger circuit of FIG. 6, hysteresis characteristics are obtained by the P-channel MOS transistor T15.

That is, the threshold voltage VTHH2 of the second pre-driver is lower than the threshold voltage VTHH1 of the first pre-driver, and the threshold voltage VTHL2 of the second pre-driver is lower than the threshold voltage VTHL1 of the first pre-driver. This is what we focused on.

Therefore, by using the Schmitt trigger circuit shown in FIG. 6 as the second predriver of the second embodiment of the present invention, the second pre-driver N in predriver 20
The number of channel MOS transistors can be reduced by one.

As explained above, the second embodiment of the present invention can also provide the same effects as the first embodiment of the present invention described above.

Furthermore, according to the second embodiment of the present invention,
Compared to the first embodiment of the present invention described above, it is also possible to obtain the effect that the number of MOS transistors used in the first pre-driver 10 and the second pre-driver 20 can be reduced by two in total.

[0078]

[Effects of the Invention] As explained above, according to the present invention, a final stage transistor including a first final stage transistor that switches the output to the H state and a second final stage transistor that switches the output to the L state is used. In the output buffer circuit, when the logic state of the output of the output buffer circuit changes from the L state to the H state or from the H state to the L state, the first final stage transistor and the second final stage transistor Both stage transistors are in the on state,
Alternatively, it is possible to reduce the through current from the power supply to the ground due to the almost on state, thereby achieving the excellent effect of reducing power consumption and temperature rise due to Joule heat.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the gist of the present invention.

FIG. 2 is a graph showing an example of the input signal of the output buffer circuit of the present invention, the output signal of each predriver, and the on/off state of each final stage transistor.

FIG. 3 is a graph showing an example of the input signal of the output buffer circuit of the present invention, the output signal of each predriver, and the on/off state of each final stage transistor.

FIG. 4 is a circuit diagram of a Schmitt trigger circuit used in a first pre-driver and a second pre-driver according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a Schmitt trigger circuit used in a first predriver according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a Schmitt trigger circuit used in a second predriver according to a second embodiment of the present invention.

[Explanation of symbols]

10...First predriver, 20...Second predriver, T1...First final stage transistor, T2...Second final stage transistor, T10, T11, T15...P channel MOS transistor, T20, T21, T25... N channel MOS IN...Input of the output buffer circuit, OUT...Output of the output buffer circuit, INA...Input of the pre-driver, OUTA...Output of the pre-driver, VDD...Power supply (power supply voltage), GND...Ground, VTH...Normal threshold voltage , VTHH1, VTHH2...Threshold voltage from L state to H state of input signal, VTHL1, VTHL2...Threshold voltage from H state to L state of input signal, VTH, VTHH, VTHL...Threshold voltage, t
1 to t4, t11 to t14...time.

Claims (2)

[Claims] Claims: 1. In an output buffer circuit using a final stage transistor including a first final stage transistor that switches the output to an H state and a second final stage transistor that switches the output to an L state, the logic state of an input signal is changed. Compare the switching from off to on of the first final stage transistor to the switching from on to off of the second final stage transistor by using a transient transition of the voltage or current of the input signal that occurs at the time of switching. The switching of the second final stage transistor from OFF to ON is controlled by using the first pre-driver to delay and the transient transition of the voltage or current of the input signal that occurs when the logic state of the input signal is switched. A second pre-driver that delays the switching from on to off of the first final stage transistor is used to shorten the time during which both the first final stage transistor and the second final stage transistor are in the on state. An output buffer circuit characterized in that the output buffer circuit prevents the output buffer circuit from turning on or both on. 2. The output buffer circuit according to claim 1, wherein the first pre-driver or the second pre-driver uses a Schmitt trigger circuit in a broad sense.