JPH04227163A - Encoding data processor - Google Patents

Abstract

PURPOSE:To execute a fast quantizing arithmetic operation with a small circuit scale by providing an encoding data processor equipped with a quantization means which substitutes difinite number of levels for a signal changing successively. CONSTITUTION:Since data is inputted from an LSB, one time unit delay means left shift. In such a case, a binary point is neglected, and output by one time unit delay is reduced to 1/512, therefore, the input of a full-adder 32 shown in 3 is 1/256 and 1/512. and it follows that the one time unit delay occurs in the adder 32, and the output goes to (1/128+1/256). The output of 4 goes to (1/64+1/128+1/256) and that of 5 to (1/32+1/64+1/128+1/256) by repeating a similar operation, thereby, an expected value can be obtained. A quantizing arithmetic operation by a quantization table is realized by a serial circuit, which enables the circuit scale of the whole quantizer to be remarkably reduced.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to an encoded data processing device used for image data compression processing, etc., and more specifically, an encoded data processing device having a quantization device that performs quantization operations during encoding. Regarding equipment.

0002

2. Description of the Related Art DCT (discrete cosine transform) is becoming the mainstream of high-efficiency encoding technology for images based on ISDN and CD-ROM. Not limited to this DCT, if the average number of bits per pixel is reduced by high-efficiency encoding, the quality of the image deteriorates, and if the compression rate is increased, the image quality deteriorates. The problem when compressing the current standard television signal to 1.5 Mbit/s is:
These are deterioration of the contour portion and block distortion occurring in block units (for example, 8×8 pixels) processed by DCT. When reproducing pixels by inverse transformation, all DCT outputs in a block are linearly summed, but if there is information loss in even one of the 64 DCT outputs of a block consisting of 8 x 8 pixels, Deterioration occurs in the reproduced pixels of the entire block.

[0003] Therefore, in order to reduce such block distortion as much as possible, reference document IEEE TRANSAC
TIONS ON ACUSTICS,SPEECH
, AND SIGNAL PROCESSING. V.O.
L. 37. NO. 4. APRIL1989(The L
OT Transform Coding Without
ut Blocking Effects, HENRIQ
UE S. MALVAR, DAVID H. STAEL
The LOT operation disclosed in IN) has been proposed. Figure 9
1 shows a LOT arithmetic device that performs this LOT arithmetic processing, and is a block diagram of a one-dimensional LOT. In FIG. 9, 1 is a LOT calculation device, 2 and 3 are DCT devices, and various calculation units shown in FIGS. 10 to 13 are connected to the DCT devices 2 and 3. Here, Figure 10 shows subtraction c
The calculation that shows =a+(-b) is shown in Figure 11 as addition c=a+b.
FIG. 12 shows the calculation showing the predetermined gain (for example, 1/2
), and FIG. 13 shows the calculation for vector rotation. The outputs of the DCT devices 2 and 3 are divided into even (even number) outputs 0, 2, 4, 6 and odd (odd number) outputs 1, 3, 5, 7, and are added and subtracted, and finally only the odd number components are added and subtracted. The data is vector-rotated by the butterfly calculator shown in FIG. 13 and becomes LOT data. In the one-dimensional LOT configuration shown in FIG. 9, 16 pixels (X0 to X7, X0' to X7'
), 8 data (Y0 to Y
The output of 7) is obtained. That is, at the first stage of input, a one-dimensional DCT operation is performed to obtain 16 data, and after various operations are performed on these 16 data, vector rotation is performed to finally obtain 8 data. Since this LOT operation is one-dimensional,
The output is 8x16 for a 16x16 input pixel, and the vertical and horizontal directions are switched again and a similar LOT operation is performed to obtain 8x8 data.

FIG. 14 is a block diagram of an encoded data processing device 11 using the LOT calculation device 1 shown in FIG. In FIG. 14, the image data stored in the image data memory 12 is subjected to two-dimensional DCT processing by the DCT calculation device 13.
It is processed and output to the LOT calculation device 1. The LOT calculation device 1 consists of the DCT devices 2 and 3 shown in FIG.
A one-dimensional (horizontal) LOT operation is performed on the data input from the CT operation device 13, and data for one block line is stored in the block line buffer A14 for the LOT operation. After the operation for one block line is completed, the same operation is performed and the block line buffer B1 is
Store data in 5. Here, the DCT calculation device 13 is
After temporarily stopping the operation, the LOT calculation device 1 performs a one-dimensional LOT calculation in the vertical direction on the data in the block line buffer A14 and the block line buffer B15, outputs the data to the quantization device 16, and outputs the data to the quantization device 16. 16 quantizes the data and outputs the quantized data to compressed data memory 17. Again, the DCT calculation device 13 and the LOT calculation device 1 perform DCT,
A LOT operation is performed and data for one block line is written into the block line buffer A14. Then, a vertical LOT operation is performed on the block line buffer B15 and the block line buffer A14 to perform quantization. Thereafter, the block line buffers are repeatedly switched to process one screen. Also, in the reverse direction, image data memory 12⇔compressed data memory 17, D
CT⇔Inverse quantization, LOT⇔ILOT, Quantization⇔IDCT
The basic operation is the same, just by changing .

FIG. 15 shows the operation of the quantization device 16 in AL
It is a figure which shows the circuit structure in the case of carrying out using U. That is, the conventional quantization circuit has an ALU as shown in FIG.
21, and the memory of 22 includes D
Contains blocks of CT-processed image data, 2
The memory No. 3 contains a quantization table as shown in FIG. 1, which will be described later. The ALU 21 reads the data, performs arithmetic operations, and outputs the result to the memory 24.

[0006]

[Problem to be Solved by the Invention] However, since such a quantization device is configured to use an ALU to perform a LOT operation, the ALU shown in FIG.
In the case of a configuration using the LU 21, there are problems in that the circuit scale becomes very large due to the division and the execution time becomes long. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an encoded data processing device that can perform high-speed quantization operations with a small circuit scale.

[0007]

[Means for Solving the Problems] In order to achieve the above object, an encoded data processing apparatus according to the present invention is an encoded data processing apparatus equipped with quantization means for converting a continuously changing signal into a finite number of levels. The quantization means is configured to perform serial operations in which data is sequentially moved using a predetermined clock.

[0008]

[Operation] The operation of the present invention is as follows. The quantization operation is performed by a serial operation that sequentially moves data using a predetermined clock. Therefore, high-speed quantization can be performed with a very small circuit scale.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on the drawings. 1 to 11 are diagrams showing an embodiment of an encoded data processing device according to the present invention.

First, the configuration will be explained. FIG. 1 is a diagram showing a quantization table of a quantization device. The quantization operation itself is
For a data block subjected to DCT processing, each component of the quantization table is divided during quantization and multiplied during inverse quantization. Here, considering division during quantization, since division is multiplication of reciprocal numbers, this reciprocal number is approximated by the sum of powers of 2 (that is, 2 raised to the nth power). This approximation is determined based on the required accuracy. FIG. 2 is an example of approximating the quantization table of FIG. 1, and the values do not necessarily have to be the values shown in FIG. For example, 17 is shown in Equation 1. (Formula 1) 17⇒1/17≒1/32+1/64+1/1
28+1/256

The reason for expressing the sum (difference) of powers of 2 as shown in FIG. 2 is to realize calculation by a serial circuit. That is, in FIG. 3, if the reference numeral 31 represents a 1 time unit delay consisting of an FF (flip-flop) whose output is delayed by 1 clock with respect to the input, then the output passing through the 1 time unit delay 31 and 1 When compared with the output that comes out directly without passing through the time unit delay 31, the former is one clock slower than the latter. Here, the 1 time unit delay 31 is like a line of shift registers, and for example, assuming that data is input in order from the LSB side, the fact that it comes out 1 clock later means that it has been doubled. means. Similarly, if you want to multiply by 8, you can line up 3 of the 1 time unit delays 31 as shown in FIG. 4 and delay them by 3 clocks, and the result will be 23 times by 8. In this embodiment, a serial circuit is realized by combining the above units and performing addition and subtraction.

FIG. 5 shows a serial calculation configuration in which calculation is performed from the LSB, and FIG. 5 is an example in which 17 is realized by a serial calculation circuit. Also, 31 in Figure 5 is F
1 time unit delay consisting of F, 32 is added (
1-time unit delay full adder (internal carry) that performs a+b). In Figure 5, the bits that appear with a 1 time unit delay are 1/
If it is 512, it is 1/256, 1/128, 1/64, 1
/32 are 2, 3, 4, and 5 time unit delays, respectively. Further, it is assumed that a one time unit delay occurs in the full adder 32 and is cleared in the initial state.

Next, the operation of this quantization arithmetic device will be explained. In Figure 5, data is input from the LSB, so
A one time unit delay means a left shift, or a doubling. Here, since the binary point is ignored and the output with 1 time unit delay is set to 1/512, the input of the full adder 32 of 3 is 1/256 and 1/5
12, this full adder 32 causes a 1 time unit delay, and the output is (1/128+1
/256). By repeating the same operation, the output of 4 becomes (1/64+1/128+1/256) and the output of 5 becomes (1/32+1/64+1/128+1/256), so that the expected values can be obtained.

FIG. 6 shows a block diagram of an arithmetic unit that implements arithmetic operations on each component of the quantization table with the above-described configuration. Since the output in this case is 9 systems,
One of them may be selected using a 9to1 selector (not shown). In this way, the quantization operation using the quantization table can be expressed by a serial circuit as shown in FIG. 6, and the quantization operation can be realized by the serial operation. In this case, each unit 31, 32 is an FF
Since this can be realized with about one extremely small circuit, the circuit scale of the entire quantization device can be significantly reduced. Also, during inverse quantization, serial operations similar to those during quantization described above can be performed. FIG. 7 is a circuit configuration diagram in which the numerical values shown in FIG. 8 are performed by serial calculation.
A serial operation similar to that in FIG. 6 is executed. For example, 17
The serial calculation is executed by thinking that 17⇒16+1. In this case, 1 is output with a 1 time unit delay.

As explained above, in this embodiment, the quantization operation is performed by serial operation, so that the conventional LOT operation using an ALU requires a very large circuit scale, but the circuit size is reduced to an extremely small FF. This can be realized by a serial circuit consisting of a combination of the above, making it possible to significantly reduce the circuit scale and to perform processing at high speed. Such a small circuit scale and high-speed quantization arithmetic device is suitable for application to an encoded data processing device that performs image compression and audio compression.

In this embodiment, each component of the quantization table is converted into a sum (difference) of powers of 2 (2 to the nth power), and a serial operation is performed using a serial circuit as shown in FIGS. 6 and 7. However, it goes without saying that any combination of units may be used as long as serial data processing is performed.

[0017] Furthermore, if a quantization operation is performed,
It is applicable to any quantization device. Furthermore, any type of data transformation may be used, such as FFT, CDT, etc.
Needless to say, the present invention can be applied to a quantization device for orthogonal data transformation such as LOT.

[0018]

According to the present invention, since the quantization calculation means performs serial calculation, the circuit scale can be significantly reduced and the processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a quantization table of a quantization calculation device according to the present invention.

FIG. 2 is a diagram showing an example of approximation for performing serial data processing of a quantization operation according to the present invention.

FIG. 3 is a diagram for explaining serial operations of the quantization operation device according to the present invention.

FIG. 4 is a diagram for explaining serial operations of the quantization operation device according to the present invention.

FIG. 5 is a circuit configuration diagram for explaining an example of serial operation of the quantization operation device according to the present invention.

FIG. 6 is a circuit configuration diagram for serially performing quantization operations in the quantization operation device according to the present invention.

FIG. 7 is a circuit configuration diagram for serially performing an inverse LOT operation in the quantization operation device according to the present invention.

FIG. 8 is a diagram for explaining the serial operation of the inverse LOT operation of the quantization operation device according to the present invention.

FIG. 9 is a configuration diagram of a conventional LOT calculation device.

FIG. 10 is a diagram showing an arithmetic unit for butterfly operation of a conventional LOT arithmetic device.

FIG. 11 is a diagram showing an arithmetic unit for butterfly operation of a conventional LOT arithmetic device.

FIG. 12 is a diagram showing an arithmetic unit for butterfly operation of a conventional LOT arithmetic device.

FIG. 13 is a diagram showing an arithmetic unit for butterfly operation of a conventional LOT arithmetic device.

FIG. 14 is a block diagram of a conventional image data processing device.

FIG. 15 is a circuit diagram using an ALU of a conventional quantization device.

[Explanation of symbols]

31 1 time unit delay

Claims (1)

[Claims] 1. An encoded data processing device comprising quantization means for converting a continuously changing signal into a finite number of levels, wherein the quantization means converts a continuously changing signal into a finite number of levels by a serial operation that sequentially moves data according to a predetermined clock. An encoded data processing device characterized by: