JPH06276101A - Quantization circuit - Google Patents

Abstract

PURPOSE:To obtain the quantization circuit of a reduced circuit scale, which executes at high speed. CONSTITUTION:A rounding constant X is stored in a rounding constant register 101 for inputting a positive number when a DCT coefficient R is positive and a rounding constant X is stored in a rounding constant register 102 for inputting a negative number when a DCT coefficient R is negative. A selecting circuit 103 selects a rounding constant for a positive or negative number by the code bit of a DCT coefficient R and inputs it to an adder 105. On the other hand, a multiplier 104 obtains the product of the DCT coefficient R and the inverse number A of a quantization threshold value. The adder 105 obtains (AR+X), a shifter 106 shifts it to right by S bits and a range limitting circuit 107 limits the range of a quantization coefficient to a specified value. Thereby, the DCT coefficient R is quantized by the quantization threshold value Q to obtain the result L rounded into an integer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantizing circuit used in an image data compressing device or the like.

[0002]

2. Description of the Related Art A method for compressing color and monochrome still images and moving images has been studied by international organizations such as ISO and CCITT, and has been reviewed by JPEG [Joint Photogr.
apic Experts Group] and MPEG
[Moving Picture Experts G
group] and H.H. 261 is standardized.

According to JPEG, a color still image is 1/8 to 1
This is a method of compressing to about / 100. It became an international standard draft in November 1991. FIG. 7 is a block diagram showing the encoding method. The input image 71 is input to the encoder 72. In the encoder 72, the input image 71 that has been input is input to the DCT unit 721 and DCT (discrete cosine transform)
Is done. Next, in the quantizer 722, the table 7
23, the output of the DCT section is quantized, and the entropy coding section 724 refers to the table 725 to entropy code the output of the quantization section 722. As a result, the compressed data 73 having the table and the header information is transferred to the transmission line 74.

MPEG is a method for compressing a color moving image. Digital recording medium such as CD-ROM (DS
M: Digital Storage Media). In November 1991, the draft recommendation (CD: Co
Mittee Draft). FIG. 8 is a block diagram showing the encoding method. The encoding circuit according to this method includes a predictor 88 that generates predicted image data having a small difference value from the input image data, and a subtractor 8 that subtracts the predicted image data output from the predictor 88 from the input image data.
9 and D that performs DCT operation on the difference output of the subtractor 89
A CT unit 81, a quantization unit 82 that quantizes the DCT coefficient output (C) of the DCT unit 81, and a VL that performs variable-length coding on the quantized coefficient output (QC) of the quantization unit 82.
C section 83, buffer section 84, inverse quantization section 85 that performs inverse quantization on the quantized coefficient output of quantization section 82, and inverse DCT section 86 that performs inverse DCT on the output of inverse quantization section 85.
And an adder 87 that adds the output of the inverse DCT unit 86 and the predicted image data output from the predictor 88 to generate new predicted image data.

H. H. 261 is a video conference / telephone coding system, which is recommended by CCITT Recommendation H.264. It is 261.
It became an International Standard (IS) in 1991. ISDN is assumed as a network, and moving images are transmitted at 64 k to 1.5 Mbit / sec. FIG. 9 is a block diagram showing the encoding method.

The coding circuit according to this method quantizes the output of the DCT converter 92 and the DCT converter, and outputs the quantizing index (q) of the transform coefficient, and the output of the quantizer 93. And an inverse DCT unit 95 for inverse DCT transforming the output of the inverse quantizer 94.
Of the switch 99 and the inverse DCT unit 95, an image memory 97 having a variable delay function for motion compensation that receives the output of the adder 96 and outputs a motion vector, and an image memory 97 Receives the output, improves the motion-compensated inter-frame prediction accuracy, outputs an on / off signal of the in-loop filter, an in-loop filter 98, 100 which negatively feeds back the output of the in-loop filter 98 to a video input, a switch 101 and a quantum. The encoding control unit 91 which controls the quantizer 93 and outputs the inter-frame / intra-frame identification flag (p), the transmission / non-transmission identification flag (t), and the quantizer type (qz).

The above three image compression methods commonly employ the method shown in FIG. That is, DCT [Discrete Co
[Sine Transform] 611 is performed to convert the DCT coefficient 622, and then the DCT coefficient 622 is quantized 612 to obtain a quantized coefficient 623.

The quantization process is individually defined for each image compression method, but each is composed of the following three steps.

(1) The DCT coefficient is divided by the quantization threshold. (Division processing) (2) Round the division result to an integer excluding the fractional part. (Rounding process) (3) Limit the rounded result to a value that does not exceed a specified range. (Binary range limiting process) However, the rounding process of (2) may be "rounding down" or "rounding down" depending on the image compression method.

For example, JPEG and H.264. The quantization in 261 is as follows. However, R is a DCT coefficient, L is a quantization coefficient, and Q is a quantization threshold value.

1) JPEG (8-bit mode) (-1
024 ≦ L ≦ 1023) L = R / Q The rounding method is rounding as shown in FIG. FIG. 2 shows that a number greater than or equal to 0.5 and less than 1.5 is rounded as 1.

2) H. 261 (-127 ≦ L ≦ 127) L = R / 2Q (Q: odd number) = (R + 1) / 2Q (Q: even number, R ≧ 0) = (R−1) / 2Q (Q: even number, R <0 The rounding method is rounding down as shown in FIG. FIG. 3 shows that a number greater than or equal to 1 and less than 2 is rounded as 1, for example.

The method of realizing the quantization is roughly classified into two, that is, the method performed by software and the method performed by hardware.

As shown in FIG. 4, the method implemented by software divides the DCT coefficient by the quantization threshold in step S41, and outputs it in steps S42, S43, and S44 corresponding to each of the positive and negative signs. The result is rounded to an integer value by the method defined in the image compression standard, and then the range limiting process is performed in step S45.

The method performed by hardware is the division processing of (1) of the quantization processing, and (a) the method of using a divider,
(B) A method is known in which the reciprocal of the quantization threshold is calculated in advance and the multiplier is used to multiply the DCT coefficient by the reciprocal thereof.

As for the rounding method (2) of the quantization processing, a dedicated circuit for "rounding down" and "rounding off" corresponding to the image compression method and a range limiting circuit are added. Figure 5 is a block diagram of the quantization processing hardware.
Shown in. The quantization circuit uses a quantized coefficient R and a quantization threshold Q.
, A code determination circuit 502 that receives the output of the division circuit 501, and a code determination circuit 50.
Decimal fractional truncation circuit 50 for positive numbers with the output of 2 as input
3, a fractional part truncation circuit 504 for negative numbers, a fractional part truncation circuit for positive numbers 503, and a range limiting circuit 505 which receives the output of the fractional part truncation circuit for negative numbers 504 as an input.

The division circuit 501 divides the quantized coefficient R by the quantization threshold value Q. The sign determination circuit 502 determines the sign of the division result. When the sign is positive, the fractional fractional part truncation circuit 503 for positive numbers performs the truncation process. If the sign is negative, the fractional part truncation circuit for negative numbers 504 performs the truncation process. The range limiting circuit 505 limits the range of the quantized coefficient to a predetermined value.

[0018]

In the conventional software implementation method, it is necessary to determine whether the DCT coefficient is positive or negative, and a plurality of steps of instructions are required. Therefore, there is a problem that the speed becomes slow.

Further, in the conventional hardware implementation method, the circuit scale becomes large and the execution speed is slow because of the rounding processing of (2) among the three steps for quantization described above. There was a problem.

An object of the present invention is to provide a quantizer circuit which has a high execution speed and a reduced circuit scale.

[0021]

The quantization circuit of the present invention comprises:
Holding means for holding a rounding constant for positive number input, holding means for holding a rounding constant for negative number input, and rounding constant selection for selecting one of a rounding constant for positive number input and a rounding constant for negative number input according to the positive / negative judgment of the input Means, multiplication means for inputting the inverse of the DCT coefficient and the quantization threshold and multiplying them, addition means for adding these with the output of the rounding constant selection means and the output of the multiplication means as input, and the addition means of the addition means. It is characterized by comprising shift means for inputting an output and subjecting the input value to shift processing, and range limiting means for limiting the range by using the output of the shift means as input.

[0022]

The rounding constant when the DCT coefficient is a positive number is stored in the rounding constant holding means for positive number input, and the rounding constant when the DCT coefficient is a negative number is stored in the rounding constant holding means for negative number input. The rounding constant selection means selects a rounding constant for positive numbers or negative numbers according to the sign bit of the DCT coefficient, and inputs it to one of the input terminals of the adding means. On the other hand, the product of the reciprocal of the DCT coefficient and the quantization threshold is obtained by the multiplication means,
The obtained result is input to the other input terminal of the adding means. The output of the adding means is shifted by the shifter means, and is limited within the range of the quantized coefficient by the range limiting means.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

When the DCT coefficient is R, the quantization threshold is Q, and the rounding function is F (x), the quantized coefficient L before the range limitation is expressed as follows.

L = F (R / Q) ... (Equation 1) Here, if A and S such that (1 / Q) = (A / 2 ^S ) ... (Equation 2) are selected, L = F (AR / 2 ^S ) ... (Equation 3) = F (AR >> S) ... (Equation 4) (where >> S is right-shifted by S bits in the two's complement representation). Here, when X is used as a rounding constant to round the value of L after multiplication into an integer, by changing the value of the rounding constant X, the DCT is calculated as follows.
It is possible to freely select the rounding method for the decimal part of the result obtained by dividing the coefficient R by the quantization threshold Q.

L = (AR + X) >> S ... (Equation 5) When R ≧ 0, X = 0: round down = A / 2: round off When R <0, X = 2 ^S −1: round down = It can be expressed as A / 2-1: rounding off.

FIG. 1 is a block diagram showing an example of the configuration of the quantization circuit of the present invention.

The quantizing circuit shown in FIG. 1 includes a rounding constant register 101 for positive number input and a rounding constant register 10 for negative number input.
2, a selection circuit 103 connected to the rounding constant registers 101 and 102, a multiplier 104 having the DCT coefficient R and the reciprocal A of the quantization threshold as inputs, a selection circuit 103 and a multiplier 104
The adder 105 connected to the shifter 106, the shifter 106 connected to the adder 105, and the range limiting circuit 107 connected to the shifter 106.

The rounding constant X when the DCT coefficient R in (Equation 5) is a positive number is used as a rounding constant register 10 for inputting a positive number.
The rounding constant X when the DCT coefficient R is a negative number is stored in the negative number input rounding constant register 102.

The selection circuit 103 selects a rounding constant for positive numbers or negative numbers according to the sign bit of the DCT coefficient R, and inputs it to the adder 105.

On the other hand, the multiplier 104 controls the DCT coefficient R
And the reciprocal A of the quantization threshold are obtained. Adder 105
Then, (AR + X) is obtained, the shifter 106 shifts it to the right by S bits, and the range limiting circuit 107 limits the range of the quantized coefficient to a predetermined value.

As a result, the calculation of (Equation 5) is realized and D
The CT coefficient R is quantized with the quantization threshold Q, and the result L rounded to an integer is obtained.

The quantizing circuit of the present embodiment has two conventional rounding constant registers, which is a conventional problem.
Higher execution speed in the software implementation method, one hardware implementation for various rounding methods for the decimal part in the hardware implementation method, and reduction in circuit scale compared to conventional methods Becomes

[0034]

The quantizing circuit of the present invention comprises rounding constant holding means for positive number input, rounding constant holding means for negative number input,
Since the rounding constant selecting means for selecting one of the rounding constant for positive number input and the rounding constant for negative number input according to the positive / negative judgment of the input, the multiplying means, the adding means, the shifting means and the range limiting means, The execution speed is high,
A quantizer circuit having a reduced circuit scale can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a quantization circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a rounding method by rounding.

FIG. 3 is an explanatory diagram of a rounding method by rounding down.

FIG. 4 is a conventional technique using software.

FIG. 5 is a conventional technique using hardware (when the rounding method is truncation).

FIG. 6 is a configuration diagram of an image compression method.

FIG. 7 is a block diagram of a JPEG encoding circuit.

FIG. 8 is a block diagram of an MPEG encoding circuit.

9: H. It is a block diagram of a H.261 system encoding circuit.

[Explanation of symbols]

 101 Rounding constant register for positive number input 102 Rounding constant register for negative number input 103 Selection circuit 104 Multiplier 105 Adder 106 Shifter 107 Range limiting circuit 611 DCT execution means 612 Quantization execution means 621 Image data 622 DCT coefficient 623 Quantization coefficient

Claims (1)

[Claims] 1. A holding means for holding a rounding constant for a positive number input, a holding means for holding a rounding constant for a negative number input, and one of a rounding constant for a positive number input and a rounding constant for a negative number input depending on whether the input is positive or negative. Rounding constant selection means to select,
A multiplication means for inputting the DCT coefficient and the reciprocal of the quantization threshold and multiplying them, an addition means for adding the outputs of the rounding constant selection means and the output of the multiplication means, and an output of the addition means The quantizing circuit is provided with: shift means for performing shift processing on the input value; and range limiting means for limiting the range with the output of the shift means as input.